FR2016448A1 - - Google Patents

Info

Publication number
FR2016448A1
FR2016448A1 FR6929205A FR6929205A FR2016448A1 FR 2016448 A1 FR2016448 A1 FR 2016448A1 FR 6929205 A FR6929205 A FR 6929205A FR 6929205 A FR6929205 A FR 6929205A FR 2016448 A1 FR2016448 A1 FR 2016448A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR6929205A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of FR2016448A1 publication Critical patent/FR2016448A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
FR6929205A 1968-08-27 1969-08-26 Withdrawn FR2016448A1 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB40863/68A GB1245441A (en) 1968-08-27 1968-08-27 Improvements in or relating to adders operating on variable fields within words

Publications (1)

Publication Number Publication Date
FR2016448A1 true FR2016448A1 (enExample) 1970-05-08

Family

ID=10416998

Family Applications (1)

Application Number Title Priority Date Filing Date
FR6929205A Withdrawn FR2016448A1 (enExample) 1968-08-27 1969-08-26

Country Status (3)

Country Link
US (1) US3683163A (enExample)
FR (1) FR2016448A1 (enExample)
GB (1) GB1245441A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2309925A1 (fr) * 1975-05-01 1976-11-26 Ibm Dispositif arithmetique numerique parallele presentant un nombre variable de zones arithmetiques independantes de largeurs et d'emplacement variables

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921144A (en) * 1971-05-18 1975-11-18 Ibm Odd/even boundary address alignment system
US3751650A (en) * 1971-06-28 1973-08-07 Burroughs Corp Variable length arithmetic unit
JPS58182754A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd 演算処理装置
US4914617A (en) * 1987-06-26 1990-04-03 International Business Machines Corporation High performance parallel binary byte adder
GB8904392D0 (en) * 1989-02-27 1989-04-12 Ibm An arithmetic logic unit for a graphics processor
US5197140A (en) * 1989-11-17 1993-03-23 Texas Instruments Incorporated Sliced addressing multi-processor and method of operation
FR2802660B1 (fr) 1999-12-21 2002-11-29 St Microelectronics Sa Procede pour effectuer des operations avec une arithmetique variable
US8495114B1 (en) * 2005-05-23 2013-07-23 The Mathworks, Inc. System and methods for determining attributes for arithmetic operations with fixed-point numbers
US8484262B1 (en) * 2005-12-22 2013-07-09 The Mathworks, Inc. System and methods for determining attributes for arithmetic operations with fixed-point numbers
US8464129B2 (en) * 2008-08-15 2013-06-11 Lsi Corporation ROM list-decoding of near codewords
FR3101981B1 (fr) * 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Extraction et insertion de mots binaires

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260840A (en) * 1961-12-28 1966-07-12 Ibm Variable mode arithmetic circuits with carry select
US3430202A (en) * 1964-10-07 1969-02-25 Bell Telephone Labor Inc Data processor utilizing combined order instructions
US3439347A (en) * 1966-12-13 1969-04-15 Gen Electric Sub-word length arithmetic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2309925A1 (fr) * 1975-05-01 1976-11-26 Ibm Dispositif arithmetique numerique parallele presentant un nombre variable de zones arithmetiques independantes de largeurs et d'emplacement variables

Also Published As

Publication number Publication date
DE1939946A1 (de) 1970-03-05
US3683163A (en) 1972-08-08
DE1939946B2 (de) 1972-11-02
GB1245441A (en) 1971-09-08

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Legal Events

Date Code Title Description
ST Notification of lapse