FR1489276A - Système de manipulation d'informations digitales - Google Patents

Système de manipulation d'informations digitales

Info

Publication number
FR1489276A
FR1489276A FR7977A FR06007977A FR1489276A FR 1489276 A FR1489276 A FR 1489276A FR 7977 A FR7977 A FR 7977A FR 06007977 A FR06007977 A FR 06007977A FR 1489276 A FR1489276 A FR 1489276A
Authority
FR
France
Prior art keywords
handling system
digital information
information handling
digital
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7977A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR1489276A publication Critical patent/FR1489276A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
FR7977A 1965-08-23 1966-07-29 Système de manipulation d'informations digitales Expired FR1489276A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US48168965A 1965-08-23 1965-08-23

Publications (1)

Publication Number Publication Date
FR1489276A true FR1489276A (fr) 1967-07-21

Family

ID=23912985

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7977A Expired FR1489276A (fr) 1965-08-23 1966-07-29 Système de manipulation d'informations digitales

Country Status (4)

Country Link
US (1) US3465132A (fr)
DE (1) DE1293188B (fr)
FR (1) FR1489276A (fr)
GB (1) GB1097909A (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3992696A (en) * 1975-06-27 1976-11-16 Bell Telephone Laboratories, Incorporated Self-checking read and write circuit
JPS5833577B2 (ja) * 1977-03-17 1983-07-20 富士通株式会社 集積回路
US4184630A (en) * 1978-06-19 1980-01-22 International Business Machines Corporation Verifying circuit operation
US4359771A (en) * 1980-07-25 1982-11-16 Honeywell Information Systems Inc. Method and apparatus for testing and verifying the operation of error control apparatus within a memory
US4410984A (en) * 1981-04-03 1983-10-18 Honeywell Information Systems Inc. Diagnostic testing of the data path in a microprogrammed data processor
US4429391A (en) 1981-05-04 1984-01-31 Bell Telephone Laboratories, Incorporated Fault and error detection arrangement
DE3404782A1 (de) * 1984-02-10 1985-08-14 Nixdorf Computer Ag, 4790 Paderborn Verfahren und schaltungsanordnung zum pruefen eines programms in datenverarbeitungsanlagen
US4794597A (en) * 1986-03-28 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Memory device equipped with a RAS circuit
JPH01180645A (ja) * 1988-01-13 1989-07-18 Hitachi Ltd 保守診断機構の自動検証方式
US5058112A (en) * 1989-07-31 1991-10-15 Ag Communication Systems Corporation Programmable fault insertion circuit
US7127646B1 (en) * 2000-06-07 2006-10-24 Lsi Logic Corporation System and method for generating real time errors for device testing

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2805278A (en) * 1951-09-04 1957-09-03 Nederlanden Staat Telegraph system
US2945915A (en) * 1958-01-28 1960-07-19 Strip Joseph Operational checkout of data handling equipment
US3027542A (en) * 1958-07-14 1962-03-27 Beckman Instruments Inc Automatic marginal checking apparatus
NL265706A (fr) * 1960-06-09
NL279117A (fr) * 1961-05-31
DE1169702B (de) * 1962-12-19 1964-05-06 Siemens Ag Schaltungsanordnung zur Ermittlung des Vollstaendigkeitskontrollsignals bei einer gesicherten UEbertragung oder Verarbeitung von im Drei-Exzess-Code binaer verschluesselten Dezimalziffern oder durch solche dargestellten Informationen, vorzugsweise in elektronischen Datenverarbeitungsanlagen
US3257546A (en) * 1963-12-23 1966-06-21 Ibm Computer check test

Also Published As

Publication number Publication date
DE1293188B (de) 1969-04-24
US3465132A (en) 1969-09-02
GB1097909A (en) 1968-01-03

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