FI946196A0 - Menetelmä kahdentyyppisten aikavälien erottamiseksi sarjamuotoisessa digitaalisessa bittivirrassa bittivirtavastaanottimessa - Google Patents

Menetelmä kahdentyyppisten aikavälien erottamiseksi sarjamuotoisessa digitaalisessa bittivirrassa bittivirtavastaanottimessa

Info

Publication number
FI946196A0
FI946196A0 FI946196A FI946196A FI946196A0 FI 946196 A0 FI946196 A0 FI 946196A0 FI 946196 A FI946196 A FI 946196A FI 946196 A FI946196 A FI 946196A FI 946196 A0 FI946196 A0 FI 946196A0
Authority
FI
Finland
Prior art keywords
bitstream
separating
types
time slots
serial digital
Prior art date
Application number
FI946196A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI946196A (fi
Inventor
Erik Oscar Abefelt
Lars Goeran Schyman
Carl Peter Birger Lundh
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of FI946196A0 publication Critical patent/FI946196A0/fi
Publication of FI946196A publication Critical patent/FI946196A/fi

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • H04M11/068—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors using time division multiplex techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
FI946196A 1992-07-01 1994-12-30 Menetelmä kahdentyyppisten aikavälien erottamiseksi sarjamuotoisessa digitaalisessa bittivirrassa bittivirtavastaanottimessa FI946196A (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9202031A SE500427C2 (sv) 1992-07-01 1992-07-01 Sätt och system för att i seriella digitala bitflöden urskilja minst två typer av tidsluckor i en mottagare av flödet
PCT/SE1993/000540 WO1994001952A1 (en) 1992-07-01 1993-06-17 A method of distinguishing in serial digital bit streams between at least two types of time slots in a bit stream receiver

Publications (2)

Publication Number Publication Date
FI946196A0 true FI946196A0 (fi) 1994-12-30
FI946196A FI946196A (fi) 1994-12-30

Family

ID=20386671

Family Applications (1)

Application Number Title Priority Date Filing Date
FI946196A FI946196A (fi) 1992-07-01 1994-12-30 Menetelmä kahdentyyppisten aikavälien erottamiseksi sarjamuotoisessa digitaalisessa bittivirrassa bittivirtavastaanottimessa

Country Status (14)

Country Link
US (1) US5450398A (ko)
EP (1) EP0648396B1 (ko)
KR (1) KR100233619B1 (ko)
CN (1) CN1066877C (ko)
AU (1) AU671655B2 (ko)
DE (1) DE69327957T2 (ko)
DK (1) DK0648396T3 (ko)
ES (1) ES2144006T3 (ko)
FI (1) FI946196A (ko)
GR (1) GR3033045T3 (ko)
MX (1) MX9303940A (ko)
NO (1) NO945055L (ko)
SE (1) SE500427C2 (ko)
WO (1) WO1994001952A1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09233054A (ja) * 1996-02-27 1997-09-05 Oki Electric Ind Co Ltd 復号装置
US6603771B1 (en) 1999-07-02 2003-08-05 Cypress Semiconductor Corp. Highly scalable architecture for implementing switch fabrics with quality of services
US6584517B1 (en) 1999-07-02 2003-06-24 Cypress Semiconductor Corp. Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices
US6625177B1 (en) 1999-08-09 2003-09-23 Cypress Semiconductor Corp. Circuit, method and/or architecture for improving the performance of a serial communication link
US6628656B1 (en) 1999-08-09 2003-09-30 Cypress Semiconductor Corp. Circuit, method and/or architecture for improving the performance of a serial communication link
US6738935B1 (en) * 2000-02-07 2004-05-18 3Com Corporation Coding sublayer for multi-channel media with error correction
JP3780419B2 (ja) * 2004-03-09 2006-05-31 セイコーエプソン株式会社 データ転送制御装置及び電子機器
EP1596262B1 (de) * 2004-05-10 2007-04-11 Siemens Aktiengesellschaft Sicherheitsgerichtete Übertragung von Daten
DE102005010820C5 (de) * 2005-03-07 2014-06-26 Phoenix Contact Gmbh & Co. Kg Kopplung von sicheren Feldbussystemen
CN102707226A (zh) * 2012-07-06 2012-10-03 电子科技大学 一种红外焦平面读出电路的行控制电路的检测电路
US9007014B2 (en) * 2012-10-19 2015-04-14 The Board Of Trustees Of The University Of Illinois System and method for compensating for high frequency application of ripple correlation to minimize power losses in induction machines
KR102204877B1 (ko) * 2019-09-06 2021-01-18 광운대학교 산학협력단 광 통신 기반의 고속 전송 장치 및 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156111A (en) * 1977-05-18 1979-05-22 Honeywell Information Systems Inc. Apparatus for transition between network control and link control
NL7707540A (nl) * 1977-07-07 1979-01-09 Philips Nv Inrichting voor het koderen van signalen die over een aantal kanalen worden verdeeld.
FR2476880A1 (fr) * 1980-02-27 1981-08-28 Ibm France Procede et dispositif pour multiplexer un signal de donnees et plusieurs signaux secondaires, procede et dispositif de demultiplexage associes, et emetteur-recepteur d'interface en faisant application
FR2500704A1 (fr) * 1981-02-20 1982-08-27 Devault Michel Commutateur temporel asynchrone pour reseau numerique a integration des services
US4847703A (en) * 1985-06-03 1989-07-11 Canon Kabushiki Kaisha Data transmission and detection system
US4635255A (en) * 1985-07-26 1987-01-06 Advanced Micro Devices, Inc. Digital subscriber controller
EP0214352B1 (en) * 1985-08-13 1990-10-24 International Business Machines Corporation Adaptive packet/circuit switched transportation method and system
DE3674196D1 (de) * 1986-04-17 1990-10-18 Ibm Leistungsfaehiges integriertes uebertragungsverfahren fuer daten und nichtkodierte information.
JPH07118749B2 (ja) * 1986-11-14 1995-12-18 株式会社日立製作所 音声／データ伝送装置
US4891808A (en) * 1987-12-24 1990-01-02 Coherent Communication Systems Corp. Self-synchronizing multiplexer
DE3917214A1 (de) * 1988-06-13 1989-12-21 Asea Brown Boveri Verfahren zur bitseriellen uebertragung von datenwoertern
JPH0744511B2 (ja) * 1988-09-14 1995-05-15 富士通株式会社 高郊率多重化方式

Also Published As

Publication number Publication date
MX9303940A (es) 1994-02-28
AU4518693A (en) 1994-01-31
DE69327957D1 (de) 2000-04-06
EP0648396B1 (en) 2000-03-01
CN1066877C (zh) 2001-06-06
SE9202031L (sv) 1994-01-02
NO945055D0 (no) 1994-12-27
ES2144006T3 (es) 2000-06-01
SE9202031D0 (sv) 1992-07-01
DE69327957T2 (de) 2000-07-13
SE500427C2 (sv) 1994-06-20
KR100233619B1 (ko) 1999-12-01
EP0648396A1 (en) 1995-04-19
AU671655B2 (en) 1996-09-05
CN1083292A (zh) 1994-03-02
US5450398A (en) 1995-09-12
DK0648396T3 (da) 2000-07-31
WO1994001952A1 (en) 1994-01-20
FI946196A (fi) 1994-12-30
GR3033045T3 (en) 2000-08-31
NO945055L (no) 1994-12-27

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