FI914429A - Foerfarande och anordning foer optimering av bussarbitration. - Google Patents

Foerfarande och anordning foer optimering av bussarbitration. Download PDF

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Publication number
FI914429A
FI914429A FI914429A FI914429A FI914429A FI 914429 A FI914429 A FI 914429A FI 914429 A FI914429 A FI 914429A FI 914429 A FI914429 A FI 914429A FI 914429 A FI914429 A FI 914429A
Authority
FI
Finland
Prior art keywords
optimering
bussarbitration
anordning foer
och anordning
foerfarande och
Prior art date
Application number
FI914429A
Other languages
English (en)
Finnish (fi)
Other versions
FI914429A0 (fi
Inventor
George Bohoslaw Marenin
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of FI914429A0 publication Critical patent/FI914429A0/fi
Publication of FI914429A publication Critical patent/FI914429A/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
FI914429A 1990-09-21 1991-09-20 Foerfarande och anordning foer optimering av bussarbitration. FI914429A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US58634990A 1990-09-21 1990-09-21

Publications (2)

Publication Number Publication Date
FI914429A0 FI914429A0 (fi) 1991-09-20
FI914429A true FI914429A (fi) 1992-03-22

Family

ID=24345380

Family Applications (1)

Application Number Title Priority Date Filing Date
FI914429A FI914429A (fi) 1990-09-21 1991-09-20 Foerfarande och anordning foer optimering av bussarbitration.

Country Status (18)

Country Link
US (1) US5195185A (fr)
EP (1) EP0476990B1 (fr)
JP (1) JPH0810445B2 (fr)
KR (1) KR950014505B1 (fr)
CN (1) CN1037553C (fr)
AU (1) AU639589B2 (fr)
BR (1) BR9103929A (fr)
CA (1) CA2050129C (fr)
CZ (1) CZ282214B6 (fr)
DE (1) DE69132344T2 (fr)
FI (1) FI914429A (fr)
HU (1) HU215867B (fr)
MX (1) MX173460B (fr)
NO (1) NO913707L (fr)
PL (1) PL167608B1 (fr)
PT (1) PT99006A (fr)
RU (1) RU2110838C1 (fr)
SG (1) SG42853A1 (fr)

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US5526496A (en) * 1994-04-22 1996-06-11 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
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US5758106A (en) * 1994-06-30 1998-05-26 Digital Equipment Corporation Arbitration unit which requests control of the system bus prior to determining whether such control is required
US5568614A (en) * 1994-07-29 1996-10-22 International Business Machines Corporation Data streaming between peer subsystems of a computer system
US5598542A (en) * 1994-08-08 1997-01-28 International Business Machines Corporation Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values
US5559969A (en) * 1994-08-09 1996-09-24 Unisys Corporation Method and apparatus for efficiently interfacing variable width data streams to a fixed width memory
US5634060A (en) * 1994-08-09 1997-05-27 Unisys Corporation Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus
US6434638B1 (en) 1994-12-09 2002-08-13 International Business Machines Corporation Arbitration protocol for peer-to-peer communication in synchronous systems
KR0155269B1 (ko) * 1995-01-16 1998-11-16 김광호 버스 중재방법 및 그 장치
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US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5859986A (en) * 1997-02-20 1999-01-12 International Business Machines Corporation Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing
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US5996037A (en) * 1997-06-03 1999-11-30 Lsi Logic Corporation System and method for arbitrating multi-function access to a system bus
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture
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US6182112B1 (en) 1998-06-12 2001-01-30 Unisys Corporation Method of and apparatus for bandwidth control of transfers via a bi-directional interface
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US8834864B2 (en) * 2003-06-05 2014-09-16 Baxter International Inc. Methods for repairing and regenerating human dura mater
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JP2006155387A (ja) * 2004-11-30 2006-06-15 Yamaha Corp コンピュータシステム
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CN111478840A (zh) * 2020-04-15 2020-07-31 联合华芯电子有限公司 用于总线系统的双速率仲裁中继设备
CN113821470B (zh) * 2020-06-19 2024-09-06 杭州中天微系统有限公司 总线设备、嵌入式系统和片上系统
RU2749911C1 (ru) * 2020-12-25 2021-06-21 Акционерное Общество "Крафтвэй Корпорэйшн Плс" Аппаратная реализация механизма использования одной памяти несколькими устройствами

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Also Published As

Publication number Publication date
HUT58931A (en) 1992-03-30
EP0476990A3 (en) 1993-08-04
EP0476990A2 (fr) 1992-03-25
CA2050129C (fr) 1996-05-14
AU639589B2 (en) 1993-07-29
SG42853A1 (en) 1997-10-17
FI914429A0 (fi) 1991-09-20
PL167608B1 (pl) 1995-09-30
CS287491A3 (en) 1992-04-15
CZ282214B6 (cs) 1997-06-11
AU8261291A (en) 1992-03-26
DE69132344T2 (de) 2001-02-15
NO913707L (no) 1992-03-23
DE69132344D1 (de) 2000-09-07
HU913024D0 (en) 1992-01-28
CN1037553C (zh) 1998-02-25
JPH0810445B2 (ja) 1996-01-31
KR950014505B1 (ko) 1995-12-02
RU2110838C1 (ru) 1998-05-10
KR920006858A (ko) 1992-04-28
MX173460B (es) 1994-03-04
US5195185A (en) 1993-03-16
CA2050129A1 (fr) 1992-03-22
HU215867B (hu) 1999-03-29
EP0476990B1 (fr) 2000-08-02
BR9103929A (pt) 1992-05-26
PL291778A1 (en) 1992-06-01
CN1060166A (zh) 1992-04-08
NO913707D0 (no) 1991-09-20
JPH04246758A (ja) 1992-09-02
PT99006A (pt) 1993-10-29

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Legal Events

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