FI901826A0 - COUPLING FOR SYNCHRONIZATION. - Google Patents

COUPLING FOR SYNCHRONIZATION.

Info

Publication number
FI901826A0
FI901826A0 FI901826A FI901826A FI901826A0 FI 901826 A0 FI901826 A0 FI 901826A0 FI 901826 A FI901826 A FI 901826A FI 901826 A FI901826 A FI 901826A FI 901826 A0 FI901826 A0 FI 901826A0
Authority
FI
Finland
Prior art keywords
inverter
counting
transistor
load path
case
Prior art date
Application number
FI901826A
Other languages
Finnish (fi)
Inventor
Peter Preller
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI901826A0 publication Critical patent/FI901826A0/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The circuit arrangement for a synchronous counter exhibits counting stages (Z1, Z2) which in each case exhibit a ring circuit consisting of a load path of a first transistor (T1), a first inverter (I1), a load path of a second transistor (T2) and a second inverter (I2) and third inverter (I3). The first and second transistors can be controlled via first and second control clocks (TM1, TM2; TS). The first control clock (TM1, TM2) in each case can be picked up at a clock output (TA) of each counting stage (Z1, Z2) for an immediately following counting stage (Z2), the second control clock (TS) having to be applied synchronously to all counting stages (Z1, Z2). Compared with the previously known synchronous counters, the component expenditure can be reduced by 30%. <IMAGE>
FI901826A 1989-04-11 1990-04-10 COUPLING FOR SYNCHRONIZATION. FI901826A0 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP89106358 1989-04-11

Publications (1)

Publication Number Publication Date
FI901826A0 true FI901826A0 (en) 1990-04-10

Family

ID=8201199

Family Applications (1)

Application Number Title Priority Date Filing Date
FI901826A FI901826A0 (en) 1989-04-11 1990-04-10 COUPLING FOR SYNCHRONIZATION.

Country Status (8)

Country Link
EP (1) EP0392222B1 (en)
JP (1) JPH02294117A (en)
KR (1) KR900017302A (en)
AT (1) ATE109600T1 (en)
DE (1) DE59006661D1 (en)
ES (1) ES2057228T3 (en)
FI (1) FI901826A0 (en)
PT (1) PT93719A (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3833822A (en) * 1972-12-21 1974-09-03 Bell Telephone Labor Inc Ripple free counter
US3829713A (en) * 1973-02-12 1974-08-13 Intersil Inc Cmos digital division network
GB1483068A (en) * 1973-07-30 1977-08-17 Tokyo Shibaura Electric Co Circuit comprised of insulated gate field effect transistors
US4025800A (en) * 1975-06-16 1977-05-24 Integrated Technology Corporation Binary frequency divider
US4182961A (en) * 1976-09-27 1980-01-08 Rca Corporation Inhibitable counter stage and counter
US4395774A (en) * 1981-01-12 1983-07-26 National Semiconductor Corporation Low power CMOS frequency divider

Also Published As

Publication number Publication date
ATE109600T1 (en) 1994-08-15
ES2057228T3 (en) 1994-10-16
DE59006661D1 (en) 1994-09-08
EP0392222B1 (en) 1994-08-03
PT93719A (en) 1990-11-20
KR900017302A (en) 1990-11-16
EP0392222A1 (en) 1990-10-17
JPH02294117A (en) 1990-12-05

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Legal Events

Date Code Title Description
FD Application lapsed

Owner name: SIEMENS AKTIENGESELLSCHAFT