FI885881A - Grafiksystem med grafik- och dram-kontrollkretsar. - Google Patents

Grafiksystem med grafik- och dram-kontrollkretsar. Download PDF

Info

Publication number
FI885881A
FI885881A FI885881A FI885881A FI885881A FI 885881 A FI885881 A FI 885881A FI 885881 A FI885881 A FI 885881A FI 885881 A FI885881 A FI 885881A FI 885881 A FI885881 A FI 885881A
Authority
FI
Finland
Prior art keywords
kontrollkretsar
grafiksystem
grafik
och
dram
Prior art date
Application number
FI885881A
Other languages
English (en)
Finnish (fi)
Other versions
FI885881A0 (fi
Inventor
Jean-Michel Callemijn
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of FI885881A0 publication Critical patent/FI885881A0/fi
Publication of FI885881A publication Critical patent/FI885881A/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
FI885881A 1987-12-23 1988-12-20 Grafiksystem med grafik- och dram-kontrollkretsar. FI885881A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8718041A FR2625340B1 (fr) 1987-12-23 1987-12-23 Systeme graphique avec controleur graphique et controleur de dram

Publications (2)

Publication Number Publication Date
FI885881A0 FI885881A0 (fi) 1988-12-20
FI885881A true FI885881A (fi) 1989-06-24

Family

ID=9358232

Family Applications (1)

Application Number Title Priority Date Filing Date
FI885881A FI885881A (fi) 1987-12-23 1988-12-20 Grafiksystem med grafik- och dram-kontrollkretsar.

Country Status (6)

Country Link
US (1) US4991112A (ja)
EP (1) EP0322065A1 (ja)
JP (1) JPH01201785A (ja)
KR (1) KR890010727A (ja)
FI (1) FI885881A (ja)
FR (1) FR2625340B1 (ja)

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US6025840A (en) * 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US5802581A (en) * 1995-12-22 1998-09-01 Cirrus Logic, Inc. SDRAM memory controller with multiple arbitration points during a memory cycle
KR19990029027A (ko) * 1996-05-17 1999-04-15 엠. 제이. 엠. 반캄 표시장치
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6311258B1 (en) 1997-04-03 2001-10-30 Canon Kabushiki Kaisha Data buffer apparatus and method for storing graphical data using data encoders and decoders
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6289138B1 (en) 1997-04-30 2001-09-11 Canon Kabushiki Kaisha General image processor
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US6119207A (en) * 1998-08-20 2000-09-12 Seiko Epson Corporation Low priority FIFO request assignment for DRAM access
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US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
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US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
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US4453214A (en) * 1981-09-08 1984-06-05 Sperry Corporation Bus arbitrating circuit
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US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system

Also Published As

Publication number Publication date
US4991112A (en) 1991-02-05
KR890010727A (ko) 1989-08-10
EP0322065A1 (fr) 1989-06-28
JPH01201785A (ja) 1989-08-14
FI885881A0 (fi) 1988-12-20
FR2625340B1 (fr) 1990-05-04
FR2625340A1 (fr) 1989-06-30

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Legal Events

Date Code Title Description
FA Application withdrawn

Owner name: N.V. PHILIPS GLOEILAMPENFABRIEKEN