FI882595A - Kontroller foer perifera anordningar och adapterinterface. - Google Patents

Kontroller foer perifera anordningar och adapterinterface. Download PDF

Info

Publication number
FI882595A
FI882595A FI882595A FI882595A FI882595A FI 882595 A FI882595 A FI 882595A FI 882595 A FI882595 A FI 882595A FI 882595 A FI882595 A FI 882595A FI 882595 A FI882595 A FI 882595A
Authority
FI
Finland
Prior art keywords
adapterers
controller
peripheral order
peripheral
order
Prior art date
Application number
FI882595A
Other languages
English (en)
Finnish (fi)
Other versions
FI882595A0 (fi
Inventor
Richard P Lewis
John A Klashka
Sidney L Kaufman
Krzstof A Kowal
John L Mcnamara Jr
Arthur M Douglass
Original Assignee
Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Bull filed Critical Honeywell Bull
Publication of FI882595A0 publication Critical patent/FI882595A0/fi
Publication of FI882595A publication Critical patent/FI882595A/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
FI882595A 1987-06-03 1988-06-02 Kontroller foer perifera anordningar och adapterinterface. FI882595A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5755387A 1987-06-03 1987-06-03

Publications (2)

Publication Number Publication Date
FI882595A0 FI882595A0 (fi) 1988-06-02
FI882595A true FI882595A (fi) 1988-12-04

Family

ID=22011296

Family Applications (1)

Application Number Title Priority Date Filing Date
FI882595A FI882595A (fi) 1987-06-03 1988-06-02 Kontroller foer perifera anordningar och adapterinterface.

Country Status (11)

Country Link
EP (1) EP0293860B1 (no)
JP (1) JPH0198048A (no)
KR (1) KR930002787B1 (no)
CN (1) CN1038362A (no)
AU (1) AU1671688A (no)
CA (1) CA1311310C (no)
DE (1) DE3855024D1 (no)
DK (1) DK305588A (no)
FI (1) FI882595A (no)
NO (1) NO882432L (no)
YU (1) YU107788A (no)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0501621A3 (en) * 1991-02-26 1994-07-06 Hewlett Packard Co Address prediction and verification for burst cycle data reads
US5379381A (en) * 1991-08-12 1995-01-03 Stratus Computer, Inc. System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
JPH07219894A (ja) * 1994-01-31 1995-08-18 Sony Corp データ転送方法及びデータ転送装置
KR100221080B1 (ko) * 1994-12-08 1999-09-15 정몽규 내연기관 제어장치의 통신속도 변환 장치 및 그 방법
DE69429007T2 (de) * 1994-12-22 2002-09-12 United Microelectronics Corp., Hsinchu DMA-Logikeinheitsarchitektur
JP3374739B2 (ja) 1998-01-09 2003-02-10 トヨタ自動車株式会社 車両用チャイルドシート検知システム
GB2353114B (en) * 1999-04-21 2001-09-19 Nec Corp Data processing system
JP3356110B2 (ja) 1999-04-21 2002-12-09 日本電気株式会社 機能拡張システム及びそれに用いるデータ転送方法
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6735715B1 (en) 2000-04-13 2004-05-11 Stratus Technologies Bermuda Ltd. System and method for operating a SCSI bus with redundant SCSI adaptors
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6633996B1 (en) 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US6971043B2 (en) 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US7447810B2 (en) * 2004-10-28 2008-11-04 Intel Corporation Implementing bufferless Direct Memory Access (DMA) controllers using split transactions
CN103226529B (zh) * 2012-01-31 2017-03-15 上海华虹集成电路有限责任公司 基于Nandflash的双端口存储器电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3409878A (en) * 1966-03-18 1968-11-05 Rca Corp Controlling interchanges between a computer and many communications lines
US4079452A (en) * 1976-06-15 1978-03-14 Bunker Ramo Corporation Programmable controller with modular firmware for communication control
JPS59108134A (ja) * 1982-12-13 1984-06-22 Nec Corp 入出力制御方式
JPS6059464A (ja) * 1983-09-12 1985-04-05 Nec Corp バスリクエスト制御方式
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
JPS6298444A (ja) * 1985-10-25 1987-05-07 Hitachi Ltd デ−タ通信方式

Also Published As

Publication number Publication date
DE3855024D1 (de) 1996-04-04
CA1311310C (en) 1992-12-08
NO882432L (no) 1988-12-05
JPH0198048A (ja) 1989-04-17
DK305588A (da) 1989-12-04
AU1671688A (en) 1988-12-08
EP0293860A2 (en) 1988-12-07
KR930002787B1 (ko) 1993-04-10
DK305588D0 (da) 1988-06-03
EP0293860B1 (en) 1996-02-28
NO882432D0 (no) 1988-06-02
EP0293860A3 (en) 1992-04-08
CN1038362A (zh) 1989-12-27
FI882595A0 (fi) 1988-06-02
KR900000776A (ko) 1990-01-31
YU107788A (en) 1990-12-31

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Legal Events

Date Code Title Description
FD Application lapsed
MM Patent lapsed

Owner name: HONEYWELL BULL INC.