FI844341L - Buffertsystem foer input/output delen i ett digitalt databehandlingssystem. - Google Patents

Buffertsystem foer input/output delen i ett digitalt databehandlingssystem.

Info

Publication number
FI844341L
FI844341L FI844341A FI844341A FI844341L FI 844341 L FI844341 L FI 844341L FI 844341 A FI844341 A FI 844341A FI 844341 A FI844341 A FI 844341A FI 844341 L FI844341 L FI 844341L
Authority
FI
Finland
Prior art keywords
databehandlingssystem
buffertsystem
delen
foer
input
Prior art date
Application number
FI844341A
Other languages
English (en)
Other versions
FI844341A0 (fi
Inventor
William F Bruckert
Barry Flahive
James V Lacy
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of FI844341A0 publication Critical patent/FI844341A0/fi
Publication of FI844341L publication Critical patent/FI844341L/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
FI844341A 1983-11-07 1984-11-06 Buffertsystem foer input/output delen i ett digitalt databehandlingssystem. FI844341L (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/549,608 US4860244A (en) 1983-11-07 1983-11-07 Buffer system for input/output portion of digital data processing system

Publications (2)

Publication Number Publication Date
FI844341A0 FI844341A0 (fi) 1984-11-06
FI844341L true FI844341L (fi) 1985-05-08

Family

ID=24193709

Family Applications (1)

Application Number Title Priority Date Filing Date
FI844341A FI844341L (fi) 1983-11-07 1984-11-06 Buffertsystem foer input/output delen i ett digitalt databehandlingssystem.

Country Status (8)

Country Link
US (1) US4860244A (fi)
EP (1) EP0141742A3 (fi)
JP (1) JPS60186956A (fi)
AU (1) AU575352B2 (fi)
CA (1) CA1227879A (fi)
DK (1) DK526584A (fi)
FI (1) FI844341L (fi)
IE (1) IE842855L (fi)

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US5241630A (en) * 1990-11-13 1993-08-31 Compaq Computer Corp. Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device
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US5377328A (en) * 1991-06-05 1994-12-27 Data General Corporation Technique for providing improved signal integrity on computer systems interface buses
US5222216A (en) * 1991-07-12 1993-06-22 Thinking Machines Corporation High performance communications interface for multiplexing a plurality of computers to a high performance point to point communications bus
US5848297A (en) * 1991-12-30 1998-12-08 Apple Computer, Inc. Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect
US5887196A (en) * 1991-12-30 1999-03-23 Apple Computer, Inc. System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer
US5640599A (en) * 1991-12-30 1997-06-17 Apple Computer, Inc. Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed
JPH05257851A (ja) * 1991-12-30 1993-10-08 Apple Computer Inc データの転送の順序を制御させる装置
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
US5325401A (en) * 1992-03-13 1994-06-28 Comstream Corporation L-band tuner with quadrature downconverter for PSK data applications
US5396597A (en) * 1992-04-03 1995-03-07 International Business Machines Corporation System for transferring data between processors via dual buffers within system memory with first and second processors accessing system memory directly and indirectly
FI90708C (fi) * 1992-04-23 1994-03-10 Nokia Telecommunications Oy Menetelmä sekä järjestelmä digitaalisten signaalien siirtämiseksi digitaalisen signaaliprosessorin ja siihen liitettyjen oheispiirien välillä
US5418911A (en) * 1992-06-09 1995-05-23 Intel Corporation Data path switch method and apparatus that provides capacitive load isolation
TW276312B (fi) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5499384A (en) * 1992-12-31 1996-03-12 Seiko Epson Corporation Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device
US5483640A (en) * 1993-02-26 1996-01-09 3Com Corporation System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices
US6067408A (en) * 1993-05-27 2000-05-23 Advanced Micro Devices, Inc. Full duplex buffer management and apparatus
US5664224A (en) * 1993-07-23 1997-09-02 Escom Ag Apparatus for selectively loading data blocks from CD-ROM disks to buffer segments using DMA operations
EP0646871B1 (en) * 1993-10-05 2003-11-26 Hitachi, Ltd. Data transfer control system
US5416520A (en) * 1993-11-30 1995-05-16 Intel Corporation Multiple encoder output buffer apparatus for differential coding of video information
US5615392A (en) * 1995-05-05 1997-03-25 Apple Computer, Inc. Method and apparatus for consolidated buffer handling for computer device input/output
US5592622A (en) * 1995-05-10 1997-01-07 3Com Corporation Network intermediate system with message passing architecture
US5802278A (en) * 1995-05-10 1998-09-01 3Com Corporation Bridge/router architecture for high performance scalable networking
US5805930A (en) * 1995-05-15 1998-09-08 Nvidia Corporation System for FIFO informing the availability of stages to store commands which include data and virtual address sent directly from application programs
US5732286A (en) * 1995-08-10 1998-03-24 Cirrus Logic, Inc. FIFO based receive packet throttle for receiving long strings of short data packets
JPH1040168A (ja) * 1996-07-29 1998-02-13 Ricoh Co Ltd データ処理装置
EP0859323B1 (en) * 1997-02-14 2007-03-21 Canon Kabushiki Kaisha Data transmission apparatus, system and method, and image processing apparatus
US5958026A (en) * 1997-04-11 1999-09-28 Xilinx, Inc. Input/output buffer supporting multiple I/O standards
US6073190A (en) 1997-07-18 2000-06-06 Micron Electronics, Inc. System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
US6243769B1 (en) 1997-07-18 2001-06-05 Micron Technology, Inc. Dynamic buffer allocation for a computer system
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US6559851B1 (en) 1998-05-21 2003-05-06 Mitsubishi Electric & Electronics Usa, Inc. Methods for semiconductor systems for graphics processing
US6504550B1 (en) 1998-05-21 2003-01-07 Mitsubishi Electric & Electronics Usa, Inc. System for graphics processing employing semiconductor device
US6535218B1 (en) 1998-05-21 2003-03-18 Mitsubishi Electric & Electronics Usa, Inc. Frame buffer memory for graphic processing
US6145032A (en) * 1998-09-21 2000-11-07 International Business Machines Corporation System for recirculation of communication transactions in data processing in the event of communication stall
US6993605B2 (en) 2001-02-28 2006-01-31 Sharp Laboratories Of America, Inc. Adaptive run-time data transfer optimization
JP2008146459A (ja) * 2006-12-12 2008-06-26 Toshiba Corp インタフェースコントローラ、リードアクセス制御方法及び該インタフェースコントローラを備える情報処理装置
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JPS51104233A (fi) * 1975-03-12 1976-09-14 Hitachi Ltd
US4099231A (en) * 1975-10-01 1978-07-04 Digital Equipment Corporation Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
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AT352449B (de) * 1977-01-21 1979-09-25 Schrack Elektrizitaets Ag E Einrichtung zur zeitlichen pufferung seriell einlangender bitfolgen in einem oder mehreren silospeichern
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JPS5833972B2 (ja) * 1979-11-12 1983-07-23 富士通株式会社 計算機システム間通信方式
DE3149678C2 (de) * 1981-12-15 1984-02-23 Siemens AG, 1000 Berlin und 8000 München Anordnung zur Zwischenspeicherung von zwischen zwei Funktionseinheiten in beiden Richtungen zu übertragenden Informationen in einem Pufferspeicher
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AU575351B2 (en) * 1983-11-07 1988-07-28 Digital Equipment Corporation Data processing system

Also Published As

Publication number Publication date
EP0141742A3 (en) 1989-04-12
AU575352B2 (en) 1988-07-28
CA1227879A (en) 1987-10-06
JPS60186956A (ja) 1985-09-24
IE842855L (en) 1985-05-07
EP0141742A2 (en) 1985-05-15
US4860244A (en) 1989-08-22
DK526584A (da) 1985-06-14
DK526584D0 (da) 1984-11-06
JPH0332094B2 (fi) 1991-05-09
AU3489484A (en) 1985-05-16
FI844341A0 (fi) 1984-11-06

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Legal Events

Date Code Title Description
FD Application lapsed
FD Application lapsed

Owner name: DIGITAL EQUIPMENT CORPORATION