FI66995C - OVER ANGLE CONNECTION FOR ATTACHMENT DATA MELLANPROCESSORER I ETT FLERPROCESSORSYSTEM - Google Patents

Description

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(71) Elevator GmbH, Rathausstrasse 1, CH-63 ^ 0 Baar, Switzerland-Switzerland (CH) (72) Paavo Sääksjärvi, Kirkkonummi, Finland-Finland (FI) (7 * 0 Oy Heinänen Ab (5 * 0 Method and equipment The present invention relates to a method for transferring data between central processing units or processors in a multiprocessor system, the system comprising one or more central processing units in a memory system, for transmitting data between processors or processors in a multiprocessor system.

In multiprocessor systems, two different technologies are most commonly used to transfer information between processors: one is called I / O technology and the other is called DMA technology. In traditional I / O technology (Input / Output technology), a processor reads data sent by another processor word by word or byte and stores it in its memory, or reads a word or byte at a time from its memory and writes it to another processor via the communication channel between them. In addition, if the data transfer is fast, the writing processor must make sure that the reading processor has had time to read the previous data before writing the next one. This way of handling data transfer is quite slow due to the fact that processors have to perform several different operations to transfer one word 2 66995 or bytes to another. In addition, the use of I / O technology slows down the execution of the other program of the processors, because the execution of the other program has to be interrupted during the above-mentioned operations, which also causes additional process state deposits and restores. I / O technology is only useful for either slow or limited data transfer events.

Another way to handle data transfer between processors is DMA (direct memory access) technology, in which data is transferred from or to the memory of the processor without the processor itself participating in the actual transfer event at all. In most cases, this is accomplished by stopping the processors involved in the transfer for the duration of the transfer event. In this way, the extra deposit and return operations that occur in I / O technology are avoided, and in addition, the transfer can be fast because it can be done by logic made just for this purpose. In other words, the logic, for example, does not read and store, but stores the incoming information directly in memory. However, this method requires a rather complex logic, which makes this technique expensive. In addition, if the need for data transfer is high, the logic begins to slow down the operation of the processor because stop times are extended or repeated more often. The same happens when there are several processors writing to or reading from the same memory, because transfer in this way is usually only possible between two processors at the same time. DMA technology has also implemented structures in which data transfer between processors takes place via a common memory. In this case, the system has a memory that all processors can write to and read from, but this memory can only be used by one processor at a time, in which case the processor, or at least DMA technology, must wait for the transfer of the second or repeat logics or processors to finish. In this way, some of the interruptions caused by DMA in the DMA interface of more than two processors can be reduced, but the actual transfer event may have to wait. Other disadvantages of DMA technology are the wide bus and fast communication signals, which cause poor interference immunity. DMA technology is useful when the need for data transfer rate is high and there are not many devices that need simultaneous transfer.

The method and apparatus according to the present invention are intended to eliminate the above-mentioned drawbacks and to provide a reliable and economical data transmission system in a multiprocessor system.

3 66995

The method according to the invention is characterized in that the data to be transferred between the central processing units are separated from their internal bus by shared memories and that the communication between the common memories is performed by a separate copying device which copies the writing block of each central processing unit to all others at the same time. The advantage in this case is that the data is transferred between the memories of the central processing units without any load from the central processing unit. Synchronization of the data processing processes performed by the CPUs connected to the shared memories is facilitated because the copying device updates the data in all the shared memories simultaneously.

A preferred embodiment of the invention is characterized in that the copying device performs data transmission without interruption while the system is in operation.

A preferred embodiment of the invention is characterized in that the updating of data between the shared memories is performed completely without a load from the central processing unit. The advantage in this case is that one central processing unit can have several shared memory buses and they do not load it.

Yet another preferred embodiment of the invention is characterized in that the data transmission between the shared memories is performed in series 1 ... n bits in parallel.

Yet another preferred embodiment of the invention is characterized in that the assignment of data in the copying operation is performed between the shared memories by separate address counters, which are synchronized by the copying device. A common advantage of these two embodiments is that the shared memory bus can be considered narrow because it does not need to transfer address information. In addition, due to the narrowness of the bus and its allowable slowness, the manufacturing cost of the bus can be reduced and the CPUs connected to it can be galvanically isolated quite easily, which also reduces the manufacturing cost.

The invention also relates to an apparatus for carrying out the above-mentioned method. The apparatus comprises one or more central processing units with memories. The hardware is characterized in that a copying device is connected to the common memory bus, as well as a common memory for each central processing unit, which is further connected to the central processing unit on the local bus. The advantage in this case is that the common memory bus does not load the devices to be connected to it from the central unit. Another advantage is that the central processing units can perform normal read and write operations with shared memory. Another advantage is the low cost of the hardware.

In the following, the invention will be described in more detail by means of an example with reference to the accompanying drawings, in which

Figure 1 shows the principle of the invention in block diagram form,

Figure 2 shows the structure of the shared memory with the accompanying connections in a block diagram and

Figure 3 shows a memory copying event.

For the sake of clarity, when describing the invention, it has been necessary to speak only of the data transmission between the central processing units. However, everything described here can also be applied, for example, to the transfer of data between the processors of the central processing units without substantially changing anything. Thus, when talking about a central processing unit, this word can be replaced by a processor in the method according to the present invention. The method according to the invention uses a very simple processor, hereinafter referred to as a copying device (1), which transfers data between shared memories (2). Data transfer takes place via the shared memory bus (5). The connection from the shared memory bus (5) to the central units (31) is made via each central unit's own so-called shared memory (2) and local bus 61. The shared memory bus (51) is run at such a slow frequency and synchronized with the central units (3) that affect the operation of the shared memory bus (51. Another, slightly more expensive way to get the CPU (31 shared memory (21) so that it does not affect the operation of the shared memory bus (51 is to interleave the operation of the shared memory bus (51) shared memories (21 at intervals when the CPUs (31) cannot be active in the shared memories (21. The shared memories are further divided into several blocks (A, B, C, .., N1. The copier 5 66995 (1) copies each CPU (3) a write memory, shown in Figure 3 as a dashed block, to all other corresponding blocks simultaneously ti.

The copying device (1) of the shared memory bus (5) is a clock generator which is synchronized with the central processing units (3) to be connected to the common memory bus (5) so that time slots are found, in which case (5) address changes. The central unit indicates the shared memory on the address bus (18). The copying device (1) generates at least the following signals on the shared memory bus (5): a clock pulse (7) with which the address counters (10) of all shared memories (2) step and a synchronizing pulse (8) for checking all address counters (10) at least once every copying round.

The basis of the shared memory operation is that either the copying via the shared memory bus1 (5) takes place so slowly that the central processing unit (3) can read or write to the shared memory (2) during the copying operation without affecting the operation of the shared memory bus (5), i.e. the central processing unit (3) "steals" time shared memory1 ta (2) or operation is interleaved, as previously described. The function of the address counter (10) is to operate in step with the clock pulse (7) coming from the copying device (1) and to count the address to the RAM type 11e memory (12). Synchronization is performed by the synchronization signal1i11 a (Θ). The unit (11) can be called a read / write selection unit. This is a logic unit that performs the selection of the aforementioned 1uku / write blocks as well as their timing. The outgoing data holding unit (13) ensures that the data on the bus (5) remains unchanged if the central processing unit (3) wants to use the RAM (12) in the middle of writing to the bus (5). It is also conceivable to add an incoming data holding unit (15) to the connection. ). The RAM memory has ports for both the bus (6) of the central processing unit (3) and the bus (5) of the common memory. The bus buffers (14) are circuits that adapt the RAM (12) to the shared memory bus (5) to be electrically compatible.

It will be apparent to one skilled in the art that the invention is not limited solely to the example set forth above, but that embodiments thereof may vary within the scope of the claims set forth below.

Claims (5)

66995 6 A method for transferring data between central processing units or processors in a multiprocessor system comprising one or more central processing units (3) with memories (4), characterized in that the data to be transferred between central processing units (3) or processors is separated from their internal bus (6) and that the communication between the shared memories (2) is performed by a separate copying device (1) which copies the writing block of each central processing unit (3) or processor to all other corresponding blocks simultaneously. A method according to claim 1, characterized in that the copying device (1) performs data transmission without interruption while the system is in operation. Method according to Claim 1 or 2, characterized in that the data update between the shared memories (2) is carried out completely without loading the central processing units (3) or processors. Method according to Claims 1, 2 or 3, characterized in that the data transmission between the shared memories (2) is carried out in series 1 to n bits in parallel. Method according to Claims 1 to 4, characterized in that the assignment of data in the copying operation is performed between the shared memories (2) by separate address counters (10) which are synchronized by the copying device (1). Apparatus for carrying out the method according to claim 1, comprising one or more central processing units (3) with memories (4), characterized in that a copying device (1) and each central processing unit (3) or processor are connected to the common memory bus (5). for this purpose, a common memory (2) further connected to the central processing unit (3) or the processor via the local bus (6).