FI20215371A1 - En metod och ett system för att generera ett högupplöst mönster på ett substrat - Google Patents

En metod och ett system för att generera ett högupplöst mönster på ett substrat Download PDF

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Publication number
FI20215371A1
FI20215371A1 FI20215371A FI20215371A FI20215371A1 FI 20215371 A1 FI20215371 A1 FI 20215371A1 FI 20215371 A FI20215371 A FI 20215371A FI 20215371 A FI20215371 A FI 20215371A FI 20215371 A1 FI20215371 A1 FI 20215371A1
Authority
FI
Finland
Prior art keywords
semi
polymer ink
ink film
desired pattern
substrate
Prior art date
Application number
FI20215371A
Other languages
English (en)
Finnish (fi)
Other versions
FI130437B (sv
Inventor
Jaakko Leppäniemi
Asko Sneck
Original Assignee
Teknologian Tutkimuskeskus Vtt Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teknologian Tutkimuskeskus Vtt Oy filed Critical Teknologian Tutkimuskeskus Vtt Oy
Priority to EP21816118.0A priority Critical patent/EP4248502A1/en
Priority to PCT/FI2021/050778 priority patent/WO2022106755A1/en
Priority to US18/035,765 priority patent/US20230399736A1/en
Publication of FI20215371A1 publication Critical patent/FI20215371A1/sv
Application granted granted Critical
Publication of FI130437B publication Critical patent/FI130437B/sv

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1275—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by other printing techniques, e.g. letterpress printing, intaglio printing, lithographic printing, offset printing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M1/00—Inking and printing with a printer's forme
    • B41M1/26—Printing on other surfaces than ordinary paper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/0046—Surface micromachining, i.e. structuring layers on the substrate using stamping, e.g. imprinting
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/042—Coating on selected surface areas, e.g. using masks using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Keksintö liittyy menetelmään ja laitteistoon halutun kuvion valmistamiseksi substraatille (26) sähköisesti johtavasta, puolijohtavasta tai eristävästä materiaalista (30). Kuvioitu polymeerimustekalvo (22’) tuotetaan puolikuivasta polymeerimusteesta tuomalla kolmiulotteinen reliefikuvio (25), jossa on halutun kuvion positiivinen kuva, väliaikaiseen kontaktiin puolikuivan polymeerimustekalvon (22) kanssa siten, että osat (22’’) puolikuivasta polymeerimustekalvosta, siirtyvät kolmiulotteiseen reliefikuvioon (25). Kuvioidulla polymeerimustekalvolla (22’), jossa on halutun kuvion negatiivi, on vertikaaliset sivuseinämät, jotka aiheutuvat puolikuivan polymeerimustekalvon (22) lohkeamisesta kolmiulotteisen reliefikuvion (25) reunojen koheesion ja puolikuivan polymeerimustekalvon (22) toisten osien (22’’) ja kolmiulotteisen reliefikuvion (25) välisestä adheesiosta. Kuvioitu polymeerimustekalvo (22’) siirretään substraatille (26) ja johtava, puolijohtava tai eristävä materiaalikerros (30, 30’) kerrostetaan substraatille (26) käyttäen fysikaalista kaasufaasipinnoitusta tai kemiallista kaasufaasipinnoitusta. Kuvioitu polymeerimustekalvo (22’) liuotetaan substraatilta (26) orgaanisella liuottimella halutun (30) kuvion aikaansaamiseksi.
FI20215371A 2020-11-20 2021-03-30 En metod och ett system för att generera ett högupplöst mönster på ett substrat FI130437B (sv)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21816118.0A EP4248502A1 (en) 2020-11-20 2021-11-17 A method and a system for generating a high-resolution pattern on a substrate
PCT/FI2021/050778 WO2022106755A1 (en) 2020-11-20 2021-11-17 A method and a system for generating a high-resolution pattern on a substrate
US18/035,765 US20230399736A1 (en) 2020-11-20 2021-11-17 A method and a system for generating a high-resolution pattern on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20206184 2020-11-20

Publications (2)

Publication Number Publication Date
FI20215371A1 true FI20215371A1 (sv) 2022-05-21
FI130437B FI130437B (sv) 2023-08-30

Family

ID=82399775

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20215371A FI130437B (sv) 2020-11-20 2021-03-30 En metod och ett system för att generera ett högupplöst mönster på ett substrat

Country Status (1)

Country Link
FI (1) FI130437B (sv)

Also Published As

Publication number Publication date
FI130437B (sv) 2023-08-30

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