FI20165521A - Tasonmuunnin ja menetelmä jännitetason muuntamiseksi - Google Patents

Tasonmuunnin ja menetelmä jännitetason muuntamiseksi

Info

Publication number
FI20165521A
FI20165521A FI20165521A FI20165521A FI20165521A FI 20165521 A FI20165521 A FI 20165521A FI 20165521 A FI20165521 A FI 20165521A FI 20165521 A FI20165521 A FI 20165521A FI 20165521 A FI20165521 A FI 20165521A
Authority
FI
Finland
Prior art keywords
level
converting voltage
converter
voltage level
level converter
Prior art date
Application number
FI20165521A
Other languages
English (en)
Swedish (sv)
Other versions
FI127771B (fi
Inventor
Ari Paasio
Lauri Koskinen
Matthew Turnquist
Original Assignee
Minima Processor Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minima Processor Oy filed Critical Minima Processor Oy
Priority to FI20165521A priority Critical patent/FI127771B/fi
Priority to TW106120892A priority patent/TW201813312A/zh
Priority to EP17177329.4A priority patent/EP3261251A1/en
Priority to US15/630,665 priority patent/US10469084B2/en
Priority to KR1020170079181A priority patent/KR20180000695A/ko
Priority to CN201710484487.9A priority patent/CN107547080A/zh
Priority to JP2017122825A priority patent/JP2018026802A/ja
Publication of FI20165521A publication Critical patent/FI20165521A/fi
Application granted granted Critical
Publication of FI127771B publication Critical patent/FI127771B/fi

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
    • H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
FI20165521A 2016-06-23 2016-06-23 Tasonmuunnin ja menetelmä jännitetason muuntamiseksi FI127771B (fi)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FI20165521A FI127771B (fi) 2016-06-23 2016-06-23 Tasonmuunnin ja menetelmä jännitetason muuntamiseksi
TW106120892A TW201813312A (zh) 2016-06-23 2017-06-22 位準偏移器及用來偏移電壓位準的方法
EP17177329.4A EP3261251A1 (en) 2016-06-23 2017-06-22 A level shifter and a method for shifting voltage level
US15/630,665 US10469084B2 (en) 2016-06-23 2017-06-22 Level shifter and a method for shifting voltage level
KR1020170079181A KR20180000695A (ko) 2016-06-23 2017-06-22 레벨 시프터 및 전압 레벨을 시프트하는 방법
CN201710484487.9A CN107547080A (zh) 2016-06-23 2017-06-23 电平转换器、电子设备及用于控制电平转换器的方法
JP2017122825A JP2018026802A (ja) 2016-06-23 2017-06-23 レベルシフタおよび電圧レベルをシフトする方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20165521A FI127771B (fi) 2016-06-23 2016-06-23 Tasonmuunnin ja menetelmä jännitetason muuntamiseksi

Publications (2)

Publication Number Publication Date
FI20165521A true FI20165521A (fi) 2017-12-24
FI127771B FI127771B (fi) 2019-02-15

Family

ID=59152689

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20165521A FI127771B (fi) 2016-06-23 2016-06-23 Tasonmuunnin ja menetelmä jännitetason muuntamiseksi

Country Status (7)

Country Link
US (1) US10469084B2 (fi)
EP (1) EP3261251A1 (fi)
JP (1) JP2018026802A (fi)
KR (1) KR20180000695A (fi)
CN (1) CN107547080A (fi)
FI (1) FI127771B (fi)
TW (1) TW201813312A (fi)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10171080B2 (en) * 2016-09-20 2019-01-01 Qualcomm Incorporated Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase
CN108712166B (zh) * 2018-02-27 2022-06-28 北京时代民芯科技有限公司 一种自适应电平转换电路
CN113452363A (zh) * 2020-03-24 2021-09-28 长鑫存储技术(上海)有限公司 动态控制转换电路
US11921651B2 (en) * 2021-06-07 2024-03-05 AyDeeKay LLC Interface module with low-latency communication of electrical signals between power domains

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3267436B2 (ja) 1993-04-19 2002-03-18 三菱電機株式会社 半導体装置
US20020047726A1 (en) 2000-03-31 2002-04-25 Narendra Siva G. Footless domino gate
US6693461B2 (en) * 2001-12-20 2004-02-17 Intel Corporation Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation
US7355905B2 (en) * 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
US7764087B2 (en) 2006-02-01 2010-07-27 Wisconsin Alumni Research Foundation Low swing domino logic circuits
US7355447B2 (en) * 2006-06-02 2008-04-08 Bae Systems Information And Electronic Systems Integration Inc. Level shifter circuit
US7808294B1 (en) 2007-10-15 2010-10-05 Netlogic Microsystems, Inc. Level shifter with balanced rise and fall times
US7804334B2 (en) * 2008-07-29 2010-09-28 Qualcomm Incorporated High signal level compliant input/output circuits
US8593203B2 (en) * 2008-07-29 2013-11-26 Qualcomm Incorporated High signal level compliant input/output circuits
US7800407B1 (en) * 2009-06-26 2010-09-21 Intel Corporation Multiple voltage mode pre-charging and selective level shifting
US8179178B2 (en) * 2009-08-13 2012-05-15 Via Technologies, Inc. Registers with reduced voltage clocks
JP5350141B2 (ja) * 2009-08-26 2013-11-27 ルネサスエレクトロニクス株式会社 レベルシフト回路
US7986165B1 (en) 2010-02-08 2011-07-26 Qualcomm Incorporated Voltage level shifter with dynamic circuit structure having discharge delay tracking
US8406077B2 (en) * 2010-07-01 2013-03-26 Qualcomm Incorporated Multi-voltage level, multi-dynamic circuit structure device
US8559247B2 (en) * 2011-05-16 2013-10-15 Apple Inc. Dynamic level shifter for interfacing signals referenced to different power supply domains
US8912853B2 (en) * 2012-06-14 2014-12-16 Apple Inc. Dynamic level shifter circuit and ring oscillator using the same
WO2014105013A1 (en) * 2012-12-27 2014-07-03 Intel Corporation Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
US8860488B2 (en) 2013-03-06 2014-10-14 Micron Technology, Inc. Apparatuses and method for shifting a voltage level
KR102078291B1 (ko) 2014-01-20 2020-02-19 에스케이하이닉스 주식회사 레벨 쉬프터
US9385722B2 (en) * 2014-11-25 2016-07-05 Intel Corporation Voltage level shifter circuit
US9608637B2 (en) * 2015-08-14 2017-03-28 Qualcomm Incorporated Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods
US10171080B2 (en) * 2016-09-20 2019-01-01 Qualcomm Incorporated Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase

Also Published As

Publication number Publication date
TW201813312A (zh) 2018-04-01
JP2018026802A (ja) 2018-02-15
US20170373691A1 (en) 2017-12-28
FI127771B (fi) 2019-02-15
KR20180000695A (ko) 2018-01-03
US10469084B2 (en) 2019-11-05
EP3261251A1 (en) 2017-12-27
CN107547080A (zh) 2018-01-05

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