FI120328B - CCD sensor and method for expanding CCD sensor dynamics - Google Patents

Description

CCD sensor and method for expanding CCD sensor dynamics

Field of the Invention

The invention relates to a readout arrangement for reading a CCD sensor according to the preamble of claim 5. The invention further relates to a method for expanding the dynamics of a CCD sensor according to the preamble of claim 31.

BACKGROUND OF THE INVENTION A Charge Coupled Device (CCD) device can be defined as a semiconductor device (10) where, due to the movement of electrical charges, it is possible to store and collect charges. These charge transfer devices are used in dynamic, variable memory elements, which are characterized by high information density. In CCD sensors for X-ray imaging, the charges in the physical pixels used to form the image can be combined, binned. When binned on a CCD sensor, virtually larger pixels are formed. However, in certain situations, handling of the charge of these combined pixels can be problematic. Especially at higher signal levels, the signal from the image area may be so large that, with the selected binary, the charges cannot be combined inside the CCD without the risk of saturation of the output amplifier. This can be partially taken into account by designing a read register and an output amplifier charge well having a charge capacity: * · *: greater than the pixel charge capacity. However, if the departure • •: ** ·; • the expansion chamber of the strainer is enlarged too much, the voltage is reduced • · ·: ·. nee, which also reduces the output signal.

“·· [25 Today, the resolution or resolution of digital imaging is nearing 9 · the level of film-based systems and in some cases may even exceed…. However, it is known that the dynamic range of the CCD sensors, the ratio of the maximum signal to the idle noise, the basic sensitivity, is smaller than the dynamic range of the conventional film-based systems. In this context, sensitivity can mean · · · ·. * ··. the size of the signal can be distinguished from noise.

• · · ·. A typical CCD device operating in MPP mode that is not ··· ·· ”'has a dynamic range of about 10.000: 1 ... 20.000: 1. The dynamic range figure describes the ratio of saturation voltage to rms noise. If this dynamic-35 ka range is effectively utilized, the gray levels will be as many as 2 as the A / D conversion used. For example, in the case of the 14-bit, 16,384 gray levels are available in their entirety.

However, these numerical values are not comparable when comparing film and digital systems. Even if only a small part of the overall dynamic system is utilized in the film system, a very large number of gray levels are available in practice. For example, if you look at one-thousandth (1: 1000) of the film's dynamics, it can be shown that this area is divided into more than 16 distinct levels.

Also, CCD-based sensors do not forgive over-exposure-10 situations, such as team-based systems where the reciprocal law (gradual saturation of the film, s-curve) causes soft saturation with accompanying "compression", an expansion of dynamics. which can also be thought of as a kind of gamma correction in the film itself. ”Digital sensors produce an instantly visible boundary, an artifact, when the dynamics are maximized.

The signal amplifier behind the CCD sensor and the Analog-to-Digital converter (A / D) are designed so that the entire dynamic range produced by the CCD sensor can be utilized. As mentioned above, current CCD sensors can provide a dynamic range of up to 20,000: 1. The perfect situation is when the quantization step of the A / D converter is slightly below the noise level of the CCD sensor. However, this would mean that you would need to use an A / D conversion greater than 14-bit to digitize the image.

··: * ·· In other words, the charge entered in one pixel and accommodating it can be ['V so large that it cannot be processed in the read register and / or near "in the bin state: 25 amplifiers in the well without risk of saturation. In binnings, eg 3x3 and 4x4 (horizontal x vertical, mono · · · ·. ***. forged times from the image area to the output register and from the output register to the excavation well), this becomes a problem. :. · 'Saturated and it is fully usable, but cannot be read out without • · · y / 30 saturation at that binnacle.

**: · * Both in Cephalostat (Ceph) and Panoramic (Pan), there are areas beneath the jaws that receive direct radiation without any attenuating tissue. Among other things, saturation in these situations. the danger is obvious if the system is otherwise tuned to • • · 35 optimally receive a signal coming through the target. This, for example, makes imaging • soft parts impossible and all image information is lost in saturation regions.

Brief Description of the Invention

It is thus an object of the invention to provide a method and apparatus implementing the method 5 so that the above problems can be solved. The object of the invention is achieved by a method and a system characterized by what is stated in the independent claims. Preferred embodiments of the invention are claimed in the dependent claims.

The invention is based on changing the binnings and / or using at least two different capacity reservoir wells and dynamically selecting a readout well to be used during sensor readout.

An advantage of the method and system according to the invention is that the dynamic range of the CCD sensor can be expanded and thus prevent the sensor or a part of it from being saturated.

15 Brief Description of the Figures

The invention will now be further described in connection with preferred embodiments, with reference to the accompanying drawings, in which:

Figure 1 shows a device for increasing dynamics according to a preferred embodiment; Figure 2 shows the structure of image data; ··· ·

Figure 3 illustrates, by way of example, a method for performing an imaging and an AGC operation control over a FPGA device during imaging. logic of; • · · ”·. Figure 4 shows a table showing typical charge processing capacities of the CCD sensor used; ** ·· 'FIG. 5 illustrates an exemplary charge capacity distribution for all units capable of transferring electron charges; and v; Figure 6 illustrates a four chip CCD sensor and its control blocks.

• · · • • • • • *. DETAILED DESCRIPTION OF THE INVENTION The invention and preferred embodiments thereof will be described in the following **: · * by way of example with reference to a typical CCD sensor (manufactured by, for example, * j * Atmel, Thomson) and charge capacity specifications optimized for? ·· Note also the Automatic Gain Control (AGC) function. For example, the sensor may have the following characteristics: 4 1) A random single pixel (size: 33 µm x 33 µm) random charge: 600,000 electrons.

2) Saturation reservation of the numerical register: 5 1.800.000 electrons.

3) Saturation charge of output amplifier A: 2,400,000 electrons.

4) Saturation charge of output amplifier B: 4.800.000 electrons.

10

When used in the horizontal direction (TDI, Time Delay Integration), this sensor can accommodate a 100% signal of 3 consecutive pixels in a read register (3x600K = 1800K, K = Kilo = 1000). The 4x4 binary can sum up 4 horizontal pixels that are 75% full 15 (1800K / 4/600 * 100) without overflow. An overflow can mean that, for example, an electronic component such as capacitance can no longer hold additional charges. In an overflow, the excess electron charge in the image region may move in the horizontal direction and in the overflow in the output register, it may move vertically.

20 In the vertical direction (reading direction) the situation is as follows.

With 2x2 binning, one output A can be summed with 2 pixels with · · · - 50% charge and another output B with 3 pixels with 100% charge without overflow. With 3x3 binning, 3 pixels can be added to output A: ***: with 44% charge, and output B 3 pixels with 88% reserve • ·. ** ·. 25 without overflow. With 4x4 binning you can add to the output A 4 pieces 25% ·· ·:. charge pixels and output B 4 50% charge pixels without over *. ··· * leakage.

• · This shows that even the less sensitive output B cannot. . to process a signal from the image area without saturation if the signal exceeds 25% of the physical pixel charge capacity when using the output of A.Kek- ·· ♦ * and its preferred embodiments can remedy this situation.

·: · Figure 1 shows a CCD ··· ”: *** according to a preferred embodiment. sensor to increase dynamics. In it, reference numeral 1-1 describes the entire CCD · · ·. *. sensor module, detector. Pixels receiving detector charges • · · ** * | The 35 active regions are described by reference numeral 1-2. This image-forming surface may have a substantially flat structure of any shape.

For example, the image information of a two-dimensional CCD sensor can be read out by means of a read register 1-4 at least one edge operatively associated with said active region. For example, one pixel column may be loaded at a time into this register. The pixels in the pixel column may be interconnected, i.e. binned. The sensor also comprises means for transferring the charges to the output 1-4a, 1-4b of the read register 1-4, whereupon the register can be read, for example, serially by transferring the charge 10 pixels at a time, with or without binning, to the output well 1-6, 1-8. it can be further output from the 1-10, 1-12 CCD sensor 1-1.

Thus, the bookings can be transferred by suitable arrangements in the register in the desired direction, in the direction of a lower capacity outlet or in the direction of a larger capacity outlet. Which output well is used during imaging can be dynamically optimized during imaging so that, for example, the size of the output well and / or binning used by the sensor output is selected by the electronics, selection program, or combination thereof.

The output amplifier reservoir 1-6, 1-8 may be located at either end of the register 1-4, or alternatively two or more wells and / or amplifiers may be located at one end of the register or at both ends of the register. . According to the invention and a preferred embodiment thereof, at each end of the read register there is at least one operatively associated well, a read well 1-6,1-8 and an amplifier.

The well may have an operational amplifier and / or buffer attached. and / or a buffer amplifier.

[···] These dual amplifiers can be designed for different »· applications. For example, the second amplifier can be optimized for so-called. slow-scan moo-. . for slides, so that noise can be optimized to a minimum at the cost of speeds. The second amplifier can be optimized for so-called. for high-speed mode • · * ··· * slides to optimize read speed as fast as possible, but not at the expense of noise.

• · · ·: ***: However, with both traditional amplifiers, the output amplifiers • · ·. *. the wells have had the same capacity. Thus, according to the invention and the preferred embodiments thereof, at least two outlet wells having different capacities are produced. Preferably, the capacities should differ substantially from each other, for example, so that the capacity of the larger outlet is approximately twice that of the smaller outlet. Other ratios may also be used. If there are more than two wells, the capacities of at least two wells may differ.

Thus, the invention and its preferred embodiments are based on the use of at least two different capacity charge wells, and a dynamically operated readout well can be selected during sensor readout. The selection can be made depending on the signal, based on the signal information, for example an image signal.

This gives the advantage over using only one output amplifier or, on the other hand, using two output amplifiers having the same capacities, so that saturation of the internal transfer and readout wells (not the image area) of the CCD sensor can be prevented. In addition, the invention and its preferred embodiments can prevent over-control of the A / D converter.

15 Both situations are very likely to occur when pixel charges are merged, i.e. binned, at greater than 2x2 pixels.

Figure 2 shows a structure of an image data. In the figure, the lowest 14 data bits (AD0-AD13: Figure 6: 6-51, 6-53, 6-55, 6-57) may come from a Field Programmable Gate Array (FPGA) of a pixel FPGA (Figure 6: 6-40). illustrates a data processing module in a 16-bit adder (Figure 6: 6-41, 6-42, 6-43, 6-44) and a register (6-45, 6-46, 6-47, 6-48) which can keep subtotals.

This adder can be reset before sampling each pixel, and the resulting 14-bit A / D converter result can be added to this adder once.

: * · * · You can also add +1 to the sum so that the result is always greater than 0.

• ·. ···. 25 This is a result of 14 bits and the top 2 bits (ADDO and ADD1) are zeros.

: * ·!. In one case, the sum of four consecutive A / D converters is added to this adder so that the result approaches a maximum of 16 bits. Mi- • · * '* if one takes into account the fact that each CCD sensor chip can. . There can be two outputs (Output A and Output B, one of which can give double sig- nal: 30 signals with the same radiation), the total system dynamics is 17 bits, or 131,072 gray planes (16,384 x 4 x 2).

··· One CCD sensor (Figure 6: 6-20) can consist of one or more • ·· ·. ***. for example, four (Figure 6: 6-21, 6-22, 6-23, 6-24) one after the other. **. seamlessly connected chip. Each chip can have its own clock signal- • · · * ♦ * | 35 flax. Ceph operation uses two identical CCD sensors. Each * * chip has two outputs (Figure 6: 6-25 ... 6-32). The other may be more sensitive to so-called.

7 high sensitivity or A-output and the other may be less sensitive so-called. high capacity or B output. Thus, a single CCD sensor can have a total of 8 digitizable outputs, of which, for example, only four outputs are used at a time. In practice, the output ratio of the AB outputs is very close to Vz, i.e. the signal of the B output 5 is half the same amount of radiation as the output of the A output.

If more than one chip is used, each different chip may handle a specific portion of the patient and / or operate in a different mode, and each chip may be individually or individually controlled.

The current output can be selected (Switches 6-33 ... 6-36 in Fig. 10 6), for example, manually via the control register. Alternatively, the AGC function or one of the test functions may decide the output. All 8 outputs can be digitized with A / D converters, such as three. Each A / D converter can have a 3-input multiplexer or selector, so the total number of channels to be digitized is 9. The extra tenth channel is in 15 test runs that can measure electronics and A / D conversion noise.

Figure 6 illustrates a situation in which the selection element 6-33 ... 6-36 after the output wells 6-25 ... 6-32 directs one of the wells to a single A / D converter 6-37. Alternatively, the outputs of both wells can be subjected to A / D conversion and then only the select element used to select the di-20-gated signal of each well is used. The selection element may also be part of an A / D converter and may be, for example, an analog or digital switch. Figure 6 also shows an option for importing 6-100 clock signals and / or control signals from the FPGA element 6-40 to the CCD sensor 6-20.

AGC function means automatic level or gain • ·. ···. 25 adjustments. It does not, however, refer to Programmable Gate Array (PGA) amplifiers inside AD converters, which can be adjusted, for example, between 1 and 6. This gain can be adjusted. separately for each CCD chip, and the adjustment is mainly used to optimize the basic sensitivity according to the imaging conditions (Pan / Ceph).

: 30 The AGC method can be utilized in a camera in the following two ways. Either of the output amplifiers A or B of each CCD sensor can be used as appropriate. Because the signal amplifier of the B amplifier is * ··. compression capacity is about twice that of the A amplifier, virtually one bit is added to the AD transform. Alternatively:. ** i 35 Binnings outside the CCD can also be used. However, this is only possible with a binning toward the read register.

8

If with large binnings, such as 4x4 binning, the B output amplifier is getting saturated, it is possible to switch to a smaller binning inside the CCD sensor, for example 4x2 binning. Hereby, the pixel values can be sampled twice by the A / D converter, and summing can be performed, for example, inside an FPGA device in an arithmetic unit. The multiplication of electronics offsets can be offset by computer software. This external summation can even be in the form of 4x1 and 4 summations.

For example, in binary reduction, instead of summing four charges, you can combine only 2 pixels with the output well, digitize the pixels, take the next two pixels, digitize the pixels, and then digitize the Digitized Results.

In the above manner, the total dynamics is increased to 17 bits, of which 14 bits are obtained from the AD conversion, 1 bit from the output of the A or B-15 amplifier and 2 bits from the external summing, which can thus be done 4 times.

FIG. 3 illustrates, by way of example, a method for performing imaging and control logic for automatic gain control (AGC) of an FPGA device during imaging. Shooting starts normally with the initial value selected, the default binary. Initially, the output A of each CCD sensor chip can be used. Since the read register of each chip can be individually controlled, it is possible to select in which direction the charge is transferred.

• · · ·

The charge can thus be shifted either in the direction of output A (1-8: Fig. 1) or output B: *. (1-6: Figure 1).

• · *. · !. The logic of the FPGA device can continuously monitor the signal of each of the individual A / D conversions. In step 3-2, a new column of CCDs is read from the sensor to the memory. In Step 3-4, it can be checked whether even one of the * /·· 'A / D converted outputs of the CCD currently in use (Figure 6: 6-50, 6- 52, 6-54, 6-56), for example, exceeds 75% of signal to A / D converter. (Information • ·: 30 signal sizes can be passed to the inference block and, for example, to a state machine: Figure 6: 6-50, 6-52, 6-54, 6-56) Thus, if the signal or a portion thereof exceeds a predetermined value, e.g. From the D converter range, you can switch to Τ '*. to less sensitive output, output B, on the chips where this condition is met. If all outputs are below the first threshold, it is possible to check • · 35 in steps 3-6 whether all currently used CCD sensor * "'· outputs produce below a second predetermined threshold, for example less than 25% of the 9 A / D signal. converter. If all the outputs are below the second threshold, it can be checked in step 3-8 whether the smallest off-line binary off-CCD is already achieved. If the smallest external binning has not been achieved, it is possible to proceed to step 3-10 where the next vertical row can be 5 steps to a smaller external binning. If, on the other hand, the smallest external binning has already been achieved, in step 3-12, the next vertical row can be switched to the A-output by the B-outputs of the CCD sensor. That is, if the signal correspondingly, for example, falls below a certain predetermined second value, for example, in the range of a V * A / D converter, then the more sensitive output, output A, can be switched on the chips where this condition is required.

If, in step 3-4, at least one output exceeds 75% of the signal from the A / D converter, proceed to step 3-14. It can look at whether any of the outputs that produce more than 75% of the signal are already B-outputs. If this is not the case, the A-15 outputs of the transducer may be switched to use the B output in the next column in step 3-16.

If the signal still exceeds% of the area of the A / D converter in the A / D converter of the 1-socket CCD sensor chip, even though switching to output B, i.e. where the B output is being digitized, can be viewed in steps 3-18, external binning already achieved. If the maximum external register-facing binary has not yet been reached, in step 3-20, you can move to the next vertical row incremental · · · · I * .., preferring the external register-oriented arithmetic binning of the CCD sensor, for example on all chips. Binnings can be changed incrementally as required • · [_ ···, 25 to 4x4 ... 1x4 and back to 4x4. This binning reduction does not • ·. ”I appear in the image data because, in addition to binning inside the sensor, binning is also performed after the AD conversion, so more A / D can be performed. -convert per pixel. The result is still the same when this is taken into account when compensating for dark currents. The dark current can mean the leakage current of silicon • · 30 due to non-idealities, whereby electrons are leaking into the pixels, • · · resulting in a bottom signal. The signal can double as the temperature increases by about +7 degrees C. The dark current is not uniform but can affect different [···. pixels differently.

• · The design and timing of the FPGA can also be optimized for your own:: ** i 35 femininity. In step 3-22, the A output can be reset to all CCD sensors having a B output below a second threshold, for example less than 25%. If the maximum exterior register binning has already been reached, proceed from step 3-18 to step 3-24. Likewise, after steps 3-10, 3-12, 3-16 and 3-22, it is possible to proceed to step 3-24, where the next column is expected to be digitized.

5 If the AGC function is thus activated, in the automatic gain control, the camera head can independently determine the binning and the A / B outputs to be used, according to defined conditions. Hysteresis can be built into the FPGA's logic to prevent jumping from one output to another. The image data produced can be marked on the camera head so that the computer software can accordingly perform the necessary processing of the image data regardless of, for example, how the actual virtual pixels are produced.

When at least two different output wells of different capacities are used in accordance with the invention and preferred embodiments thereof, the inference diagram of Figure 3 may be presented in the following form. When using an output well of lower capacity, it is checked whether the signal or part thereof exceeds the first predetermined value, for example, 75%. If this is the case, a higher capacity outlet well will be used. While a higher capacity output well is used, it is checked whether or not the signal is below another predetermined value, for example 25%. If this is the case, switch to a lower-capacity output well.

It is also possible to extend the inference scheme so that there are more than two starting wells. You can then switch to a larger outlet well instead of a smaller exit well and then to a subsequent exit well, such as an even larger outlet well. Similarly, you can switch to! ···. 25 smaller ones instead of 25 bigger ones, and more • ·. ']! the next outlet, for example an even smaller outlet.

As described above, the start-up can proceed in a predetermined manner with all the CCD sensor chips. The initial situation may be fixed and always the same: A-output on all CCD sensors, normal selected CCD sensor • ·: 30 pixels, no binning outside the CCD. Thus, shooting may always start at maximum sensitivity with the selected pixel size. Outside CCD sensor:. line, the maximum totalization by summing can also be defined separately, j · '·. if you do not want the AGC function to automatically switch to the lowest possible • · "* sensitivity. Also note that when the ENABLE signal is activated:. ** i 35 for example internally, the FPGA will execute a calibration sequence with both A- *: ** : that the B-directions can be read alternately upright or inverse 11. During this calibration, the AGC function may be automatically disable and may not commence operation when it is selected until after the calibration sequence.

As described above, when automatically switching to the less her-5 cell direction, the following column can be used to allow, if permitted, the B output of the CCD sensor chip. This can be used if, for example, when using N output, the n-pixel AD conversion exceeds 75%. This examination can be done individually for all four or eight chips. The number n is selectable between 1 and 16. By default, the number 10 can be considered to be 1. The actual number to use depends on the number of defective lines in a single chip at most.

If possible or permissible, the next column can be used to use a smaller binary internal register-to-15 binary if any of the CCD transducer B-output AD conversions still exceed 75%. At the same time, any chip-specific changes can be made from output B to output A. In this case, possible sensitizations can be allowed. In the change from output A to output B, non-sensitization can be prevented. In this situation, simultaneous AB non-sensitization can be prevented by simultaneously switching to external binning. Otherwise, the output signal can be calculated by summing the fourth part of the side, rather than a added.

• · ·

When automatically switching to a more sensitive direction, the next one *. · · J., ·. the blade can move to use a larger CCD sensor internal register • · 25 bisector, if the maximum possible binary is not already used, if at most m kappa • · · j (: over 25 of the AD conversions of all B output chips) The number m is selectable between 1 and 16 and the default value is 1. The actual number used may, for example, depend on the number of defective lines, saturated rows that are too large at any one time. CCD chip.

In this case, any possible chip-specific changes from output B to output A may prevent sensitization, and changes from output A to output B may allow non-sensitizations. In this situation, simultaneous AB-**: ** sensitization can be automatically prevented by switching to a smaller external · · ·. * ·· 35 binnacle. Otherwise, the signal *: · * of these outputs would be increased 4-fold instead of doubling.

12

If the AD conversion of any chip does not exceed 25% when digitizing the B output, then the following column can be used to switch to the A output of the chip.

Similarly, the Ceph method can be used at the end of a CCD sensor with two CCD sensor packages. The CCD sensor of the CCD sensor (Dl-5 MAX2) is capable of individually controlling the reading directions of a total of eight separate chips and the vertical binning of all chips together.

Tracking vertical binnings to different sizes on different CCD sensor chips is also possible, although it complicates both the required hardwares and software.

When altering the gain as described above, the system noise and X-ray quantum noise in the signal may also be different at different outputs (output A / output B) and / or A / D binary. Noise can be reduced when bin-binizing using an A / D converter. This may be taken into account in software where it is possible to artificially add noise to areas where it is smaller due to the binning method.

The dark current can be reduced from some pixels to several times depending on the binary mode. This can be done, for example, mathematically and programmatically. If necessary, both dark-current calibration and gain calibration can be performed for both the A output and the B output. The FPGA device enables the measurement of signals from both outputs.

However, it should be noted that the small binnings (2x2 or 1x1) do not benefit from the auto-thematic gain adjustment function.

• · · ·: ·. Figure 4 shows a table showing the CCD of the batch used. · · | ·. ·. typical charge handling capacities of the sensor. In the figure, column 4-2 represents • · 25 capacities and column 4-4 represents the number of electrons. From the table it can be seen that when the capacity of one pixel (33um x 33um) is 1 million electrons, the capacity of the read register is 3 million electrons, the output signal is * ··. ' capacitor A has a capacity of 2.4 million electrons and output amplifier B has a capacity of 4.8 million electrons. Guaranteed minimum capacities are approximately 20%.

Figure 5 illustrates an exemplary charge capacity distribution in units capable of transferring electron charges. Block 5-2 represents the typical saturation of four pixels in the "" image area, which is about 1 million charges, '*; ** with a minimum of 800,000 charges. The saturation value for each pixel is about 0.8 ...

0-j 35 1Me.

• · 13

Each pixel in the image area can be mapped to a pixel in the summation register. Block 5-4 illustrates a typical randomization value of four pixels of summing registers, about 3 million charges and, at minimum, about 2.4 million charges. Thus, the saturation value of each pixel is about 2.4 ... 3 million to 5 nano charges.

In turn, each pixel in the summation register can be associated with a read register. Block 5-6 describes the typical saturation and minimum values for the four readout registers, 3 million charges and 2.4 million charges respectively. Blocks 5-8 illustrate typical saturation of source well B, about 4.8 million charges 10 and minimum values, approximately 4 million charges, respectively. The output signal 5-9 of the output well B is typically about 3 volts, with a minimum of about 2 volts. Block 2-10, in turn, describes the typical saturation of the well A, about 2.4 million charges, with a minimum charge of about 2 million charges. The output signal 2-11 of output well A is typically about 3 volts, with a minimum of about 2 volts. In Figure 2, the basic sensitivity is about 60 mV / mR with a binary 3x3. The pixel size is about 99 micrometers.

From the example of Fig. 5, the situation can be derived in a horizontal direction.

In this case, 4x4 binning can be used to bin 4 horizontal pixels from the image area, which are about 75% full (3000000/4 = 750000), without overflow in the read register. With 3x3 and smaller binnings, pixels of the image area can be freely binned into the read index without being overwritten. . leakage.

However, it should be noted that the output wells must be designed to be small enough to avoid the loss of sensitivity of the CCD. In this case, the output voltage 5-9, • · · 25 5-11 is a suitable AD for both interference distance and: ···: sufficient resolution, which may result in limitations even when using two different • ·: capacity output wells.

• · ·

In the vertical direction, in the readout direction, in the case of 4x4 binning, the total signal level is approximately 4x4x1 Me = 16 Me (million: 30 electrons). This is approximately 6.6 times the capacity of the A output well, ··· ·, and about 3.3 times the capacity of the B output well. Then, with this binnacle, • · · *. the average processing charge, for example, at 33 μm full pixel capacity ··· • *; j before saturation of the output well is approximately 15% of the value: ···: obtained using the A output and approximately 30% of that value , obtained with the B-35 output.

• · m • · 14 When using 3x3 binary, the total signal level is approximately 3 x 3 x 1 Me = 9 Me. This is about 3.75 times the capacity of output A and about 1.875 times the capacity of output B. At 3 x 3 binnings, for example, the maximum average charge to be processed, for example, at 33 μηη: η 5 per pixel capacity before saturation of the output well, is about 26.6% for A output and about 13.3% for B output.

With a 2x2 binary, the total signal level is about 2 x 2 x 1 Me = 4 Me. This is approximately 1.66 times the capacity of the A-well. This 4 Me capacity, however, will fit entirely into the Βίο well. Therefore, with this binning, the maximum average charge to be processed, for example, at 33 µm full pixel capacity before output well saturation, is about 60% with A output, but about 100% with B output.

If no binning is done, the total signal level will be about 1Me, or 15 times the pixel level. This allows both internal registers and output wells to process the signal without the risk of saturation.

From Figure 5, it can be seen that the less sensitive B output is unable to process the signal from the unsaturated image area with 4x4 binning if this exceeds about 30% of the physical pixel charge storage capacity 20. However, this problem can be solved by the invention and its preferred embodiments.

: According to the invention and its preferred embodiments, the sensitivity • · · · and thus the dynamics can be increased by various methods. Dynamiik- • *: *. *. for example, it can be increased simply by changing the binnacle. Binna-. ·. ··. The 25 doors can be changed by moving to a larger or smaller binnacle.

• ·

The binning can be changed several times and the binning can be changed, for example, outside the CCD sensor.

• · ***** Instead of changing the binnacle, you can switch to a larger capacity output well. For example, instead of the A: 30 output, you can switch to a higher capacity B output. It is also possible to · · · switch to another, for example, an even larger starting well.

! · · ·. Still other options for increasing dynamics may be to move the • • [** 'sin to use a larger capacity output well and then:.' * I 35 to change the binning or to change the binning first and then to use a larger capacity outlet well.

15

When the sensitivity, the dynamics of the arrangement is changed, it can be done by changing the binning in response at least in part to the control signal. The control signal can be defined, for example, in advance, before changing the binning. The control signal may also be based directly or indirectly on the signal, which may depend on, for example, the amount of light seen by the CCD sensor. Alternatively, the control signal may be based on a signal output from the CCD sensor. The control signal may also be based on another signal.

The dynamics of the arrangement can be changed during shooting, or before or after shooting. The binning can be changed, for example, between the image area 10 and the shift register and / or between the shift register and the output register

Further, the arrangement may comprise means for normalizing the image signal. The image may be manipulated in normalization so that the image (s) subsequently appear (s) to be viewed, e.g., without any change in the gray scale. The normalization means may include digital summing and / or darkening of the signals produced by the sensor 15 physically adjacent pixels, which may depend on binning, and / or correction of gain. Such summing and / or correction may be carried out partially or completely, for example electronically and / or software.

The object of the invention and its preferred embodiments is thus to extend the dynamics of the CCD sensor, for example by external means, to the greatest extent possible. In accordance with the invention and preferred embodiments thereof, amplifiers can be optimized for noise and speed, for example, real-time TDI readout of an x-ray image when charge wells have different capacities. By doing so, the dynamics processed by the CCD can be • ·) ·> ·. For example, 25 areas will be doubled or quadrupled when using larger binnings, such as more than 2x2 binnings.

:: i .: In addition, the signals of both output amplifiers can be • · '··· * digitized simultaneously or alternately. Which signal from the output amplifier is used depends on the signal itself. With a suitable arrangement, the · · · 30 CCD sensor, which may consist of multiple CCD sensor chips, can process the · · · signal of each CCD sensor chip individually and also decide separately which amplifier to use in each chip. This decision can be made with the column * -. ···. blast, and thus dynamically monitor the signal level and maximize it throughout the • · image area. Such automatic selection of the register reading direction and thus of the amplifier can be made independently, for example, by a controlling FPGA device. Information about which amplifier has been used can be transmitted in the • • 16 line-by-line image data and also by CCD, so that the calibration program can take this into account when processing the image data. Image data can be transmitted at 16 bits / pixel, even if it is a 14-bit conversion.

For example, if a 14-bit A / D conversion is used, it can be easily upgraded to virtually 15-bit (dynamics doubling if the output amplifier wells have a capacity ratio of 2: 1) further using the same A / D conversion.

Thus, the CCD sensor camera can be selected to use output A or output B. This selection can be made, for example, manually, or automatically by the AGC-10 device on a chip-specific basis, for example, with all eight chips, chips. However, both register binning and horizontal binning are always the same for all chips. If this is not done, image data would be produced on the computer where not all pixels would be the same size. While the camera's camera head moves to use the 15 smaller binnings internally in the CCD sensor, the virtual pixels remain the same size. Missing binning inside the sensor can be invisibly replaced by AD binning.

Thus, binning is common to all chips, while the A / B direction can be individually selected manually or automatically with the aid of the AGC 20 for each chip individually. It is also possible to differentiate the AD binning to serum specific.

: In a preferred embodiment, some of the chips may be moved backward • · · ·: ·. while using the more sensitive A-output, other chips can produce such a large signal that both B-output and external · · 25 bins are required. In other words, if one of the B-outputs of a chip gives too much signal to move to a smaller internal binning, the other chips may • • · be allowed to move back in the A-direction if the signal drops too small.

• · * ··· * The control logic for A / B outputs, for example a total of 8 chips, may be separate, but there may be common binning logic inside the FPGA device.

Thus, the dynamics of the 30 CCD sensor A / D converter (14 bit A / D converter in DIMAX2 device = 16384 discrete levels) can thus be extended to 8x (17 bit sex = 131072 discrete levels) in accordance with the invention and preferred embodiments thereof. ). This extension occurs automatically at the end of the CCD sensor (D1- • *: * MAX2) and depends on the image signal. Dynamics can be doubled when switching to a higher capacity output well instead of a smaller output well. The dynamics can be further increased fourfold by switching from 4x4 to Binna instead of 4x4 and then 4x1 to Binna. All in all, this way the dynamics can be increased by the above amount, ie by eight times.

5 The sensor is capable of transmitting image data in true 17-bit format to a computer. In addition, it should be noted that image data can be compressed by a computer to 12-bit (in future 16-bit) as soon as the minimum and maximum intensities of the image are known. Regardless, it is advantageous to describe the object itself with maximum dynamics. Gamma correction can be performed concurrently by converting the image data to 12 bits, in order to preserve the maximum dynamics of the final image.

Pixel binning can also be performed alternately using binning, whereby two pixels are binned in the register direction of the CCD and sampled, and then another pixel is binned and the result is added to the previous binned pixel. This type of binning can be used if the initial binning in the registry direction is about three times selected and if you need to move to a less sensitive direction while the AGC is activated.

During this triple binning, symmetry-20 line errors may occur when switching to external summing binning, if 2 pixels binned inside a CCD sensor are summed first and then another discrete CCD device. However, this situation can also be taken into account programmatically.

The AGC function is only dependent on the registry • binary • · 25. Horizontal, TDI biasing does not matter. Horison- • ·. * '! the tilt may be different from the vertical. However, in this case, the produced pixels are not of equal square size.

The invention and its preferred embodiments can also provide for the CCD sensor to have separate outputs for at least two different capacities.

• · ·

An arrangement according to the invention and preferred embodiments thereof may be integrated on a single CCD chip using one or more integrated circuits.

"··. It is also possible to integrate the device with the CCD preamps, for example, • PGA amplifiers. The amplification of these amplifiers is adjustable * · 35, for example between x1 ... x6 in 64 steps (today x1).

By using the invention and its preferred embodiments and adjusting the gain to the signal level (Ceph / Pan), an optimum result in terms of both noise and dynamics can be obtained. Because the signal level, especially in Ceph images, is extremely low, additional gain can also reduce the smaller image processing artifacts and system noise. Furthermore, the device according to the invention and its preferred embodiments still prevents saturation. It is also possible, for example, in the same skull photography, to incorporate soft parts, tissues, into the image, for example, programmatically (Soft-tissue filter).

A CCD sensor according to the invention and preferred embodiments thereof produces 16-bit image data with very high dynamics, pixels, the structure of which is illustrated by way of example in Figure 2. Thus, 2 bytes are required to represent one pixel gray level. The first byte in the data stream has the lower 8 bits (AD0-AD7) and the next byte 15 the upper 8 bits (AD8-ADD1). The A / D conversion itself is 14-bit. This amount of A / D conversion bits can be justified so that the system's own noise is very small.

The CCD sensor according to the invention and its preferred embodiments thus solves the problems of a limited dynamic range and slow recovery from an overdrive situation. Using a 14-bit conversion and keeping the system noise low achieves the ideal situation where one: A / D converter step corresponds to the noise level of the CCD sensor output amplifier • · · · I * ... The signal-to-noise ratio of the final image is determined by the quantum • ': *. ·. tikohina. Under normal shooting, the top two bits (ADD1 and ADDO) are 16- *. * ··. The 25-bit pixel value can be zeros.

• ·. * “However, there are two exceptions. The invention and its advantageous · · · *

::: Operation of automatic gain control according to J embodiments AGC

• · ***** may have shifted the pixel blurring of the CCD sensor with a large amount of radiation to a form where the index blurring is made with pixels thinner than • 1 bar. To maintain the same situation, the sampled values of consecutive pixels can be summed within the FPGA device.

Thus, for example, the binning of x4 may change to x2 + x2 or at worst] ···. in the case x1 + x1 + x1 + x1. In this case, the 16-bit pixel value · · * ”approaches OxFFD when the four 14-bit numbers are summed.

: Λ: 35 However, the AGC can handle all this independently. In this summation, · · 19, the signal can be subtracted from the sum of times the offset of the silicon stream.

It will be obvious to a person skilled in the art that as technology advances, the basic idea of the invention can be implemented in many different ways. The invention and its embodiments are thus not limited to the examples described above, but may vary within the scope of the claims. In the context of the inventive idea, the sensitivity can be adjusted in other ways.

· 1 t 1 t t 1 t1 mm mm • · 1 1 1 1 1 1 1 1 1 1 1 1 1 ··· * 1 • • • • • • • • • • • • • • · · · · · · · · · · · · · · · · · · · · ··· «· • · · ·

Claims (46)

A readout arrangement for reading a CCD sensor (1-1) arranged on a camera used for panoramic and / or cephalophotography, which CCD sensor (1-1) is configured for use with TDI technology and comprising a 5th detector (1-2) with charges an active area comprising receiving pixels in the vertical rows; a reading register (1-4) operatively associated with said active area; - means for transferring the charges from the active area to the read register (1-4); means for transferring charges to the output (1-4a, 1-4b) of the read register (1-4); - at least one readout well (1-6, 1-8) operatively associated with the read register (1-4); and 15. means for transferring charges from the output (1-4a, 1-4b) of the read register (1-4) to at least one readout well (1-6, 1-8), characterized in that the arrangement further comprises: means for changing the dynamics by changing at least a vertical binnings of the charges by the sensor, at least in part in response to a control signal based on a signal read from the sensor. 2. An arrangement according to claim 1, characterized in that the arrangement comprises means for changing the binning during imaging. . . Arrangement according to Claim 1 or 2, characterized in that the means change the binning between the image area and the shift register at least partly according to the control signal. • 1.ί Arrangement according to Claim 1 or 2, characterized in that the means change the binning between the shift register and the output register ···: ·. at least in part according to the control signal. Arrangement according to claim 1 or 2, characterized in that the means change the binning between the image area and the shift register and the shift register and the output register according to the control signal. An arrangement according to any one of claims 1 to 5, characterized in that the control signal is predetermined. • · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Arrangement according to one of Claims 1 to 6, characterized in that the control signal is based directly or indirectly on a signal which is dependent on the amount of light seen by the CCD sensor. Arrangement according to one of Claims 1 to 7, characterized in that means for measuring the signal generated by the charges are provided in the sensor or in a functional connection with the sensor, and means for selecting at least partially based on said measured signal 8). An arrangement according to any one of claims 1 to 8, characterized in that the arrangement further comprises means for normalizing the image signal. An arrangement according to claim 9, characterized in that the normalization means comprise digital summation of the signals produced by the sensor physically adjacent pixels. Arrangement according to Claim 9 or 10, characterized in that the normalization means comprise correction of the dark current and / or gain dependent on the binary. Arrangement according to Claim 10 or 11, characterized in that the summing and / or correction is carried out partially or completely electronically. Arrangement according to Claim 10 or 11, characterized in that the summing and / or correction is carried out partially or completely by software. Arrangement according to one of the preceding claims 1 to 13, characterized in that the arrangement comprises at least two, the first and the second,. 25 read wells (1-6, 1-8) arranged in connection with the read register (1-4) having different capacities and means for measuring the signal generated by the charges in the sensor or in the functional connection with the sensor. · • V and selection means, at least in part, on the basis of said measured signal to determine which readout well (1-6, 1-8) is used by the CCD sensor to read out the charges indicated by 30 (1-1). "·· 1. A sensor arrangement according to claim 14, characterized in that its selection means are adapted to decide during the sensor readout whether the readout well (1-6, 1-8) to be used is changed. : 2 · Arrangement according to one of Claims 1 to 15, characterized in that the read-out well (1-6, 1-8) is an amplifier. • · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Arrangement according to one of the preceding claims 14 to 16, characterized in that the read-out wells (1-6, 1-8) are located at each end of the read register (1-4) or at the other end of the read register. Arrangement according to one of the preceding claims 14 to 17, characterized in that the capacity of the second discharge well (1-6) is about twice the capacity of the first discharge well (1-8). Arrangement according to one of the preceding claims 1 to 18, characterized in that a register is arranged between the detector (1-2) and the read register (1-4), operatively connected therewith, for summing up the charges before they are transferred to the read register (1-4). ). 20 Based on the signal from the CCD sensor. Arrangement according to one of the preceding claims 9 to 19, characterized in that it further comprises means for processing the charge of the pixels before transferring them to the read register (1-4). Arrangement according to one of the preceding claims, characterized in that it comprises means adapted to determine the binary to be used and / or the output well to be used based on at least one clock pulse. Arrangement according to Claim 21, characterized in that it further comprises means for at least partially changing the clock pulse Arrangement according to one of Claims 14 to 22, characterized in that it comprises selection means adapted to select through which readout well (1-6, 1-8) the signal from the CCD sensor (1-1) is read and means adapted to perform an A / D conversion to a signal or means adapted to perform an A / D conversion to a signal of at least two read wells and selection means adapted to select which outgoing • • j 'read well (1- 6, 1-8), the signal from the CCD sensor (1-1) is read. : V An arrangement according to claim 23, characterized in that it comprises means adapted to check (3-4) whether the A / D-: 30 conversion exceeds a predetermined first threshold value; and if the A / D conversion • · · ·. ···. exceeds a predetermined first threshold, in addition to verifying (3-14) whether a higher capacity excavation well (1-6, 1-8) is used and, if not used, to move (3-16) to use the next column to read higher • · A man-capacity excavation well (1-6, 1-8) instead of a capacity-excavation-35 well (1-6, 1-8). · · «« 1 1 1 1 1 1 1 1 1 1 1 An arrangement according to claim 23 or 24, characterized in that it comprises means if the A / D conversion exceeds (3-4) a predetermined first cut-off value and a higher capacity excavation well (1-6, 1-8) is used, to check (3-18) whether the maximum off-sensor off-register has already been reached and, if not, to move (3-20) to read the next off-sensor off-line in order to read the next vertical line. An arrangement according to claim 25, characterized in that it comprises means adapted to move (3 to 22) for use with a lower drainage well (1 to 6, 1 to 8) if the A / D conversion falls below another predetermined limit. value. An arrangement according to claim 26, characterized in that it comprises means, if the A / D conversion does not exceed a predetermined first threshold value, to check (3-6) whether the A / D conversion falls below a second predetermined limit value. value, and if the A / D conversion falls below another predetermined threshold value to check (3-8) whether the lowest register-facing external binning is achieved and, if not, move (3-10) to read the next vertical line to the smaller external binning. An arrangement according to any one of claims 14 to 27, characterized in that it comprises means, if the smallest external binning of the register has been achieved, to move (3-12) to read the next vertical row to use a lower capacity readout (1-6, 1). -8). A method for expanding the dynamics of a CCD sensor (1-1) in the context of panoramic and / or cephalostatic X-ray imaging, wherein . The 25 representations are detected by the TDI technique, characterized in that the method comprises «· · '' 1 :: 1 steps: • · •“ - receiving charges in a • · ·: active area comprising pixel vertical lines; - reading (3-2) the first •; 1: 30 columns of the active area pixels from the active area to the read-out register l :: \ (1-4); • · - Transferring the allocations to the output of the readout register (1-4) (1-4a,: ·. 1'4b): 2. Transferring the bookings to the output of the readout register (1-4) • · · 35 (1-4a, 1-4b) to the output well (1-6, 1-8); - changing the dynamics by changing the charge biasing of the sensor, at least in the vertical row direction, at least partially in response to a control signal based on the signal read from the sensor. A method according to claim 29, characterized by changing the binning of the charges during imaging. 31. A method according to claim 29 or 30, characterized in that the binning is changed according to the control signal. A method according to any one of claims 29 to 31, characterized in that the binning between the shift register and the count register is changed. Method according to one of Claims 29 to 32, characterized in that the binning between the image area and the shift register is changed. The method according to any one of claims 29 to 33, characterized in that the arrangement comprises at least two read wells (1-6, 1-8) arranged in connection with the first and second read registers (1-4), has different capacities and measures the signal generated by the charges and determines, at least in part, on the basis of said measured signal, which readout well (1-6, 1-8) is used to read out the charges indicated by the CCD sensor (1-1). A method according to claim 34, characterized by selecting via which readout well (1-6, 1-8) the signal from the CCD sensor (1-1) is read and the A / D conversion is performed or the A / D conversion is performed. at least two readout wells and selecting which output; ... The signal from the CCD sensor (1-1) is read through the 25 wells (1-6, 1-8). The method of claim 35, characterized in that it is checked (3-4) whether the A / D conversion exceeds a predetermined first: V threshold; and if the A / D conversion exceeds a predetermined first: ... threshold, additionally checking (3-14) whether a higher capacity 30-well excavation well (1-6, 1-8) is used and if not , move to (3-16) to use • · · · .1 ··. reading one of the next columns, a higher capacity readout than a smaller capacity readout (1-6, 1-8). The method according to any one of claims 29 to 36, characterized by measuring the signal level 35 of the signal read from the CCD sensor (1-1), and if the signal level exceeds a predetermined threshold value, the charge reading is adjusted. from the sensor so as to reduce the number of pixels to be transferred to the well, before reading out the charges in the well, and if the signal level falls below a predetermined threshold, reading out the information by incrementing the number of pixels 5 to be transferred to the reading well before reading out the charges in the read well. 38. A method according to claim 37, characterized by determining a predetermined threshold value as a function of the saturation level of the excavation well. A method according to any one of claims 37 to 38, characterized in that a sensor comprising at least two different capacity readout wells is used to measure the signal level of the readout signal, and if the lower capacity output well saturates during the measurement, a higher capacity readout well is used. The method of claim 39, characterized in that if one of the wells is saturated, the charge binning outside the sensor is increased. A method according to any one of claims 35 to 36, characterized in that if the A / D conversion exceeds (3-4) a predetermined first cut-off value and a higher capacity excavation well (1-6, 20 1-8) is used, 3-18) whether the maximum off-sensor off-register has already been reached and, if not, moving to (3-20) to read the next off-sensor off-peak. A method according to claim 41, characterized by: ... switching (3-22) to a lower capacity excavation well (1-6, 1-8) i :: 1 if the A / D conversion is below another a predefined threshold. The method of claim 42, characterized in that: if the A / D conversion does not exceed a predetermined first limit: ...: value, (3-6) is checked. whether the A / D conversion falls below another • predefined threshold and • if the A / D conversion falls below another predefined threshold • · · ·. ···. further checking (3-8) whether the smallest external binning in the register direction has been reached and, if not, moving to (3-10) to read the next vertical row .. the smaller external binning. • · • 1 ' 44. The method of any one of claims 29 to 43, characterized in that, if the smallest off-line binning of the register is achieved, moving (3-12) to read the next vertical row to use a lower capacity readout (1-6, 1-8). 45. A method according to any one of claims 29 to 44, characterized in that the charge biasing by the sensor is reduced based on a control signal, by which the readout capacity utilization exceeded the first predetermined threshold, such as 75% of its maximum. A method according to any one of claims 29 to 45, characterized in that the charge binning on the sensor is increased based on a control signal, whereby the utilization rate of the readout capacity dropped below another 10 predetermined threshold, such as 25% of its maximum. • '' '' '•' '' '' '' '' '' '' '' '*' '' '' * '*' '' '' '*' '' '' '' * '' '' '' * '' '' '*' '' '' '' '*' '' '' '' '' '' '' '' '' '' '' '' '' '' '? · • · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · To– werequil - ·