JP2008536422A - CCD sensor and method for expanding dynamic range of CCD sensor - Google Patents

Abstract

  The present invention relates to a readout device for reading out a CCD sensor (1-1). The CCD sensor (1-1) functions as a detector (1-2) having an active region including a pixel that receives charges, and the active region. Connected read register (1-4), means for transferring the charge from the active region into the read register (1-4), the output of the read register (1-4) (1-4a, 1-4b) means for transferring to, at least one read well (1-6, 1-8) operatively connected to the read register (1-4), charge of the read register (1-4) Means are provided for transferring from the output section (1-4a, 1-4b) into at least one read well (1-6, 1-8). The invention is characterized in that the readout device further comprises means for changing the dynamics by changing the binning of the charges at least partly in response to the control signal.

Description

  The present invention relates to a read-out arrangement for reading a CCD sensor according to the preamble of claim 1. Furthermore, the present invention relates to a method for enlarging the dynamics of a CCD sensor according to the preamble of claim 31.

  A CCD device (charge coupled device) can be defined as a semiconductor device capable of accumulating and collecting charges by charge movement. These charge transfer elements are used for dynamic variable storage elements that characteristically have a high information density. In a CCD sensor intended for X-ray imaging, charges used for image generation formed on physical pixels can be combined and binned. Binning in CCD sensors results in substantially larger image pixels. However, in certain situations, processing of the charge of these combined pixels can be problematic. Especially at high signal levels, the signal coming from the image area may be very large, so that with the selected binning charge cannot be combined in the CCD sensor without the risk of saturation of the output amplifier. This can be considered in part by designing the readout register and the charge well of the output amplifier so that they have a charge capacity higher than the charge capacity of the pixel. However, if the charge well of the output amplifier is enlarged too much, the voltage generated thereon will drop, and thus the signal to be generated will also drop.

  Currently, the resolution of digital images is already approaching the level of film-based systems, and in some cases it can be exceeded. However, it is known that the dynamic range of the CCD sensor, i.e. the ratio of maximum signal to open circuit noise relative to the basic sensitivity, is smaller than the dynamic range of conventional film-based systems. In this context, sensitivity can mean the resolution within the background noise, ie the signal size that can be resolved from the background noise.

  A typical uncooled CCD device operating in the MPP mode has a dynamic range of about 10,000: 1 to 20,000: 1. The number giving the dynamic range represents the ratio between the saturation voltage and the RMS noise. If this dynamic range is effectively utilized, it will be possible to extract as many grayness levels as the A / D conversion used allows. For example, for 14 bits, the total number of available gray levels is 16,384.

  However, these numbers are not mutually comparable when film-based systems and digital systems are compared to each other. Even if the film system utilizes only a small percentage of the total dynamics, there are still a very large number of available gray levels. For example, when considering the dynamics of a film (1,000: 1000), it can be seen that this range is divided into more than 16 separation levels.

  In addition, CCD-based sensors, like film-based systems, are not allowed in overexposure situations, where reciprocity laws (slow saturation, sigmoidal curve of the film) Along with this, “compression”, that is, expansion of dynamics is brought about. Thus, it is conceivable that the inherent non-linearity is addressed here, which can also be understood as a gamma correction of the film itself. With digital sensors, visible boundaries and artifacts are generated as soon as the highest dynamic range is reached.

  The signal amplifier and A / D converter (A / D, analog-digital) connected after the sensor is designed with the aim of making available the full dynamic range provided by the CCD sensor. As mentioned above, existing CCD sensors can provide a dynamic range of even more than 20000: 1. In an ideal state, the quantization step of the A / D converter is slightly below the noise level of the CCD sensor itself. However, this means that in order to digitize the image, it is necessary to use high-speed A / D conversion exceeding 14 bits.

  In other words, the charge placed on the receiving pixel can be so large that it cannot be processed in the binning state without risk of saturation in the read register and / or the charge well of the output amplifier. . This is particularly a problem for larger binning operations, such as 3 × 3 and 4 × 4 (horizontal × vertical, read count from image area to output register and read count from output register to read well). An image formed in the image area can be completely used without being saturated, but cannot be read out without saturation in the binning.

  In both cephalostatic applications (Ceph) and panoramic images (Pan), there is an area under the jaw that receives radiation directly without intermediate tissue that attenuates the radiation. In these situations, the danger of saturation is obvious, especially if the system is tuned for optimal reception of signals through the subject if it is normal. This makes it impossible to image, for example, a soft tissue region, and all image information is lost in a saturated region.

  Therefore, an object of the present invention is to develop a method and an apparatus for implementing the method so as to solve the above problems.

The object of the invention is achieved by a method and device characterized in that it is presented in the independent claims. Preferred embodiments of the invention are disclosed in the dependent claims.
The present invention is based on changing the binning and / or using at least two different capacity charge wells and dynamically selecting the read well to be used during sensor readout.

  The method and system of the present invention has the advantage of extending the dynamic range of the CCD sensor and thus preventing the sensor or a portion thereof from being saturated.

  The present invention will be described in detail below with reference to preferred embodiments and the accompanying drawings.

  In the following, for the present invention and its preferred embodiments, a typical CCD sensor (eg manufactured by Atmel or Thomson) and an automatic gain control function (AGC, automatic gain control) are also provided. Description will be made with reference to an example of the charge capacity specification optimized by considering the above. The sensor can have the following characteristics, for example.

1) Saturation charge of separated single pixel (size: 33 μm × 33 μm): 600,000 electrons 2) Saturation charge of readout register: 1.800,000 electrons 3) Saturation charge of output amplifier A: 2,400,000 Electrons 4) Saturation charge of output amplifier B: 4,800,000 electrons

When the sensor is operated in the horizontal direction (TDI direction, time delay integration), with 3 × 3 binning, the readout register outputs 100% signal of 3 consecutive pixels (3 × 600K = 1800K, K = kilo = 1000) Can be held. In 4x4 binning, four horizontal pixels charged to 75% of their capacity (1800K / 4/600 ^* 100) can be added without overflow. Overflow can mean that an electronic component, such as a capacitance, has no capacity left for additional charge. In the overflow in the image area, the extra electronic charge can move in the horizontal direction, and in the overflow in the output register, the extra electronic charge can move in the vertical direction.

  In the vertical direction (reading direction), the situation is as follows. In 2 × 2 binning, two pixels with 50% charge can be added to one output A and three pixels with 100% charge can be added to the second output B without overflow. In 3 × 3 binning, three pixels with 44% charge can be added to output A and three pixels with 88% charge can be added to output B without overflow. In 4 × 4 binning, 4 pixels with 25% charge can be added to output A and 4 pixels with 50% charge can be added to output B without overflow.

  From this, it can be seen that when the output unit A is used and the signal exceeds 25% of the charge capacity of the physical pixel, even the low-sensitivity output unit B cannot process the signal coming from the image area without saturation. This situation can be corrected by applying the invention and its preferred embodiments.

  FIG. 1 shows a CCD sensor for increasing dynamics according to a preferred embodiment. Here, reference numeral 1-1 indicates a detector that is the entire CCD sensor module. The active area of the detector including the charge receiving pixels is indicated by reference numeral 1-2. The image forming surface can have a substantially flat structure having an arbitrary shape.

  For example, image information of a two-dimensional CCD sensor can be read out by using a read register 1-4 arranged on at least one edge, which is functionally connected to the active region. In this register, it is possible to load, for example, one pixel column at a time. The pixels in the pixel column can be combined with each other and binned, for example. The sensor also comprises means for transferring the charge to the outputs 1-4a, 1-4b of the read register 1-4. After the transfer, the register is read out continuously, for example by transferring the charge from one binned or unbinned pixel into the charge wells 1-6, 1-8 of the output amplifier. Can be further transferred and output from the CCD sensor 1-1 1-10, 1-2.

  Thus, by using an appropriate configuration, charge can be transferred in the register in the desired direction, in the direction of a small output well, or in the direction of a large output well. The selection of the output well to be used during imaging is dynamically optimized during imaging, so the size of the output well and / or binning to be used can be determined for example by an electronic circuit or a suitable selection program or these Selected by combination.

Output wells 1-6, 1-8 of the output amplifier may be located at either end of resistor 1-4, or two or more wells and / or amplifiers are located at one end of the resistor. Alternatively, at least one well may be located at each end of the register. According to the present invention and one preferred embodiment thereof, the read register comprises at each end at least one charge well, read wells 1-6, 1-8, and an amplifier functionally connected thereto. .
An amplifier and / or buffer and / or buffer amplifier may be operatively connected to the well.

  Such dual amplifiers can be designed for various applications. For example, one of the amplifiers is optimized for the so-called slow scan mode, in which case the noise can be optimized to be as small as possible at the expense of speed. The other amplifier is optimized in a so-called fast mode, in which case the readout speed can be optimized to be as fast as possible, at the expense of noise.

  However, in both conventional amplifiers, the charge wells of the output amplifier have the same capacitance. In accordance with the present invention and its preferred embodiment, an output well having at least two different capacitances is formed. These capacities are preferably substantially different from each other, for example, so that the large output well has about twice the capacity of the small output well. Other ratios can also be used. If the number of wells is greater than two, the capacity of at least two wells can be different from each other.

  Thus, the present invention and its preferred embodiments are based on the use of at least two different capacitance charge wells and the possibility of dynamically selecting the output well to be used during readout. This selection can be performed based on signal data, for example, an image signal, depending on the signal.

  Compared to the situation where only one output amplifier is used or two output amplifiers with the same capacitance are used, this configuration saturates the internal moving well and readout well (not the image area) of the CCD sensor. Provides the advantage of being able to avoid. Furthermore, by applying the present invention and its preferred embodiments, it is possible to avoid saturating the A / D converter. Both situations are very likely to occur when the pixel charge is combined, ie binned, with a pixel larger than 2 × 2.

  FIG. 2 shows the structure of the image data set. In the figure, the 14 least significant data bits (AD0 to AD13, FIG. 6: 6-51, 6-53, 6-55, 6-57) are assigned to the FPGA device (FIG. 6: 6-40) (FPGA, 16-bit adder (FIG. 6: 6-41, 6-42, 6-43, 6-44) of the image data processing module of the field programmable gate array) and a register (6-45) capable of storing intermediate sums 6-46, 6-47, 6-48). The adder can be reset before sampling each pixel, and the 14-bit calculation result obtained from the A / D converter can be added once to the adder. It is also possible to add the value +1 to the sum so that the result is always greater than zero. The result is a 14-bit number, with the two most significant bits (ADD0 and ADD1) being zero.

  In certain cases, four consecutive A / D converter values are added to this adder, so that the calculation results approach a 16-bit maximum. When further considering that each chip of a CCD sensor can have two outputs (output A and output B, one of which can provide a dual signal with the same radiation), It can be noted that the overall dynamics is 17 bits, ie 131072 gray level (16384 × 4 × 2).

  One CCD sensor (FIG. 6: 6-20) has one or a plurality of, for example, four chips (FIG. 6: 6-21, 6-22, 6-23, 6) sequentially connected in sequence. -24). Each chip can be supplied with a separate clock signal. In Cef operation, two identical CCD sensors are used. Each chip includes two output units (FIG. 6: 6-25 to 6-32). One of these can be a so-called high-sensitivity output unit with high sensitivity, that is, an A output unit, and the other can be a so-called large-capacity output unit with low sensitivity, that is, a B output unit. Thus, one CCD sensor can have a total of eight digital outputs, for example only four of which are used simultaneously. In practice, the ratio of the capacities of the A and B outputs is very precisely ½, ie the B output signal is equal to half the A output signal with the same amount of radiation. .

  If multiple chips are used, each of the different chips can process data obtained from a given patient part and / or function in different modes, each chip individually or individually Can be controlled.

  The output used can be manually selected by a control register, for example (switches 6-33 to 6-36 in FIG. 6). Alternatively, an AGC function or a test function can be determined for the output. All eight outputs can be digitized by an A / D converter, and the number of A / D converters can be, for example, three. Each A / D converter can include a three-input multiplexer, or selector, so the total number of channels to be digitized in this case is nine. The extra tenth channel can be used in testing and applied to measure electronic circuit noise and A / D conversion.

  FIG. 6 shows a state in which the selection elements 6-33 to 6-36 after the output wells 6-25 to 6-32 are transferring one of the wells to one A / D converter 6-37. Show. Alternatively, A / D conversion of the outputs of both wells can be performed and then the digitized signal can be selected by the selection element for one of the wells to be used. The selection element can also form part of an A / D converter, for example an analog switch or a digital switch. FIG. 6 also shows a possible solution 6-100 for carrying clock and / or control signals from the FPGA element 6-40 to the CCD sensor 6-20.

  AGC function means automatic control of level or gain. However, the AGC function does not mean the gain of the programmable variable PGA amplifier (programmable gate array) in the A / D converter, and the gain of the amplifier can be adjusted within a range of 1 to 6, for example. This gain can be adjusted separately for each CCD chip, and this adjustment is mainly used for optimization of the basic sensitivity according to the imaging conditions (pan / ceff).

  The AGC method can be used in a camera by, for example, the following two methods. Either one of the output amplifiers A or B of each CCD sensor can be used within the applicable range. Since the B amplifier has a signal that processes about twice the capacity of the A amplifier, virtually one additional bit is obtained in the A / D conversion. Alternatively, binning performed outside the CCD sensor can be used. However, this is only possible when binning is performed in the direction of the read register.

  In the case of high binning, for example 4 × 4 binning, if the B output amplifier is saturated, it can be changed to low binning, for example 4 × 2 binning in the CCD sensor. The pixel value can then be sampled twice by the A / D converter, and the addition can be performed, for example, in an FPGA device in an arithmetic unit. Multiple additions of shifts that occur in electronic circuits can be compensated by computer software. This external addition can take the form of 4 × 1 binning and four addition operations.

  For example, to reduce binning instead of adding four charges, combine only two pixels in the charge well, digitize that pixel, take the next two pixels, digitize that pixel, Only in that case, the digitized results can be added by digital processing.

  In the manner described above, the overall dynamics can be increased to 17 bits, of which 14 bits are derived from A / D conversion, 1 bit from the output of the A or B amplifier, and 2 bits from the external addition. Can be performed four times as described above.

  FIG. 3 shows an example of a method for performing imaging, and shows control logic for controlling automatic gain control (AGC) of the FPGA device during imaging. Imaging is normally started with a selected initial value, ie, default binning. Initially, the output A of each CCD sensor chip can be used. Since the read register of each chip can be controlled individually, it is possible to select the direction in which the charge should be shifted in a chip specific manner. As described above, the charge can be shifted either in the direction of the output part A (1-8: FIG. 1) or in the direction of the output part B (1-6: FIG. 1).

  The logic circuit of the FPGA device can continuously and continuously monitor the A / D conversion signal of each chip. In step 3-2, a new vertical column is read into memory from the CCD sensor. In step 3-4, any one of the currently used A / D converted CCD sensor outputs (FIG. 6: 6-50, 6-52, 6-54, 6-56) is A / D converted. A check may be performed to see if it has produced a signal, for example, greater than 75% from the instrument. (Information on the signal size can be transferred to the inference block and to the state machine, for example (FIG. 6: 6-50, 6-52, 6-54, 6-56). If the value exceeds 3/4 of the range of the A / D converter, for example, a low-sensitivity output unit and output unit B can be used in a chip that satisfies this condition. If all outputs are below the first threshold, whether all currently used CCD sensor outputs have generated signals from the A / D converter that are below a second predefined threshold, eg, 25% Can be checked in steps 3-6. If all outputs are below the second threshold, a check can be made in steps 3-8 to see if the minimum register direction binning outside the CCD sensor has already been reached. If the minimum external binning has not yet been reached, the procedure can proceed to steps 3-10 where it is possible to move to the next smaller external binning size in the next vertical column. On the other hand, if the minimum external binning has already been reached, then in step 3-12, in the next vertical column, if the CCD sensor B output remains below the second threshold, the output A is used. Is possible. In other words, if the signal correspondingly corresponds, for example, completely below a certain predefined second value, e.g. 1/4 of the range of the A / D converter, the chip that meets this condition is highly sensitive. It is possible to use the output unit and output unit A.

  If in step 3-4 at least one output exceeds 75% of the signal from the A / D converter, the procedure can proceed to step 3-14. Here, any one of the outputs that generated a signal greater than 75% can be checked to see if it is a B output. Otherwise, if it exceeds the A output of the sensor, it is possible to use the B output in the next vertical column in steps 3-16.

  The output unit B is used, that is, the B output is digitized, but the signal is 3 in the range of the A / D converter in any one of the A / D converters of the CCD sensor chip. If it still exceeds / 4, it can be checked in step 3-18 to determine if external binning in the maximum register direction has already been reached. If the external maximum binning in the register direction has not yet been reached, in step 3-20, use the increased register-direction arithmetic external binning size in the next vertical column, for example, by one step for all chips. Is possible. If necessary, binning can be gradually changed from 4 × 4 level to 1 × 4 level and back to 4 × 4 level. This reduction in binning cannot be seen externally in the image data. This is because in addition to binning being performed in the sensor, binning is also performed after A / D conversion, i.e., multiple A / D conversions per pixel can be performed. The result is still the same. This is because this is taken into account in the dark current compensation. Dark current can mean a leakage current caused by non-idealities in silicon, and as a result, electrons leak into the pixel and generate a base signal. Since the temperature always rises about + 7 ° C., the signal can double. Dark current is not uniform, but can affect different pixels differently.

  The structure and timing of the FPGA device can also be optimized for this property. In stage 3-22, use of the A output can be resumed for CCD sensors whose B output has a level below a second threshold, eg, 25%. If the external maximum binning in the register direction has already been reached, the procedure can proceed from step 3-18 to step 3-24. Similarly, after steps 3-10, 3-12, 3-16 and 3-22, the procedure can proceed to step 3-24 to wait for digitization of the next vertical column.

  Thus, when the AGC function is activated, in the gain control automation device, the camera head alone makes its conclusion regarding the binning and A / B output to be used, according to predefined conditions. The logic circuit of the FPGA device can be configured to include hysteresis to prevent it from jumping from one output to the other. Once the image data has been generated, the computer software is marked by the camera head so that it can be executed in response to the operations required to process the image data, for example, regardless of how the virtual pixels are generated. Can be turned on.

  According to the present invention and its preferred embodiments, when at least two different output wells having different capacities are used, the state diagram of FIG. 3 can be presented in the following form. When a small volume output well is in use, it is checked to determine if the signal or part thereof exceeds a first predefined value, eg, the value 75%. In this case, a large output well is used. Again, when a large output well is used, it is checked to see if the signal or part of it remains below a second predefined value, for example the value 25%. . In this case, a small output well is used.

  It is also possible to extend this diagram so that the state diagram includes more than two output wells. In that case, it is possible to use a larger output well because a smaller output well is used, and a further output well, for example, a larger output well. Correspondingly, it is possible to use a larger output well and thus use a smaller output well and a further output well, eg, a smaller output well.

  As described above, at the start-up, it is possible to set by a predetermined method using all the chips of the CCD sensor. The starting state can be fixed and always the same, that is, the output unit A is selected for all CCD sensors, standard CCD sensor pixel binning is selected, and there is no external binning outside the CCD sensor. it can. Thus, imaging can be started at maximum sensitivity at any time with the selected pixel size. External binning outside the CCD sensor, to be performed by addition, can also be defined separately if it is not desired that the AGC function automatically transition to the lowest possible sensitivity. It should also be considered that after the ENABLE signal is activated internally, for example, the FPGA device performs a calibration sequence in which both the A and B directions can be read alternately forward or backward. During this calibration, the AGC function can be automatically disabled, and when selected, the AGC function can only be activated after the calibration sequence.

  As described above, when moving automatically in the direction of low sensitivity, it is possible to use the B output of the CCD sensor chip if allowed in the next column. This can be used when the A output is used, for example when n A / D conversions are above 75% level. This review can be performed individually for all four or eight chips. The number n can be selected within the range of 1-16. The initial value can be considered as 1. The actual number to be used depends on the maximum number of defective stages producing an excessive signal in a single chip.

  If possible or acceptable, in the next column, if the A / D conversion of the B output of any one of the 1 to 16 CCD sensors still exceeds 75%, the procedure is Small register-oriented binning can be used within the entire sensor. At the same time, possible chip-specific changes from output B to output A can be implemented, which allows for a possible increase in sensitivity. In the change from the output unit A to the output unit B, the decrease in sensitivity can be invalidated. In this situation, a simultaneous decrease in AB sensitivity can be avoided if changed to external binning at the same time. If this is not the case, the signal at these outputs may drop to a quarter instead of a half.

  When automatically moved in the direction of higher sensitivity, in the next column, if the maximum possible binning is not already used, the maximum m A / D conversions of the chip output using B output will be 25%. If so, it is possible to use large register-oriented internal binning in the CCD sensor. The number m can be selected in the range of 1-16, and the initial value can be considered to be the value 1. The actual number to be used can depend, for example, on how many defective and saturated stages producing an excessive signal are in the same CCD chip.

  In this case, a change specific to the chip from the output unit B to the output unit A that can be performed can invalidate the increase in sensitivity, and a change from the output unit A to the output unit B effectively reduces the sensitivity. can do. In this situation, the simultaneous decrease in AB sensitivity can be automatically disabled if changed to a smaller external binning at the same time. Otherwise, the signal at these outputs is quadrupled rather than doubled.

  If the A / D conversion of the output of any chip does not exceed 25%, the A output of that chip can be used in the next column when the B output is digitized.

  When a Ceph method is used for a CCD sensor head comprising two CCD sensor packages, a corresponding procedure can be followed. The FPGA device of the CCD sensor (DIMAX2) can control the reading directions of the registers of a total of eight separated chips separately, and can collectively control the vertical binning of all the chips.

  Although it is possible to prepare vertical binning made in different sizes for various chips of the CCD sensor, vertical binning involves more complex both in the required hardware and software.

  When the gain is changed as described above, the system noise and X-ray quantum noise included in the signal are different in magnitude at different output units (output unit A / output unit B) and / or by AD binning. May be. Noise can be reduced when binning is performed using an A / D converter. If necessary, this can be considered in software, where noise can be artificially added over the area where it has been reduced by the binning technique.

For some pixels, the dark current can be reduced by a fraction by binning techniques. This can be accomplished by software, for example mathematically. If necessary, dark current calibration and gain calibration can be performed on both the A and B outputs. The FPGA device allows measurement of both output signals.
However, it should be noted that the automatic gain control function is not useful for small binning sizes (2 × 2 or 1 × 1).

  FIG. 4 shows a table showing typical charges processing the capacitance of the CCD sensor used. In the table, column 4-2 indicates the capacity, and column 4-4 indicates the number of electrons. From this table, when the capacity of one pixel (33 μm × 33 μm) is 1 million electrons, the capacity of the read register is 3 million electrons, the capacity of the output amplifier A is 2.4 million electrons, and the capacity of the output amplifier B Is found to be 4.8 million electrons. The guaranteed minimum capacity is about 20% lower.

  FIG. 5 shows as an example the charge capacity distribution of a unit capable of transferring electronic charges. Block 5-2 shows four pixels in an image area with a typical saturation of approximately 1 million charges and a minimum of 800,000 charges. The saturation value of each pixel is about 0.8 to 1 Me (million electrons).

  Each pixel in the image area may be coupled to a pixel in the addition register. Block 5-4 shows four adder register pixels having a typical saturation value of about 3 million charges and a minimum value of about 2.4 million charges. Therefore, the saturation value of each pixel is about 2.4 to 3 million charges.

  Each pixel in the summing register can be coupled in turn to a readout register. Block 5-6 shows the typical saturation and minimum values for the four read registers, 3 million charges and 2.4 million charges, respectively. Blocks 5-8 show typical saturation and minimum values for output well B, which are about 4.8 million charges and about 4 million charges, respectively. The output signal 5-9 of output well B is typically about 3 volts and at least about 2 volts. Block 2-10 similarly exhibits a typical saturation value for output well A, approximately 2.4 million charges, with a minimum value for this charge amount of 2 million charges. The output signal 2-11 of output well A is typically about 3 volts, and at least about 2 volts. In FIG. 2, the basic sensitivity is about 60 mV / mR with 3 × 3 binning. The pixel size is about 99 micrometers.

  From the example of FIG. 5, it is possible to draw the situation in the horizontal direction. In this case, four horizontal pixels can be binned from the image area with 4 × 4 binning, and the image area has 75% fullness (3000000/4 = 750,000) without overflow in the readout register. ). With a binning size of 3 × 3 or less, the pixels in the image area can be freely binned into it without overflow in the readout register.

  However, it should be noted that the output well must be designed to be small enough to avoid loss of sensitivity of the CCD device. In that case, the output voltages 5-9, 5-11 are suitable for A / D conversion and are therefore sufficient in terms of both signal-to-noise ratio and resolution. This can be limited even when different volumes of output wells are used.

  In the vertical or read direction, the total signal level for 4 × 4 binning is approximately 4 × 4 × 1 Me = 16 Me (million electrons). This is about 6.6 times the capacity of the output well A and about 3.3 times the capacity of the output well B. Thus, in this binning, the maximum average charge to be processed for the total capacity of a pixel of eg 33 μm before the output well is saturated is about 15% of the value obtained when the A output is used. , About 30% of the value obtained when the B output is used.

  When 3 × 3 binning is used, the total signal level is approximately 3 × 3 × 1Me = 9Me. This is about 3.75 times the capacity of the output well A and about 1.875 times the capacity of the output well B. Thus, in 3 × 3 binning, the maximum average charge to be processed for the total capacity of, for example, a 33 μm pixel before the output well saturates is about 26.6% when the A output is used. , About 13.3% when the B output is used.

  When 2 × 2 binning is used, the total signal level is approximately 2 × 2 × 1Me = 4Me. This is about 1.66 times the capacity of output well A. However, the output well B is large enough to hold this entire 4Me capacity. Thus, in this binning, before the output well is saturated, the maximum average charge to be processed for the total capacity of, for example, 33 μm pixels is about 60% when the A output is used, and the B output is About 100% when used.

  When binning is not performed, the total signal level is about 1 Me, ie the same as the pixel level. In this case, both the internal register and the output well can process the signal without the risk of saturation.

  From FIG. 5, the insensitive B output can process a signal coming from an image area with 4 × 4 binning without saturation if the signal exceeds approximately 30% of the physical pixel charge storage capacity. I understand that I can't. However, this problem can be solved by applying the present invention and its preferred embodiments.

  Thus, according to the present invention and its preferred embodiments, the sensitivity and thus the dynamics can be increased by several different methods. Dynamics can be increased, for example, by simply changing the binning. Binning can be changed by moving to higher or lower binning levels. The binning can be changed several times and can be changed from the outside, for example, outside the CCD sensor.

  Instead of changing the binning, it is possible to use a large output well. That is, instead of using the A output, it is possible to use the B output having a larger capacity. It is also possible to use other output wells, for example larger output wells.

  As an additional option to increase dynamics, it is possible to first use a larger volume output well and then change the binning further, or change the binning first and then the larger volume It is also possible to use these output wells.

  When the sensitivity or dynamics of the device is to be changed, this can be done by changing the binning at least partially in response to the control signal. The control signal can be defined, for example, prior to changing the binning. The control signal can also be based on a direct signal or an indirect signal that can depend, for example, on the amount of light seen by the CCD sensor. Alternatively, the control signal can be based on a signal read from the CCD sensor. The control signal can also be based on some other signal.

  The dynamics of the device can be changed during imaging or before and after imaging. Binning can be changed, for example, between the image area and the shift register and / or between the shift register and the output register.

  Furthermore, the apparatus can include means for normalizing the image signal. In normalization, an image can be processed so that it does not change, for example in grayscale, so that it will later look like a visible picture. Normalization means may include digital addition of signals generated by pixels physically adjacent to each other on the sensor, and / or correction of dark current and / or gain that may depend on binning. Such addition and / or correction may be performed partly or completely, for example electrically and / or by software.

  The object of the present invention and its preferred embodiments is therefore to increase the dynamic range of the CCD sensor, for example by external means that make it as wide as possible. In accordance with the present invention and its preferred embodiments, the amplifier can be optimized for noise and speed when the charge well capacity is different, eg, for real-time TDI readout of X-ray images. This procedure allows the dynamic range processed by the CCD sensor to be doubled or quadrupled, for example, when larger binning sizes are used, for example 2 × 2 binning.

  Furthermore, in the device, the signals of both output amplifiers can be digitized simultaneously or alternately. The choice of which of the two output amplifier signals is to be used depends on the signal itself. In a suitable device, in a CCD sensor that can be composed of a plurality of CCD sensor chips, the signal of each CCD sensor chip is processed separately and further which of the amplifiers is to be used for each chip can be determined. it can. This determination can be made on a column-by-column basis, so the signal level can be dynamically monitored and maximized over the entire image area. The automatic selection of the register reading direction and thus the selection of the amplifier can be performed separately, for example by controlling the FPGA device. Information about which amplifier is being used can be sent separately for each row in the form of image data and separately for each CCD, so the calibration program can do this by processing the image data. Can be considered. Image data can be shifted at 16 bits / pixel even in the case of 14-bit conversion.

  For example, if a 14-bit A / D conversion is used, it can easily be virtually increased to a 15-bit conversion, again using the same A / D conversion (capacity ratio of the output amplifier well is 2: 1) If so, the dynamics doubled).

  Therefore, in the CCD sensor camera, it is possible to select whether the output unit A or the output unit B should be used. This selection can be made, for example, manually or automatically, for example using an AGC device individually for each of all eight chips. However, both register direction binning and horizontal binning are always the same for all chips. If this procedure is not followed, the image data generated by the computer should contain pixels of different sizes. Even if the camera head of the camera uses a smaller binning size in the CCD sensor, the virtual pixels remain the same size. Lost binning in the sensor can be replaced invisible with AD binning.

  In other words, binning is common to all chips, but the A / B direction can be selected manually or automatically individually using an AGC device for each chip separately. It is also possible to distinguish AD binning in a chip-specific manner.

  In a preferred embodiment, some of the chips can be re-used with a sensitive A output, but the signal is so large that both the B output and external binning outside the CCD device are required. Can be generated by other chips. In other words, if the B output of any one of the chips generates an excessive signal and therefore has to use smaller internal binning, the other chip will have too low the signal in it Can freely return to the A direction. Although the control logic of the A / B output, ie a total of 8 chips for example, may be separated, the FPGA device can have a common binning logic in it.

  In accordance with the present invention and its preferred embodiments, the A / D converter dynamics of the CCD sensor (DIMAX2 device has a discrete level of 14-bit A / D converter = 16384) is expanded, for example 8 times higher. (17 bits = 131072 discrete levels). This enlargement is automatically performed in the CCD sensor head (DIMAX2) and according to the image signal. The dynamics can be doubled when trying to use larger capacity output wells instead of smaller output wells. When 4 × 2 binning is used instead of 4 × 4 binning, and then 4 × 1 binning is used, the dynamics can be further quadrupled. Therefore, by this method, the dynamics can be increased by the above-mentioned amount in total, that is, the dynamics can be increased by 8 times.

  The sensor can send image data to the computer in a pure 17-bit format. Furthermore, it should be noted that the image data can be compressed in a computer to a 12-bit format (in the future to a 16-bit format) as soon as the highest and lowest strengths are known. Regardless, it is preferable to image the subject itself using maximum dynamics. Gamma correction can be performed simultaneously while the image data is converted to a 12-bit format, and thus maximum dynamics can be stored in the form of the final image.

  Pixel binning uses binning where two pixels are binned and sampled in the direction of the register of the CCD sensor, after which another pixel is digitized without binning and the result is added to the previous binned pixel. Can also be performed alternately. This binning approach can be used when the selected original binning in the register direction is approximately three times and needs to move in a less sensitive direction while the AGC device is in operation.

  During this 3x binning, if two pixels binned in the CCD sensor are first summed, then another one CCD device is summed, a symmetrical error will occur when changed to external summing binning. It can happen. However, this situation can also be considered by the software.

  The AGC function depends only on binning in the register direction. Binning in the horizontal or TDI direction is not important at all. Horizontal binning may be different from vertical binning. However, in this case, the generated pixel is not an isosceles size.

  The present invention and its preferred embodiments also provide a means for allowing the CCD sensor to have separate outputs for at least two capacitors.

  The device according to the invention and its preferred embodiments can be integrated on a single CCD chip using one or more microcircuits. For example, a PGA amplifier can be additionally integrated before the CCD of the device. The gains of these amplifiers can be adjusted to 64 levels (for example, 1 time) in the range of 1 to 6 times, for example.

  By applying the present invention and its preferred embodiments and adjusting the gain to an appropriate value for the signal level (Cef / Pan), optimal results can be achieved for both noise and dynamics. In particular, the signal level in the cef image is very low, so extra gain can be utilized to reduce subsequent image processing artifacts and system noise. Furthermore, the device according to the invention and its preferred embodiments still prevents saturation. For example, in the same cranial imaging, it is possible to have a soft tissue region (soft tissue filter) included in the image by software, for example.

  The CCD sensor according to the present invention and its preferred embodiment generates 16-bit image data having very high dynamics in a pixel, and the structure of such image data is shown as an example in FIG. As shown, 2 bytes are required to represent the gray level of the pixel. The first byte that occurs in the data flow contains the lower 8 bits (AD0 to AD7) and the next byte contains the upper 8 bits (AD8 to ADD1). The A / D conversion itself is a 14-bit conversion. This bit count of A / D conversion can be justified by the very low noise of the system itself.

  Thus, the CCD sensor according to the present invention and its preferred embodiments solves the problem of limited dynamic range and slow recovery from saturation. By using 14-bit conversion and keeping the system noise at a low level, an ideal state is achieved in which one step of the A / D converter corresponds to the noise level of the output amplifier of the CCD sensor. The signal-to-noise ratio of the final image is determined by the quantum noise of the X-ray beam. In a normal imaging state, the two most significant bits (ADD1 and ADD0) of the 16-bit pixel value can be zero.

  However, an exception occurs in two states. The function of the automatic gain control according to the AGC of the present invention and the preferred embodiment thereof is performed by binning the CCD sensor pixels by integrally binning pixels with less binning in the register direction when the radiation dose is large. Convert. In situations where they remain the same, successive pixel sample values may be added within the FPGA device. Therefore, the quadruple binning can be changed, for example, to a form of 2 times + 2 times, and in the worst case, a form of 1 time + 1 times + 1 times + 1 times. In this situation, the 16-bit pixel value approaches 0 × FFD when four 14-bit values are added together. However, the AGC device can handle all of this alone. In this summing situation, the amount of dark current that cancels out corresponding to the number of summing operations can be subtracted from the signal.

  It will be apparent to those skilled in the art that the basic concept of the present invention can be implemented in various ways in technology development. Accordingly, the invention and its preferred embodiments are not limited to the examples described above but may vary within the scope of the claims. Within the framework of the inventive concept, the sensitivity can be adjusted in other ways.

FIG. 2 shows an apparatus for increasing dynamics, according to a preferred embodiment. It is a figure which shows the structure of image data. It is a figure which shows as an example the method to perform imaging, and the logic which controls the AGC function of an FPGA apparatus during imaging. 6 is a table showing typical charges for processing the capacitance of a CCD sensor used. It is a figure which shows the charge capacity distribution of all the units which can transfer an electronic charge as an example. It is a figure which shows a 4-chip CCD sensor and its control block.

Claims (46)

A reading device for reading a CCD sensor (1-1), wherein the CCD sensor (1-1)
A detector (1-2) having an active region comprising a pixel receiving charge;
A read register (1-4) functionally connected to the active region;
Means for transferring charge from the active region into the read register (1-4);
Means for transferring charge to the output section (1-4a, 1-4b) of the read register (1-4);
At least one read well (1-6, 1-8) operatively connected to the read register (1-4), and charge to the output section (1-4a, 1-4b) comprising means for transferring into the at least one readout well (1-6, 1-8), and changing the dynamics by at least partially changing the binning of the charge in response to a control signal A reading apparatus, further comprising means for changing.   The apparatus of claim 1 further comprising means for changing binning during imaging.   3. An apparatus according to claim 1, wherein said means changes binning according to a control signal.   4. A device according to claim 1, wherein said means changes binning at least partly according to a control signal between the image area and the shift register.   4. An apparatus according to any one of the preceding claims, wherein the means changes binning at least partially between the shift register and the output register according to a control signal.   4. A device according to claim 1, wherein said means changes binning according to a control signal between said shift register and said output register.   7. A device according to any one of the preceding claims, wherein the control signal is a predefined signal.   8. A device according to claim 1, wherein the control signal is based directly or indirectly on a signal depending on the amount of light seen by the CCD sensor.   The apparatus according to claim 1, wherein the control signal is based on a signal read from the CCD sensor.   Should the means for measuring the signal generated by the charge placed in or functionally connected to the sensor and the binning (1-6, 1-8) be modified? 10. A device according to any one of the preceding claims, comprising selection means for determining at least in part based on the measured signal.   The apparatus according to any one of claims 1 to 3, further comprising means for normalizing the image signal.   12. The apparatus of claim 11, wherein the normalization means includes digital addition of signals generated by pixels located physically adjacent to each other on the sensor.   13. Apparatus according to claim 11 or 12, characterized in that the normalization means comprise dark current and / or gain corrections dependent on the binning.   14. Device according to claim 12 or 13, characterized in that the addition and / or the correction is carried out partially or completely electrically.   14. Apparatus according to claim 12 or 13, characterized in that the addition and / or the correction is performed partly or completely by software.   At least two read wells (1-6, 1-8) having different capacitances arranged in connection with the read register (1-4), ie first and second read wells, arranged in the sensor Or means operatively connected to the sensor for measuring the signal generated by the charge and which of the readout wells (1-6, 1-8) is the CCD sensor (1-1) 16. A selection means for determining at least in part on the basis of the measured signal whether it should be used to read out the charge detected by The device described in 1.   The means for selecting is adapted to determine whether the readout wells (1-6, 1-8) to be used are to be changed during readout of the sensor. 16. The sensor device according to 16.   18. Device according to any one of the preceding claims, characterized in that the read well (1-6, 1-8) is an amplifier.   19. The read well (1-6, 1-8) is located at either end of the read register (1-4) or at one end of the read register. apparatus.   20. Device according to any one of claims 16 to 19, characterized in that the capacity of the second read well (1-6) is equal to approximately twice the capacity of the first read well (1-8). .   The detector (1-2) and the read register (1-4) are arranged between and functionally connected to the charge before the transfer of the charge to the read register (1-4). 21. The apparatus according to any one of claims 1 to 20, further comprising a register for adding.   22. A device according to any one of claims 11 to 21, further comprising means for processing pixel charges prior to transfer to their readout registers (1-4).   23. A means according to any one of the preceding claims, comprising means adapted to determine the binning to be used and / or the output well to be used based on at least one clock pulse. The device described.   24. The apparatus of claim 23, further comprising means for changing the clock pulse based at least in part on the signal coming from the CCD sensor.   Selection means adapted to select the readout wells (1-6, 1-8) to be read by the signal coming from the CCD sensor (1-1), so as to perform A / D conversion of the signal Means for performing A / D conversion of the signals of the at least two readout wells, the signal coming from the CCD sensor (1-1) by which the readout well (1- 25. Device according to any one of claims 16 to 24, comprising selection means adapted to select 6, 1-8).   Check whether the A / D conversion exceeds a predefined first threshold (3-4), and if the A / D conversion exceeds the predefined first threshold, read the large capacity It is further checked whether the well (1-6, 1-8) is used (3-14), and if it is not used, the small vertical read well (1-6) is read in the next vertical line read. 26. The apparatus of claim 25, further comprising (3-6) means adapted to use a large capacity read well (1-6, 1-8) instead of 1-8).   When the A / D conversion is above the predefined first threshold (3-4) and the large read well (1-6, 1-8) is used, It is checked whether the external maximum binning in the register direction outside the sensor has already been reached (3-18), and if not, a larger register direction external binning outside the sensor is used (3 27. A method according to any one of claims 25 or 26, comprising means for reading the next vertical line.   The system is adapted (3-22) to use the small read wells (1-6, 1-8) when the A / D conversion value is below a second predefined threshold. 28. The method of claim 27, further comprising:   If the A / D conversion does not exceed the first predefined threshold, the system checks whether the A / D conversion value is below the second predefined threshold (3-6). ), If the A / D conversion value is below the second predefined threshold, then further check if external binning in the minimum register direction has been reached, otherwise use smaller external binning 29. The method of claim 28, further comprising: (3-10) means for reading a next vertical line.   If the system has reached external binning in the direction of the minimum register, use the small read wells (1-6, 1-8) (3-12) to set the next vertical line 30. A method according to any one of claims 16 to 29, comprising means for reading. A method for enlarging the dynamics of the CCD sensor (1-1),
Receiving a charge in an active region including a pixel;
Reading the charge of the first vertical line of the pixels in the active region from the active region into a read register (1-4) (3-2);
Transferring the charge to the output section (1-4a, 1-4b) of the read register (1-4); and transferring the charge to the output section (1-4a, 1 -4b) to the read wells (1-6, 1-8), and (1-8) the dynamics change the binning of the charges at least partially in response to the control signal A method characterized by being modified.   32. The method of claim 31, wherein the charge binning is changed during imaging.   The apparatus according to claim 31 or 32, wherein the binning is changed according to a control signal.   The apparatus comprises at least two read wells (1-6, 1-8) having different capacitances arranged in connection with the read register (1-4), ie first and second read wells, The signal generated by the charge is measured, and which of the read wells (1-6, 1-8) should be used to read the charge detected by the CCD sensor (1-1) 34. A method according to any one of claims 31 to 33, wherein the method is determined at least in part based on the measured signal.   The signal coming from the CCD sensor (1-1) is selected for the read wells (1-6, 1-8) to be read out, and A / D conversion is performed on the signals, ie the signals of at least two read wells. Device according to claim 34, characterized in that the reading wells (1-6, 1-8) are selected, by which the signals coming from the CCD sensor (1-1) are to be read out.   Checked to determine if the A / D conversion exceeds a predefined first threshold (3-4), and if the A / D conversion exceeds the predefined first threshold, then It is further checked (3-14) to determine if the capacitive read wells (1-6, 1-8) are being used, and if they are not being used, the next vertical line read will produce a small volume. 36. The high-capacity read well (1-6, 1-8) is used instead of the read well (1-6, 1-8) (3-6) according to claim 35. apparatus.   If the signal level of the signal read from the CCD sensor (1-1) is measured and the signal level exceeds a predefined threshold, reading of the charge from the sensor will cause the charge in the read well to be read out. If the signal level is below the pre-defined threshold and the number of pixels to be transferred into the read well is reduced before the is read out, information reading is performed in the read well. 37. A method according to any one of claims 31 to 36, wherein the number of pixels to be transferred into the readout well is adjusted before charge is read out.   38. The method of claim 37, wherein a predefined threshold is determined in relation to a saturation level of the read well.   If the signal level of the read signal is measured using a sensor comprising at least two different capacity read wells, and a small output well is saturated during the measurement, a large capacity read well is used. The method according to any one of claims 37 and 38, characterized in that:   40. The method of claim 39, wherein external binning of charges external to the sensor increases when either one of the read wells is saturated.   When the A / D conversion exceeds the predefined first threshold (3-4) and the large-capacity readout well (1-6, 1-8) is used, Check if the maximum external binning in the register direction has already been reached (3-18), if not, use the external binning in the large register direction outside the sensor (3-20) 37. A method according to claim 35 or 36, wherein a vertical line is read.   When the A / D conversion is below a second predefined threshold, the small read well (1-6, 1-8) is used (3-22). Item 42. The method according to Item 41.   If the A / D conversion does not exceed the predefined first threshold, a check is made to determine if the A / D conversion value is below the second predefined threshold (3-6). ), If the A / D conversion value is below the second predefined threshold, it is further checked to determine if external binning in the minimum register direction has been reached (3-8); 43. The method of claim 42, wherein (3-10) the next vertical line is read using small external binning.   When the external binning in the minimum register direction is reached, the next vertical line is read by using the small read wells (1-6, 1-8) (3-12). The method according to any one of claims 31 to 43.   45. A method according to any one of claims 26 to 44, wherein the first predefined threshold is 75%.   46. A method according to any one of claims 26 to 45, wherein the second predefined threshold is 25%.

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