JP5629568B2 - Imaging device and pixel addition method thereof - Google Patents

Imaging device and pixel addition method thereof Download PDF

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JP5629568B2
JP5629568B2 JP2010280985A JP2010280985A JP5629568B2 JP 5629568 B2 JP5629568 B2 JP 5629568B2 JP 2010280985 A JP2010280985 A JP 2010280985A JP 2010280985 A JP2010280985 A JP 2010280985A JP 5629568 B2 JP5629568 B2 JP 5629568B2
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博文 渡邊
博文 渡邊
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本発明は、撮像装置及びその画素加算方法に関する。   The present invention relates to an imaging apparatus and a pixel addition method thereof.

CMOS型イメージセンサ等の、信号読出回路としてMOSトランジスタ回路を用いた固体撮像素子は、近年では多画素化が進展し、1000万画素以上を搭載するのが普通になっている。このため、1画素1画素が微細化され、個々の画素(光電変換素子)の飽和電荷量が小さくなった関係で、撮像画像のダイナミックレンジが狭くなり、また、明るい画像を撮像するのが困難になってきている。   In recent years, a solid-state imaging device using a MOS transistor circuit as a signal readout circuit, such as a CMOS type image sensor, has been increased in number of pixels, and it is common to mount 10 million pixels or more. For this reason, each pixel (pixel) is miniaturized and the saturation charge amount of each pixel (photoelectric conversion element) is reduced, so that the dynamic range of the captured image is narrowed and it is difficult to capture a bright image. It is becoming.

このため、高感度撮影や広ダイナミックレンジ撮影等を行う場合、複数画素の検出信号を加算する画素加算が行われる。この画素加算には、例えば、下記の特許文献1記載の様に、撮像素子から撮像画像信号を読み出した後の信号処理で画素加算する第1の方法と、下記の特許文献2に記載されている様に、受光量に応じて各画素が検出した信号電荷をそのまま撮像素子内部で加算(信号電荷の電荷混合)し、加算した信号電荷量に応じた信号を撮像素子外部に読み出す第2の方法とがある。   For this reason, when performing high-sensitivity imaging, wide dynamic range imaging, or the like, pixel addition for adding detection signals of a plurality of pixels is performed. In this pixel addition, for example, as described in Patent Document 1 below, a first method of adding pixels by signal processing after reading a captured image signal from an image sensor, and Patent Document 2 described below. As shown, the signal charge detected by each pixel in accordance with the amount of received light is directly added inside the image sensor (mixing of signal charges), and a signal corresponding to the added signal charge amount is read out to the outside of the image sensor. There is a method.

特開2007―124137号公報JP 2007-124137 A 特開2002―199284号公報JP 2002-199284 A

画素加算を行う上記の2つの方法のうち、撮像素子から撮像画像信号を読み出した後に信号処理で加算する第1の方法は、光ショットノイズや暗時ノイズが共に加算により増加すると共に加算処理に時間が必要になるという短所がある一方、画素加算した結果が飽和してしまうことが無いという長所がある。   Of the above two methods for performing pixel addition, the first method of adding a signal processing after reading a picked-up image signal from the image sensor increases both the light shot noise and dark noise due to the addition and adds to the addition processing. While there is a disadvantage that time is required, there is an advantage that the result of pixel addition is not saturated.

これに対し、撮像素子内部で信号電荷の加算を行う第2の方法は、加算を行う場所がフローティングディフュージョン(以下、FDという。)トランジスタのため、FDトランジスタの飽和電荷量の制限を受けてしまい、また、光ショットノイズが加算で増加してしまうという短所がある反面、暗時ノイズは増加せず、更に、加算処理に時間がかからないため高速に加算した信号を読み出すことができるという長所がある。   On the other hand, the second method for adding signal charges inside the image sensor is limited by the saturation charge amount of the FD transistor because the place where the addition is performed is a floating diffusion (hereinafter referred to as FD) transistor. In addition, there is a disadvantage that the light shot noise increases due to addition, but there is an advantage that the added signal can be read out at high speed because the dark noise does not increase and the addition processing does not take time. .

この様に、2つの加算方法には夫々一長一短があり、これ等を使い分けて互いの短所を補うことにすれば、撮像装置の使い勝手を優れたものとすることが期待され、また、撮影シーンに応じた高品質な被写体画像を得ることが期待される。しかし従来は、この2つの加算方法をどの様な撮像素子に適用し、どの様に使い分けすれば良いかについて、あまり考察されていなかった。   In this way, the two addition methods have their merits and demerits, and if these are used separately to compensate for each other's disadvantages, it is expected to improve the usability of the imaging device, It is expected to obtain a high-quality subject image according to the response. Conventionally, however, little consideration has been given to what kind of image sensor the two addition methods are applied to and how to use them properly.

本発明の目的は、撮像素子内部での画素加算と撮像素子から読み出した後の信号の画素加算とを使い分ける撮像装置及びその画素加算方法を提供することにある。   An object of the present invention is to provide an image pickup apparatus and a pixel addition method for selectively using pixel addition inside the image pickup device and pixel addition of a signal after reading from the image pickup device.

本発明の撮像装置及びその画素加算方法は、複数の光電変換素子が半導体基板上に二次元アレイ状に配列形成される共に、隣接する2つの前記光電変換素子をペア画素とし該ペア画素を1単位としてカラーフィルタがベイヤ配列され、該ペア画素毎に前記半導体基板にMOSトランジスタ回路でなる信号読出回路が形成される撮像素子と、前記撮像素子に付設され該撮像素子の前記信号読出回路から出力される撮像画像信号を処理する信号処理回路とを備える撮像装置及びその画素加算方法であって、
前記ペア画素を構成する2つの前記光電変換素子の各検出電荷に応じた撮像画像信号を個別に前記信号読出回路で読み出し前記信号処理回路で信号加算させる第1画素加算駆動モードと、前記ペア画素の2つの前記光電変換素子の各検出電荷を混合し、該混合した電荷量に応じた撮像画像信号を前記信号読出回路で読み出す第2画素加算駆動モードとを、前記撮像素子で被写体画像を撮影するときの撮影状態に応じて切り換え、前記光電変換素子が形成された前記撮像素子の受光面を複数ブロックに領域分割し、各分割ブロック毎に前記第1画素加算駆動モードと前記第2画素加算駆動モードとを切り換え、
記第1画素加算駆動モードと前記第2画素加算駆動モードとが混在した状態で同一行の前記ペア画素から前記信号読出回路が前記撮像画像信号を読み出すとき、前記第2画素加算駆動モードによる前記撮像素子の出力タイミングのうち、前記第1画素加算駆動モードで出力される前記ペア画素のうちの最初に読み出される撮像画像信号の出力タイミングと同じ位置にダミー信号を出力させ、該ダミー信号と前記混合した電荷量に応じた撮像画像信号とを前記信号処理回路で信号加算し、該信号処理回路による信号処理を、前記第1画素加算駆動モードにより前記撮像素子から出力された信号の信号加算処理と同じ処理としたことを特徴とする。
According to the imaging apparatus and the pixel addition method of the present invention, a plurality of photoelectric conversion elements are formed in a two-dimensional array on a semiconductor substrate, and two adjacent photoelectric conversion elements are used as a pair pixel. An image sensor in which a color filter is Bayer arrayed as a unit and a signal readout circuit composed of a MOS transistor circuit is formed on the semiconductor substrate for each paired pixel, and an output from the signal readout circuit of the image sensor attached to the image sensor An image pickup apparatus including a signal processing circuit for processing a picked-up image signal and a pixel addition method thereof,
A first pixel addition drive mode in which captured image signals corresponding to the detected charges of the two photoelectric conversion elements constituting the pair pixel are individually read out by the signal readout circuit and added by the signal processing circuit; and the pair pixel The detection charges of the two photoelectric conversion elements are mixed, and a second pixel addition drive mode in which a captured image signal corresponding to the mixed charge amount is read by the signal readout circuit, and a subject image is captured by the imaging element Switching according to the shooting state, and dividing the light receiving surface of the imaging element on which the photoelectric conversion element is formed into a plurality of blocks, and the first pixel addition driving mode and the second pixel addition for each divided block. Switch between drive modes,
When the signal readout circuit reads the captured image signal from the paired pixels in the same row in a state where the first pixel addition drive mode and the second pixel addition drive mode coexist, the second pixel addition drive mode Among the output timings of the image sensor, a dummy signal is output at the same position as the output timing of the captured image signal read out first among the pair of pixels output in the first pixel addition drive mode, and the dummy signal and the The captured image signal corresponding to the mixed charge amount is signal-added by the signal processing circuit, and the signal processing by the signal processing circuit is added to the signal output from the image sensor in the first pixel addition drive mode. It is characterized by having the same processing as .

本発明によれば、2つの画素加算方法を撮影状態によって適切に選択して切り換えることができるため、被写体の高品質,広ダイナミックレンジの画像を撮影することが可能となる。   According to the present invention, since the two pixel addition methods can be appropriately selected and switched depending on the shooting state, it is possible to take a high-quality, wide dynamic range image of the subject.

本発明の一実施形態に係る撮像装置の機能ブロック構成図である。It is a functional block block diagram of the imaging device which concerns on one Embodiment of this invention. 図1に示す撮像素子の表面模式図である。It is a surface schematic diagram of the image sensor shown in FIG. 図2に示す撮像素子のカラーフィルタ配列を示す図である。It is a figure which shows the color filter arrangement | sequence of the image pick-up element shown in FIG. 図3の撮像素子のうち主画素2画素と副画素2画素を取り出した図である。FIG. 4 is a diagram in which two main pixels and two sub-pixels are extracted from the image sensor of FIG. 3. 図4に示す計4画素の信号読出回路の回路図である。FIG. 5 is a circuit diagram of a signal readout circuit having a total of four pixels shown in FIG. 4. 図5に示す信号読出回路の内部回路図である。FIG. 6 is an internal circuit diagram of the signal readout circuit shown in FIG. 5. 電荷混合による画素加算のシーケンス図である。It is a sequence diagram of pixel addition by charge mixing. 信号加算による画素加算のシーケンス図である。It is a sequence diagram of pixel addition by signal addition. 本発明の第1実施形態による画素加算方法選択処理手順を示すフローチャートである。It is a flowchart which shows the pixel addition method selection process sequence by 1st Embodiment of this invention. 図9で用いる閾値αの説明図である。It is explanatory drawing of the threshold value (alpha) used in FIG. 本発明の第2実施形態による画素加算方法選択処理手順を示すフローチャートである。It is a flowchart which shows the pixel addition method selection process sequence by 2nd Embodiment of this invention. 図11で用いる閾値βの説明図である。It is explanatory drawing of the threshold value (beta) used in FIG. 撮像素子受光面を複数ブロックに分ける実施形態の説明図である。It is explanatory drawing of embodiment which divides an image pick-up element light-receiving surface into several blocks. 図13で説明する実施形態の信号読出シーケンスを示す図である。It is a figure which shows the signal read-out sequence of embodiment described in FIG. 図13で説明する実施形態で用いるマスク信号発生回路の説明図である。It is explanatory drawing of the mask signal generation circuit used by embodiment described in FIG. 撮像素子受光面を複数ブロック分けブロック毎に画素加算方法を使い分ける処理手順を示すフローチャートである。It is a flowchart which shows the process sequence which uses an image pick-up element light-receiving surface separately for several blocks and uses a pixel addition method for every block.

以下、本発明の一実施形態について、図面を参照して説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図1は、本発明の一実施形態に係るデジタルカメラ(撮像装置)の機能ブロック図である。本実施形態のデジタルカメラ10は、被写体の静止画像或いは動画像を撮影しカメラ10内で撮像画像信号をデジタル処理する機能を有し、望遠レンズ及びフォーカスレンズを備える撮影レンズ20と、撮影レンズ20の背部に置かれその結像面に配置された固体撮像素子21と、固体撮像素子21の各画素から出力されるアナログの画像データを自動利得調整(AGC)や相関二重サンプリング処理等のアナログ処理するアナログ信号処理部22と、アナログ信号処理部22から出力されるアナログ画像データをデジタル画像データに変換するアナログデジタル変換部(A/D)23と、後述のシステム制御部(CPU)29からの指示によってA/D23,アナログ信号処理部22,固体撮像素子21,撮影レンズ20の駆動制御を行う駆動部24と、CPU29からの指示によって発光するフラッシュ25とを備える。   FIG. 1 is a functional block diagram of a digital camera (imaging device) according to an embodiment of the present invention. The digital camera 10 of the present embodiment has a function of capturing a still image or a moving image of a subject and digitally processing a captured image signal in the camera 10, and includes a photographic lens 20 including a telephoto lens and a focus lens, and a photographic lens 20. The analog image data output from each pixel of the solid-state image sensor 21 and the solid-state image sensor 21 placed on the imaging surface of the solid-state image sensor 21 and the analog image data such as automatic gain adjustment (AGC) and correlated double sampling processing. From an analog signal processing unit 22 to be processed, an analog / digital conversion unit (A / D) 23 that converts analog image data output from the analog signal processing unit 22 into digital image data, and a system control unit (CPU) 29 described later The A / D 23, the analog signal processing unit 22, the solid-state imaging device 21, and the photographic lens 20 are driven and controlled by It includes a moving section 24, a flash 25 that emits light in response to an instruction from the CPU 29.

駆動部24は、後述する画素加算方法選択処理手順を実行するCPU29からの指示を受けて、該当する画素加算方法に基づき撮像素子21からの信号読出駆動を実行する。   In response to an instruction from the CPU 29 that executes a pixel addition method selection processing procedure to be described later, the drive unit 24 performs signal readout drive from the image sensor 21 based on the corresponding pixel addition method.

本実施形態のデジタルカメラ10は更に、A/D23から出力されるデジタル画像データを取り込み画素加算処理,補間処理,ホワイトバランス補正,RGB/YC変換処理等を行うデジタル信号処理部26と、画像データをJPEG形式などの画像データに圧縮したり逆に伸長したりする圧縮/伸長処理部27と、メニューなどを表示したりスルー画像や撮像画像を表示する表示部28と、デジタルカメラ全体を統括制御するシステム制御部(CPU)29と、フレームメモリ等の内部メモリ30と、JPEG画像データ等を格納する記録メディア32との間のインタフェース処理を行うメディアインタフェース(I/F)部31と、これらを相互に接続するバス40とを備え、また、システム制御部29には、ユーザからの指示入力を行う操作部33が接続されている。   The digital camera 10 of the present embodiment further includes a digital signal processing unit 26 that takes in digital image data output from the A / D 23 and performs pixel addition processing, interpolation processing, white balance correction, RGB / YC conversion processing, and the like. A compression / decompression processing unit 27 that compresses image data in JPEG format or the like, a display unit 28 that displays menus and displays through images and captured images, and overall control of the entire digital camera A system control unit (CPU) 29, an internal memory 30 such as a frame memory, and a media interface (I / F) unit 31 that performs interface processing between a recording medium 32 that stores JPEG image data and the like. In addition, the system control unit 29 receives instructions from the user. Operation unit 33 are connected.

固体撮像素子21は、本実施形態では半導体基板上に形成したMOSトランジスタ回路を信号読出回路としたMOS型イメージセンサ、例えばCMOS型イメージセンサであり、固体撮像素子21の出力信号をアナログ信号処理部(AFE:アナログフロントエンド)22で処理するが、このAFE部分(相関二重サンプリング処理やクランプ処理を行う回路や利得制御を行う信号増幅回路等)は半導体チップ上に周辺回路として設けられるのが普通である。また、固体撮像素子21の半導体チップ上には、その他にも、水平走査回路や垂直走査回路等が周辺回路として受光部周りに形成され、図1のA/D変換部23も形成される場合がある。   In the present embodiment, the solid-state image sensor 21 is a MOS image sensor, for example, a CMOS image sensor, in which a MOS transistor circuit formed on a semiconductor substrate is a signal readout circuit. The output signal of the solid-state image sensor 21 is an analog signal processing unit. (AFE: analog front end) 22 is processed, but this AFE part (a circuit that performs correlated double sampling processing or clamping processing, a signal amplification circuit that performs gain control, etc.) is provided as a peripheral circuit on the semiconductor chip. It is normal. In addition, on the semiconductor chip of the solid-state imaging device 21, in addition, a horizontal scanning circuit, a vertical scanning circuit, and the like are formed as peripheral circuits around the light receiving unit, and the A / D conversion unit 23 of FIG. 1 is also formed. There is.

図2は、図1に示す固体撮像素子21の表面模式図である。この固体撮像素子21は、半導体基板41の受光面42上に、二次元マトリクス状に多数の画素(光電変換素子:フォトダイオード)43が形成されている。本実施形態の固体撮像素子21は、奇数行の画素43に対して偶数行の画素43が1/2画素ピッチづつずれるように形成された、所謂、ハニカム画素配列となっている。半導体基板41の下辺部には水平走査回路44が設けられており、半導体基板41の左辺部には垂直走査回路45が設けられている。   FIG. 2 is a schematic diagram of the surface of the solid-state imaging device 21 shown in FIG. In the solid-state imaging device 21, a large number of pixels (photoelectric conversion elements: photodiodes) 43 are formed on a light receiving surface 42 of a semiconductor substrate 41 in a two-dimensional matrix. The solid-state imaging device 21 of the present embodiment has a so-called honeycomb pixel array in which the even-numbered pixels 43 are shifted from the odd-numbered pixels 43 by 1/2 pixel pitch. A horizontal scanning circuit 44 is provided on the lower side of the semiconductor substrate 41, and a vertical scanning circuit 45 is provided on the left side of the semiconductor substrate 41.

各画素43には、当該画素43が受光量に応じて蓄積した信号電荷量に応じた信号を読み出す信号読出回路(MOSトランジスタ回路)が設けられている。各画素43の上にはカラーフィルタが積層されており、図2では、赤色フィルタを「R」「r」、緑色フィルタを「G」「g」、青色フィルタを「B」「b」で示している。大文字RGBと小文字rgbの違いについては図3で説明する。   Each pixel 43 is provided with a signal readout circuit (MOS transistor circuit) that reads a signal corresponding to the amount of signal charge accumulated by the pixel 43 according to the amount of received light. A color filter is stacked on each pixel 43. In FIG. 2, the red filter is indicated by “R” and “r”, the green filter is indicated by “G” and “g”, and the blue filter is indicated by “B” and “b”. ing. The difference between uppercase RGB and lowercase rgb will be described with reference to FIG.

本実施形態では、画素43がいわゆるハニカム配列されている関係で、垂直走査回路45に接続される水平方向の配線46(図2では1本のみ図示)は、受光面42上の各画素43を避ける様に水平方向に蛇行して設けられ、同様に、水平走査回路44に接続される垂直方向の配線47(図2では1本のみ図示)も、垂直方向に蛇行して設けられる。   In the present embodiment, since the pixels 43 are arranged in a so-called honeycomb arrangement, the horizontal wiring 46 (only one is shown in FIG. 2) connected to the vertical scanning circuit 45 connects each pixel 43 on the light receiving surface 42. The vertical wiring 47 (only one is shown in FIG. 2) connected to the horizontal scanning circuit 44 is also provided meandering in the vertical direction.

図3は、固体撮像素子21のハニカム画素配列された各画素に積層されるカラーフィルタの色を示す図である。各画素の上には、3原色のカラーフィルタ、R=r=赤、G=g=緑、B=b=青が積層されている。   FIG. 3 is a diagram illustrating the color of the color filter stacked on each pixel in the honeycomb image array of the solid-state image sensor 21. On each pixel, three primary color filters, R = r = red, G = g = green, and B = b = blue are stacked.

奇数行の画素行だけみると各画素は正方格子配列され、その上に、カラーフィルタRGBがベイヤ配列されている。偶数行の画素行だけみても各画素は正方格子配列され、その上に、カラーフィルタrgbがベイヤ配列されている。この結果、斜めに隣接する2画素に同色のフィルタ(Rr)(Gg)(Bb)が並ぶことになる。   When only the odd-numbered pixel rows are viewed, the pixels are arranged in a square lattice, and the color filters RGB are arranged in a Bayer arrangement thereon. Even if only the even number of pixel rows are viewed, each pixel is arranged in a square lattice, and a color filter rgb is arranged thereon in a Bayer arrangement. As a result, filters (Rr) (Gg) (Bb) of the same color are arranged in two pixels adjacent obliquely.

大文字のRGBで示すカラーフィルタを搭載した画素が第1群画素を構成し、小文字のrgbで示すカラーフィルタを搭載した画素が第2群画素を構成する。Rとr、Gとg、Bとbは全く同じカラーフィルタであるが、第1群画素だけで撮影した被写体画像と、第2群画素だけで撮影した被写体画像とを区別するために、大文字と小文字で区別している。   Pixels equipped with uppercase RGB color filters constitute the first group pixels, and pixels equipped with lowercase rgb color filters constitute the second group pixels. R and r, G and g, and B and b are exactly the same color filters, but in order to distinguish between a subject image captured with only the first group pixel and a subject image captured with only the second group pixel, capital letters are used. And lowercase letters.

本実施形態では、斜めに隣接する同色フィルタ(Rr)(Gg)(Bb)の2画素がペア画素を構成し、このペア画素の各検出信号を、固体撮像素子21から個別に読み出したあと画素加算したり、固体撮像素子21内部で画素加算してから読み出す構成としている。   In this embodiment, two pixels of the same color filters (Rr) (Gg) (Bb) that are diagonally adjacent to each other constitute a pair pixel, and each detection signal of the pair pixel is read out from the solid-state imaging device 21 and then the pixel It is configured to add or read after adding pixels inside the solid-state imaging device 21.

以下、各ペア画素の一方の画素(右斜め上の第1群画素)を「主画素」といい、他方の画素(左斜め下の第2群画素)を「副画素」というものとする。主画素と副画素の各露光時間を同時間として被写体画像を撮像し、主画素と副画素の各検出信号を画素加算することで感度を倍にした撮影を行ったり、主画素の露光時間に対して副画素の露光時間を短時間として各検出信号を画素加算することで広ダイナミックレンジ撮影を行うことができる。あるいは、主画素の検出信号が充分な信号量になっていると判断した場合には、主画素の検出信号だけで被写体画像を生成し、また、主画素と副画素の各検出信号を別々に読み出し、画素加算せずに高精細な被写体画像を生成することも可能である。   Hereinafter, one pixel of each pair pixel (first diagonally upper right group pixel) is referred to as a “main pixel”, and the other pixel (lower second diagonal group pixel) is referred to as a “subpixel”. Capture the subject image with the exposure time of the main pixel and sub-pixel as the same time, and shoot by doubling the sensitivity by adding each detection signal of the main pixel and sub-pixel, or the exposure time of the main pixel On the other hand, wide dynamic range imaging can be performed by adding each detection signal to a pixel with the subpixel exposure time being short. Alternatively, if it is determined that the detection signal of the main pixel has a sufficient signal amount, a subject image is generated using only the detection signal of the main pixel, and the detection signals of the main pixel and sub-pixel are separately set. It is also possible to generate a high-definition subject image without reading and pixel addition.

図4は、図3に示す多数の画素のうち、水平方向に隣接する2つの主画素43aと、これらと夫々ペアを組む副画素43bを抜き出した図である。本実施形態の撮像素子21では、ペアを組む主画素43aと副画素43bとが1つの信号読出回路50を共用する構成となっている。符号51cについては、図6で説明する。   FIG. 4 is a diagram in which two main pixels 43a adjacent in the horizontal direction and the sub-pixels 43b each paired with these are extracted from the large number of pixels shown in FIG. In the imaging device 21 of the present embodiment, the main pixel 43a and the sub-pixel 43b that form a pair are configured to share one signal readout circuit 50. Reference numeral 51c will be described with reference to FIG.

図5は、図4に示す4つの画素の信号読出回路を示す図である。主画素43aと、これとペアを組む副画素43bとが夫々読出ゲート(TG:トランスファーゲートの略)51a,51bを介して共通(共有)の信号読出回路50に接続され、信号読出回路50の出力が出力線52に接続されている。信号読出回路50には、リセット端子と電源端子と行選択端子とが設けられている。   FIG. 5 is a diagram showing a signal readout circuit of the four pixels shown in FIG. The main pixel 43a and the sub-pixel 43b paired with the main pixel 43a are connected to a common (shared) signal readout circuit 50 via readout gates (TG: abbreviation of transfer gate) 51a and 51b, respectively. The output is connected to the output line 52. The signal readout circuit 50 is provided with a reset terminal, a power supply terminal, and a row selection terminal.

読出ゲート51aは主画素の読出パルス印加線(主画素TG線と表記)54に接続され、読出ゲート51bは副画素の読出パルス印加線(副画素TG線と表記)55に接続され、図示は省略しているが、リセット端子がリセット線に接続され、電源端子が電源線に接続され、行選択端子が行選択線に接続される。   The readout gate 51a is connected to a readout pulse application line (denoted as main pixel TG line) 54 of the main pixel, and the readout gate 51b is connected to a readout pulse application line (denoted as subpixel TG line) 55 of the subpixel. Although omitted, the reset terminal is connected to the reset line, the power supply terminal is connected to the power supply line, and the row selection terminal is connected to the row selection line.

主画素の読出パルス印加線54と、副画素の読出パルス印加線55と、リセット線,行選択線の計4本の信号配線が、垂直走査回路45から図2の水平配線46として画素行2行毎に敷設される。電源線と出力線52とが図2の垂直配線47として画素列毎に敷設され、水平走査回路44から該当電源線に電源電圧Vddが印加された画素列の信号読出回路50がイネーブル状態となり、撮像画像信号が出力線52に出力される。   A total of four signal wirings, that is, a readout pulse application line 54 for the main pixel, a readout pulse application line 55 for the sub-pixel, and a reset line and a row selection line are connected to the pixel row 2 from the vertical scanning circuit 45 as the horizontal wiring 46 in FIG. Laid for each row. The power supply line and the output line 52 are laid for each pixel column as the vertical wiring 47 in FIG. 2, and the signal readout circuit 50 of the pixel column in which the power supply voltage Vdd is applied from the horizontal scanning circuit 44 to the corresponding power supply line is enabled. A captured image signal is output to the output line 52.

図6は、本実施形態で採用した信号読出回路の構成図である。この信号読出回路50は、出力トランジスタ(FDトランジスタ)51と、出力トランジスタ51に直列接続された行選択トランジスタ54と、リセットトランジスタ53とを備える。   FIG. 6 is a configuration diagram of the signal readout circuit employed in the present embodiment. The signal readout circuit 50 includes an output transistor (FD transistor) 51, a row selection transistor 54 connected in series to the output transistor 51, and a reset transistor 53.

FDトランジスタ51のドレインが、水平走査回路44から電源電圧Vddが供給される電源端子50aに接続され、FDトランジスタ51のゲート・ドレイン間にリセットトランジスタ53が接続される。リセットトランジスタ53のゲート端子53aがリセット線に接続され、ドレインが電源端子50aに接続される。   The drain of the FD transistor 51 is connected to the power supply terminal 50 a to which the power supply voltage Vdd is supplied from the horizontal scanning circuit 44, and the reset transistor 53 is connected between the gate and drain of the FD transistor 51. The gate terminal 53a of the reset transistor 53 is connected to the reset line, and the drain is connected to the power supply terminal 50a.

FDトランジスタ51のソースが行選択トランジスタ54のドレインに接続され、行選択トランジスタ54のソース端子54aが出力線52に接続され、行選択トランジスタ54のゲート端子54bが行選択線に接続される。   The source of the FD transistor 51 is connected to the drain of the row selection transistor 54, the source terminal 54a of the row selection transistor 54 is connected to the output line 52, and the gate terminal 54b of the row selection transistor 54 is connected to the row selection line.

主画素のn領域43aと副画素のn領域43bとは近接して設けられると共に、n領域43aとn領域43bとの間にn領域51cが設けられる。このn領域51cが出力(FD)トランジスタ51のゲートに接続され、FDトランジスタ51は、主画素43aと副画素43bで共通に1つ設けられる。   The n region 43a of the main pixel and the n region 43b of the sub pixel are provided close to each other, and an n region 51c is provided between the n region 43a and the n region 43b. This n region 51c is connected to the gate of the output (FD) transistor 51, and one FD transistor 51 is provided in common for the main pixel 43a and the sub-pixel 43b.

即ち、主画素(n領域)43aとn領域51cとの間に読出ゲート51aを設け、副画素(n領域)43bとn領域51cとの間に読出ゲート51bを設け、主画素と副画素の各検出電荷を共通のn領域51cに読み出す構成としている。   In other words, the readout gate 51a is provided between the main pixel (n region) 43a and the n region 51c, and the readout gate 51b is provided between the sub pixel (n region) 43b and the n region 51c. Each detected charge is read out to a common n region 51c.

図7は、図4,図5,図6で説明した信号読出回路を用い、主画素43aと副画素43bが夫々検出した信号電荷を撮像素子21内部で画素加算(電荷混合)して読み出すシーケンス図である。読出パルス印加線54に読出パルス61が印加されると、主画素のn領域43aの蓄積電荷が図6のn領域51cに転送され、主画素43aの信号電荷は空となる。次に、読出パルス印加線55に読出パルス62が印加されると、副画素のn領域43bの蓄積電荷が図6のn領域51cに転送され、副画素43bの信号電荷は空となる。   FIG. 7 shows a sequence in which the signal charges detected by the main pixel 43a and the sub-pixel 43b are added to each other within the image pickup device 21 (charge mixing) and read using the signal readout circuit described in FIGS. FIG. When the readout pulse 61 is applied to the readout pulse application line 54, the accumulated charge in the n region 43a of the main pixel is transferred to the n region 51c in FIG. 6, and the signal charge of the main pixel 43a becomes empty. Next, when the readout pulse 62 is applied to the readout pulse application line 55, the accumulated charge in the n region 43b of the subpixel is transferred to the n region 51c in FIG. 6, and the signal charge of the subpixel 43b becomes empty.

この結果、n領域51cには主画素の検出電荷と副画素の検出電荷とが混合された状態で蓄積され、n領域51cで加算混合された電荷(主画素電荷+副画素電荷)が、出力トランジスタ51のゲートに印加されることになる。   As a result, the detection charge of the main pixel and the detection charge of the subpixel are accumulated in the n region 51c in a mixed state, and the charge (main pixel charge + subpixel charge) added and mixed in the n region 51c is output. This is applied to the gate of the transistor 51.

今、電源端子50aに水平走査回路44から電源電圧Vddが供給されているとする。垂直走査回路45から行選択トランジスタ54のゲート端子54bに行選択信号63が印加されてトランジスタ54がオン(導通)状態になると、出力トランジスタ51もオン(導通)状態となり、出力線52に上記の加算した信号電荷量に応じた信号が撮像画像信号として出力される。この撮像画像信号64が出力線52を通してアナログ信号処理部22に取り込まれ、以後の画像処理が行われる。   Assume that the power supply voltage Vdd is supplied from the horizontal scanning circuit 44 to the power supply terminal 50a. When the row selection signal 63 is applied from the vertical scanning circuit 45 to the gate terminal 54b of the row selection transistor 54 and the transistor 54 is turned on (conductive), the output transistor 51 is also turned on (conductive), and the above-described output line 52 is connected to the output line 52. A signal corresponding to the added signal charge amount is output as a captured image signal. The captured image signal 64 is taken into the analog signal processing unit 22 through the output line 52, and the subsequent image processing is performed.

その後にリセット信号がリセットトランジスタ53に印加されると、出力トランジスタ51のゲートに印加されていた信号電荷(加算電荷)は、リセットトランジスタ53を通して電源線Vddに廃棄され、n領域51aは空となる。   Thereafter, when a reset signal is applied to the reset transistor 53, the signal charge (addition charge) applied to the gate of the output transistor 51 is discarded to the power supply line Vdd through the reset transistor 53, and the n region 51a becomes empty. .

図8は、図4,図5,図6で説明した信号読出回路を用い、主画素の信号電荷量に応じた撮像画像信号と副画素の信号電荷量に応じた撮像画像信号とを撮像素子21外部に個別に読み出すシーケンス図である。この場合には、2つの撮像画像信号は、図1のデジタル信号処理部26でデジタル加算される。   8 uses the signal readout circuit described in FIG. 4, FIG. 5, and FIG. 6, and uses the imaging device to generate a captured image signal corresponding to the signal charge amount of the main pixel and a captured image signal corresponding to the signal charge amount of the sub-pixel. 21 is a sequence diagram for individually reading out to the outside. In this case, the two captured image signals are digitally added by the digital signal processing unit 26 of FIG.

この場合には、先ず、読出パルス印加線54に読出パルス61が印加される。これにより、主画素のn領域43aの蓄積電荷が図6のn領域51aに転送され、主画素43aの信号電荷は空となる。電源線には電源電圧Vddが印加されており、信号読出回路50はイネーブル状態にある。   In this case, first, the read pulse 61 is applied to the read pulse application line 54. As a result, the accumulated charge in the n region 43a of the main pixel is transferred to the n region 51a in FIG. 6, and the signal charge in the main pixel 43a becomes empty. A power supply voltage Vdd is applied to the power supply line, and the signal readout circuit 50 is in an enabled state.

出力トランジスタ51のゲートには、主画素43aが検出した信号電荷量が印加されるため、次のタイミングで行選択トランジスタ54に行選択信号65が印加されると、主画素43aの蓄積電荷量に応じた撮像画像信号66が出力線52に出力される。   Since the signal charge amount detected by the main pixel 43a is applied to the gate of the output transistor 51, when the row selection signal 65 is applied to the row selection transistor 54 at the next timing, the accumulated charge amount of the main pixel 43a is increased. A corresponding captured image signal 66 is output to the output line 52.

次のタイミングで、リセット信号67がリセットトランジスタ53印加されると、出力トランジスタ51のゲートに印加されていた信号電荷が電源線に廃棄され、図6のn領域51cは空となる。   When the reset signal 67 is applied to the reset transistor 53 at the next timing, the signal charge applied to the gate of the output transistor 51 is discarded to the power supply line, and the n region 51c in FIG. 6 becomes empty.

次のタイミングで読出パルス印加線55に読出パルス62が印加されると、副画素のn領域43bの蓄積電荷が図6のn領域51cに読み出され、副画素43bの信号電荷は空となる。出力トランジスタ51のゲートには副画素43bが検出した信号電荷量が印加されているため、行選択トランジスタ54に行選択信号68が印加されると、副画素43bの蓄積電荷量に応じた撮像画像信号69が出力線52に出力される。   When the readout pulse 62 is applied to the readout pulse application line 55 at the next timing, the accumulated charge in the n region 43b of the subpixel is read out to the n region 51c of FIG. 6, and the signal charge of the subpixel 43b becomes empty. . Since the signal charge amount detected by the sub-pixel 43b is applied to the gate of the output transistor 51, when a row selection signal 68 is applied to the row selection transistor 54, a captured image corresponding to the accumulated charge amount of the sub-pixel 43b. A signal 69 is output to the output line 52.

次に、リセット信号70がリセットトランジスタ53印加されると、出力トランジスタ51のゲートに印加されていた信号電荷が電源線に廃棄され、n領域51cは空となる。後段のデジタル信号処理部26は、主画素の撮像画像信号66と副画素の撮像画像信号69とを信号加算し、高感度な撮像画像信号としたり、広ダイナミックレンジの撮像画像信号とする。なお、撮像画像信号66と撮像画像信号69との信号加算は、デジタル変換前のアナログ信号(電圧値信号)の状態で加算しても良い。   Next, when the reset signal 70 is applied to the reset transistor 53, the signal charge applied to the gate of the output transistor 51 is discarded to the power supply line, and the n region 51c becomes empty. The digital signal processing unit 26 at the subsequent stage adds the captured image signal 66 of the main pixel and the captured image signal 69 of the sub-pixel to obtain a highly sensitive captured image signal or a captured image signal with a wide dynamic range. The signal addition of the captured image signal 66 and the captured image signal 69 may be performed in the state of an analog signal (voltage value signal) before digital conversion.

図9は、本発明の一実施形態に係る画素加算方法選択処理手順を示すフローチャートである。この画素加算方法選択処理は、図1のシステム制御部29が撮像素子を用いて被写体画像を撮影し、各画素が受光量に応じた信号電荷を蓄積した後に実行される。   FIG. 9 is a flowchart showing a pixel addition method selection processing procedure according to an embodiment of the present invention. This pixel addition method selection process is executed after the system control unit 29 in FIG. 1 captures a subject image using an image sensor and each pixel accumulates signal charges corresponding to the amount of received light.

撮像装置10による撮影処理が終了し、撮像素子21の各画素43a,43b内にシャッタ速度,露出等に応じた信号電荷が蓄積された後、先ず、ステップS1で、主画素43aの蓄積電荷をn領域51cに読み出す。   After the photographing process by the imaging device 10 is completed and signal charges corresponding to the shutter speed, exposure, and the like are accumulated in the pixels 43a and 43b of the image sensor 21, first, in step S1, the accumulated charges of the main pixel 43a are stored. Read to n region 51c.

次のステップS2では、主画素の信号電荷量の大きさが閾値α(FDの飽和量の50%)以上であるか否かを判定する。n領域51cに読み出された信号電荷量は、それに応じた撮像画像信号を出力線52に出力してみれば判断できる。   In the next step S2, it is determined whether or not the magnitude of the signal charge amount of the main pixel is equal to or greater than a threshold value α (50% of the saturation amount of FD). The signal charge amount read to the n region 51c can be determined by outputting a captured image signal corresponding to the signal charge amount to the output line 52.

図10は、閾値αを説明図である。主画素43aと副画素43bの各受光面積は同面積であり、露光時間も同時間であるため、主画素,副画素の受光量と信号レベルとは同じ比例関係となる。n領域51cの飽和電荷量(FDの飽和量)に対し、主画素43aの信号レベル(検出電荷)が半分以下であれば、主画素の検出電荷と同程度であると推測でき、副画素43bの検出電荷をn領域51cに読み出しても、n領域51cが溢れる蓋然性は小さいと判断できる。   FIG. 10 is an explanatory diagram of the threshold value α. Since the light receiving areas of the main pixel 43a and the sub pixel 43b are the same area and the exposure time is also the same time, the light receiving amounts of the main pixel and the sub pixel and the signal level have the same proportional relationship. If the signal level (detected charge) of the main pixel 43a is less than or equal to the saturation charge amount (FD saturation amount) of the n region 51c, it can be estimated that it is the same level as the detected charge of the main pixel. It can be determined that the probability that the n region 51c overflows is small even if the detected charges of the n region 51c are read out.

このため、主画素43aから読み出した信号電荷量が閾値α以上でない場合には、ステップS2からステップS3に進み、n領域51cに、副画素43bの蓄積電荷を読み出す。この結果、n領域51cには、主画素と副画素の合計した信号電荷量が読み出されることになる。次のステップS4では、この加算混合した信号電荷量に応じた撮像画像信号を出力線52に出力し、この処理を終了する。   Therefore, if the signal charge amount read from the main pixel 43a is not equal to or greater than the threshold value α, the process proceeds from step S2 to step S3, and the accumulated charge of the sub-pixel 43b is read to the n region 51c. As a result, the total signal charge amount of the main pixel and the sub-pixel is read out to the n region 51c. In the next step S4, a picked-up image signal corresponding to the added and mixed signal charge amount is output to the output line 52, and this process is terminated.

ステップS2の判定の結果、主画素43aの検出電荷量が閾値α以上の場合には、副画素43bの検出電荷を一緒にn領域51cに読み出してしまうとn領域51cが溢れてしまう。そこで、この場合にはステップS2からステップS5に進み、n領域51cの信号電荷量(主画素43aの信号電荷のみ)に応じた撮像画像信号を出力線52に出力させ、ステップS6で、この主画素のみの撮像画像信号をメモリ30(図1)に保存する。   If the detection charge amount of the main pixel 43a is equal to or greater than the threshold value α as a result of the determination in step S2, the n region 51c overflows if the detection charge of the sub-pixel 43b is read together into the n region 51c. Therefore, in this case, the process proceeds from step S2 to step S5, and the picked-up image signal corresponding to the signal charge amount of the n region 51c (only the signal charge of the main pixel 43a) is output to the output line 52. A captured image signal of only pixels is stored in the memory 30 (FIG. 1).

次のステップS7では、リセット信号(図8の信号67)を印加し、n領域51cを空とする(ステップS8)。次のステップS9で、副画素43bの検出電荷をn領域51cに読み出す。そして、ステップS10でn領域51c内の信号電荷量に応じた撮像画像信号を出力線52に出力させ、この副画素の撮像画像信号と、ステップS6でメモリ30に待機しておいた主画素の撮像画像信号とを信号加算(電圧加算)して(ステップS11)、この処理を終了する。信号加算した画素加算信号は、そのまま用いても、平均値を求めて撮像画像信号としても良い。   In the next step S7, a reset signal (signal 67 in FIG. 8) is applied, and the n region 51c is emptied (step S8). In the next step S9, the detected charge of the sub-pixel 43b is read out to the n region 51c. In step S10, a captured image signal corresponding to the signal charge amount in the n region 51c is output to the output line 52, and the captured image signal of the sub-pixel and the main pixel waiting in the memory 30 in step S6. A signal addition (voltage addition) is performed on the captured image signal (step S11), and this process ends. The pixel addition signal obtained by signal addition may be used as it is, or an average value may be obtained as a captured image signal.

なお、ステップS2における閾値αとの比較判定は、撮像素子21の受光面のうち、撮影処理前に行うAE処理で得た露出データを用い、入射光量が一番大きいと判断した部分領域の主画素から読み出した信号電荷量で判断しても良い。   Note that the comparison with the threshold value α in step S2 is performed by using the exposure data obtained by the AE process performed before the imaging process on the light receiving surface of the image sensor 21, and using the exposure data obtained by the AE process performed before the imaging process. You may judge by the signal charge amount read from the pixel.

図11は、本発明の別実施形態に係る画素加算方法選択処理手順を示すフローチャートである。基本的には、図9の画素加算方法選択処理手順と同じであるが、本実施形態では、主画素の信号電荷量が大きかった場合の処理ステップを付加している点のみ異なる。   FIG. 11 is a flowchart showing a pixel addition method selection processing procedure according to another embodiment of the present invention. Basically, it is the same as the pixel addition method selection processing procedure of FIG. 9, but the present embodiment is different only in that processing steps are added when the signal charge amount of the main pixel is large.

本実施形態では、ステップS1の後にステップS15の判定処理を行う。この判定処理S15では、撮像素子受光面のうち上記の入射光量が一番大きいと判断した部分領域の主画素からn領域51cに読み出した信号電荷量が、閾値αより大きな所定の閾値βより大きいか否かを判定する。   In this embodiment, the determination process of step S15 is performed after step S1. In this determination process S15, the signal charge amount read from the main pixel of the partial area determined to have the largest incident light amount to the n area 51c in the imaging element light receiving surface is larger than a predetermined threshold value β that is larger than the threshold value α. It is determined whether or not.

主画素から読み出した信号電荷量が閾値βより大きな場合にはステップS15からステップS16に進み、主画素の信号電荷量に応じた撮像画像信号を出力線52に出力し、この処理を終了する。即ち、この場合には、「画素加算」は行わず、主画素の検出信号だけで被写体画像を生成する。   When the signal charge amount read from the main pixel is larger than the threshold value β, the process proceeds from step S15 to step S16, and a captured image signal corresponding to the signal charge amount of the main pixel is output to the output line 52, and this process is terminated. That is, in this case, “pixel addition” is not performed, and the subject image is generated only with the detection signal of the main pixel.

ステップS15の判定の結果、主画素の検出電荷が閾値βより小さい場合には、ステップS2に進み、以下、図9の処理ステップ手順と同じ手順で処理を進めていく。   As a result of the determination in step S15, when the detected charge of the main pixel is smaller than the threshold value β, the process proceeds to step S2, and the process proceeds with the same procedure as the process step procedure of FIG.

この様に、主画素の信号電荷量(検出電荷)が閾値βより大きい場合、図12に示す様に、主画素の信号電荷量だけで十分な信号量が得られ、主画素の信号電荷だけで広いダイナミックレンジの撮像画像信号が得られる蓋然性が高いと判断できるため、画素加算をスキップできる。閾値βとしては、FDの飽和量の80%や70%とすることで良い。   In this manner, when the signal charge amount (detection charge) of the main pixel is larger than the threshold value β, as shown in FIG. 12, a sufficient signal amount can be obtained only by the signal charge amount of the main pixel, and only the signal charge of the main pixel is obtained. Since it can be determined that the probability of obtaining a captured image signal with a wide dynamic range is high, pixel addition can be skipped. The threshold value β may be 80% or 70% of the saturation amount of the FD.

図9の処理手順、図11の処理手順において、画素加算する方法を、信号電荷の電荷混合による方法(ステップS4:第2画素加算駆動モード)とするか、信号加算による方法(ステップS11:第1画素加算駆動モード)とするかを、主画素の信号電荷量で判断(ステップS2,ステップS15)したが、撮影条件によっては、一々、主画素の信号電荷量で判断するまでもない場合がある。   In the processing procedure of FIG. 9 and the processing procedure of FIG. 11, the pixel addition method is a method based on charge mixing of signal charges (step S4: second pixel addition drive mode) or a method based on signal addition (step S11: first step). Whether or not to select the one-pixel addition drive mode) is determined based on the signal charge amount of the main pixel (steps S2 and S15). However, depending on the shooting conditions, it may not be necessary to determine the signal charge amount of the main pixel one by one. is there.

例えば、撮影処理前にユーザが撮像装置10の操作部33から「連写モード」を選択していた場合、個々の撮影のシャッタ速度は短時間のため、主画素の信号電荷量は閾値αより「小さい」と判断できる場合がある。この場合には、例えばステップ1の後に「連写モード」で撮影が行われたか否かを判定し、連写モードの場合には強制的にステップS3に進む様にすれば良い。これにより、時間のかかる信号処理による画素加算が回避されることになる。   For example, when the user selects the “continuous shooting mode” from the operation unit 33 of the imaging apparatus 10 before the shooting process, the signal charge amount of the main pixel exceeds the threshold value α because the shutter speed of each shooting is short. In some cases, it can be judged as “small”. In this case, for example, after step 1, it is determined whether or not shooting has been performed in the “continuous shooting mode”, and in the continuous shooting mode, the process may be forcibly advanced to step S3. Thereby, pixel addition due to time-consuming signal processing is avoided.

同様に、撮影処理前に、ユーザがISO感度を指定した場合、あるいはオート設定で撮像装置10が自動的にISO感度を設定した場合で、ISO感度が所定感度以上(例えばISO400以上)となった場合、撮影シーンが暗いため、上記と同様に、主画素に蓄積される信号電荷量は閾値αより「小さい」と判断できる。この場合も、ステップS1の後にISO感度を判定し、所定ISO感度より大きいとき強制的にステップS3に進むようにすれば良い。低ISO感度(ISO400未満)の場合には、撮影シーンが明るいため、強制的にステップS5に進むことで、ダイナミックレンジの広い被写体画像を撮像することが可能となる。   Similarly, when the user specifies the ISO sensitivity before the shooting process, or when the imaging device 10 automatically sets the ISO sensitivity by auto setting, the ISO sensitivity becomes equal to or higher than a predetermined sensitivity (for example, ISO 400 or higher). In this case, since the shooting scene is dark, it can be determined that the signal charge amount accumulated in the main pixel is “smaller” than the threshold value α, as described above. In this case as well, the ISO sensitivity is determined after step S1, and when the sensitivity is higher than the predetermined ISO sensitivity, the process may be forced to proceed to step S3. In the case of low ISO sensitivity (less than ISO 400), the shooting scene is bright, and forcibly proceeding to step S5 makes it possible to capture a subject image with a wide dynamic range.

この様に、撮影条件によって主画素の信号電荷量が閾値αに達しないと判断できる場合には強制的に信号電荷の電荷混合による画素加算を選択することで、無駄な処理を省き、処理時間の短縮化を図ることが可能となる。   In this way, when it can be determined that the signal charge amount of the main pixel does not reach the threshold value α according to the shooting conditions, it is possible to forcibly select the pixel addition based on the charge mixture of the signal charges, thereby eliminating unnecessary processing and processing time. Can be shortened.

野外で撮影を行う場合、晴れた空や太陽で照らされた部分(明るい部分)と影の部分とが存在し、広いダイナミックレンジが要求される。例えば、図13(a)に示される野外の撮影シーンでは、明るい部分と暗い部分とが混在することになる。   When shooting outdoors, a clear sky, a portion illuminated by the sun (bright portion), and a shadow portion exist, and a wide dynamic range is required. For example, in the outdoor shooting scene shown in FIG. 13A, a bright part and a dark part are mixed.

この様な場合、撮像素子受光面を複数ブロックに領域分割し、各分割ブロック毎に、画素加算方法を、信号加算による画素加算とするか、信号電荷の電荷混合による画素加算とするかを場合分けして行うのが良い。   In such a case, the image sensor light-receiving surface is divided into a plurality of blocks, and for each divided block, whether the pixel addition method is pixel addition by signal addition or pixel addition by signal charge mixture It is good to do it separately.

例えば、図13(b)に示す様に、受光面を5行5列の計25の分割ブロックに領域分割し、A行,B行のブロックは信号加算による画素加算を行い、D行,F行のブロックは電荷混合による画素加算を行う。そして、C行においては、イ列,ロ列,ニ列,ホ列は信号加算、ハ列は電荷混合による画素加算を行う様にする。   For example, as shown in FIG. 13B, the light receiving surface is divided into a total of 25 divided blocks of 5 rows and 5 columns, and the blocks of rows A and B are subjected to pixel addition by signal addition, and rows D and F Row blocks perform pixel addition by charge mixing. In the C row, signal addition is performed for columns A, B, D, and E, and pixel addition by charge mixing is performed for column C.

MOSトランジスタ回路を信号読出回路とする撮像素子の場合、各ペア画素への信号読出をランダムアクセスすることで行うことができ、ペア画素単位,ブロック単位に画素加算の方法を変えることが可能となる。   In the case of an image pickup device using a MOS transistor circuit as a signal readout circuit, signal readout to each pair pixel can be performed by random access, and the pixel addition method can be changed for each pair pixel and block. .

A行,B行,D行,F行の各ブロックからの信号読出は同一行の各画素の信号加算方法が同じとなるため、その説明は省略し、C行の各ブロックからの信号読出方法(画素加算方法)について説明する。   The signal readout from each block of the A row, B row, D row, and F row is the same as the signal addition method for each pixel in the same row. Therefore, the description thereof is omitted, and the signal readout method from each block of the C row. (Pixel addition method) will be described.

C行ブロックの信号読出時には、先ず、ハ列のブロックの撮像画像信号から信号読出を行う。この場合、イ列,ロ列,ニ列,ホ列の各信号読出回路への電源電圧Vddの供給は止め、各信号読出回路50をディスイネーブル状態とする。そして、ハ列の信号読出回路の電源線にだけ電源電圧Vddを印加し、イネーブル状態とする。勿論、この電源電圧Vddの印加は、水平走査回路44によって1ペア画素列毎に行う。   When reading the signal of the C row block, first, signal reading is performed from the captured image signal of the block of column C. In this case, the supply of the power supply voltage Vdd to the signal readout circuits in the first row, second row, second row, and third row is stopped, and each signal read circuit 50 is disabled. Then, the power supply voltage Vdd is applied only to the power supply line of the signal readout circuit in the row C to enable it. Of course, the power supply voltage Vdd is applied by the horizontal scanning circuit 44 for each pair of pixel columns.

そして、図5の主画素TG線54に読出パルス61(図8参照)を印加すると、C行の同一行の全て(イ列,ロ列,ニ列,ホ列を含む)の主画素43aの信号電荷がn領域51cに読み出される。次に、行選択信号65を印加すると、ハ列の主画素の検出信号に応じた撮像画像信号が出力線52に出力されることになる。しかし、イ列,ロ列,ニ列,ホ列の信号読出回路50は不活性(ディスイネーブル状態)なため、撮像画像信号は出力されない。   Then, when a readout pulse 61 (see FIG. 8) is applied to the main pixel TG line 54 of FIG. 5, all of the main pixels 43a in the same row of C rows (including columns A, B, D, and E) are displayed. The signal charge is read out to the n region 51c. Next, when the row selection signal 65 is applied, a captured image signal corresponding to the detection signal of the main pixel in column C is output to the output line 52. However, since the signal readout circuits 50 in the first row, second row, second row, and first row are inactive (disabled), no captured image signal is output.

次に、リセット信号67を印加すると、ハ列のn領域51cの信号電荷は電源線に廃棄されるが、イ列,ロ列,ニ列,ホ列のn領域51cの信号電荷は、リセットトランジスタが不活性のためそのままn領域51cに残る。   Next, when the reset signal 67 is applied, the signal charges in the n region 51c in the first column are discarded to the power supply line, but the signal charges in the n region 51c in the first column, the second column, the second column, and the third column are Remains in the n region 51c as it is inactive.

次に、副画素TG線55に読出パルス62を印加すると、C行の同一行の全て(イ列,ロ列,ニ列,ホ列を含む)の副画素43bの信号電荷がn領域51cに読み出される。イ列,ロ列,ニ列,ホ列のn領域51cでは、主画素+副画素の信号電荷が混合した状態となる。しかし、ハ列のn領域51cにおいては、副画素43bの信号電荷だけが蓄積される。   Next, when the readout pulse 62 is applied to the sub-pixel TG line 55, the signal charges of all the sub-pixels 43b in the same row of C rows (including columns A, B, D, and E) are applied to the n region 51c. Read out. In the n region 51c of the A-row, B-row, D-row, and H-row, the signal charges of the main pixel + sub-pixel are mixed. However, only the signal charge of the sub-pixel 43b is accumulated in the n region 51c in the row C.

次に行選択信号68が印加されると、ハ列の撮像画像信号69だけが出力線52に出力され、イ列,ロ列,ニ列,ホ列の撮像画像信号は夫々の信号読出回路50が不活性のため出力されない。そして、リセット信号を70を印加することで、ハ列のn領域51cは空となる。   Next, when the row selection signal 68 is applied, only the picked-up image signals 69 in the first column are output to the output line 52, and the picked-up image signals in the first column, the second column, the second column, and the third column are output from the respective signal readout circuits 50. Is not output due to inactivity. Then, by applying 70 as the reset signal, the n region 51c in the row C becomes empty.

この様にして、ハ列の主画素からの撮像画像信号66と、ハ列の副画素からの撮像画像信号69とが別々に読み出された後、信号処理回路による信号加算によって画素加算が行われる。   In this way, after the captured image signal 66 from the main pixel in the column C and the captured image signal 69 from the sub-pixel in the column C are read out separately, pixel addition is performed by signal addition by the signal processing circuit. Is called.

一方、イ列,ロ列,ニ列,ホ列のn領域51cには、主画素の信号電荷と副画素の信号電荷とが混合した状態で維持されている。このため、ハ列の信号読出回路への電源電圧Vddの供給を停止し、イ列,ロ列,ニ列,ホ列の信号読出回路50への電源電圧Vddの水平走査と行選択信号の垂直走査とを行うことで、電荷混合した画素加算信号が出力線52に出力されることになる。   On the other hand, in the n region 51c of the A-row, B-row, D-row, and H-row, the main pixel signal charge and the sub-pixel signal charge are maintained in a mixed state. For this reason, the supply of the power supply voltage Vdd to the signal readout circuit in the column C is stopped, the horizontal scanning of the power supply voltage Vdd to the signal readout circuit 50 in the columns A, B, D, and H and the vertical selection of the row selection signal. By performing scanning, a pixel addition signal in which charges are mixed is output to the output line 52.

上述した信号読出(画素加算)を行う場合、C行では、図14(a)に示す様に、電荷混合した信号(主画素+副画素)71が出力される場合と、図14(b)に示す様に、主画素信号72と副画素信号73とが別々に出力される場合とが混在することになる。   When performing the above-described signal readout (pixel addition), as shown in FIG. 14A, in the row C, a signal (main pixel + subpixel) 71 in which charge is mixed is output, and FIG. As shown in FIG. 6, the main pixel signal 72 and the sub-pixel signal 73 are mixed and output separately.

後段の信号処理回路26は、ブロック毎に別々の信号処理ができない様に設計される場合が多く、同一ペア画素行の出力信号として、信号71だけのときと信号72,73の両方が存在するときとが混在すると、信号処理を誤る虞がある。例えば、電荷混合の画素加算を行う図14(a)では「主画素」の信号電荷75だけの出力は行わないが、この位置にノイズ等が重畳していると、このノイズを「撮像画像信号」と誤認する虞がある。   The signal processing circuit 26 in the subsequent stage is often designed so that separate signal processing cannot be performed for each block, and both the signal 71 and the signals 72 and 73 exist as output signals of the same pair pixel row. If time is mixed, there is a risk of signal processing being mistaken. For example, in FIG. 14A in which charge-mixing pixel addition is performed, only the signal charge 75 of the “main pixel” is not output, but if noise or the like is superimposed at this position, this noise is expressed as “captured image signal”. May be mistaken.

そこで、本実施形態では、図15に示す様に、アナログ信号処理部22の前段に、マスク信号発生回路76と加算回路77とを設け、マスク信号発生回路76がオン(ハイ)信号を出力しているときだけ、撮像素子21の出力信号をアナログ信号処理部22に通すことにし、図14(a)の主画素電荷75の読出位置に対応する信号位置ではダミー信号78を出力する様にする。これにより、デジタル信号処理部26は信号処理を誤る虞がなくなる。   Therefore, in the present embodiment, as shown in FIG. 15, a mask signal generation circuit 76 and an addition circuit 77 are provided in the preceding stage of the analog signal processing unit 22, and the mask signal generation circuit 76 outputs an on (high) signal. The output signal of the image sensor 21 is passed through the analog signal processing unit 22 only when the signal is output, and the dummy signal 78 is output at the signal position corresponding to the read position of the main pixel charge 75 in FIG. . Thereby, there is no possibility that the digital signal processing unit 26 makes a mistake in signal processing.

図16は、図13〜図15を用いて説明した実施形態の処理手順を示すフローチャートである。先ず、ステップS21で、撮影処理前のAE(自動露出)処理で取得したAEデータを図13の分割ブロック毎に取り込む。そして、次のステップS22で、各分割ブロックの露出値が所定閾値以上であるか否かを夫々判定する。   FIG. 16 is a flowchart illustrating a processing procedure of the embodiment described with reference to FIGS. First, in step S21, the AE data acquired by the AE (automatic exposure) process before the photographing process is fetched for each divided block in FIG. In the next step S22, it is determined whether or not the exposure value of each divided block is equal to or greater than a predetermined threshold value.

ステップS22の判定の結果、露出値が所定閾値未満のブロックの場合には、暗いシーンのブロックであるためステップS23に進み、信号電荷の電荷混合による画素加算処理を行うブロックとする。ステップS22の判定の結果、露出値が所定閾値以上のブロックの場合には、ステップS24に進み、信号加算による画素加算処理を行うブロックとする。   If the result of determination in step S22 is that the exposure value is less than the predetermined threshold, the block is a dark scene and the process proceeds to step S23, where the pixel addition processing is performed by signal charge mixture. If the result of determination in step S22 is that the exposure value is a block greater than or equal to a predetermined threshold, the process proceeds to step S24, where the pixel addition process is performed by signal addition.

ステップS24の次のステップS25では、信号加算を行うため、先ず主画素の信号電荷量に応じた撮像画像信号を出力線52に出力してメモリ30に保存し(ステップS26)、ステップS27で副画素の信号電荷量に応じた撮像画像信号を出力線52に出力し、ステップS31で、主画素の撮像画像信号と副画素の撮像画像信号とを信号加算し、この処理を終了する。   In step S25 following step S24, in order to perform signal addition, first, a captured image signal corresponding to the signal charge amount of the main pixel is output to the output line 52 and stored in the memory 30 (step S26). A captured image signal corresponding to the signal charge amount of the pixel is output to the output line 52. In step S31, the captured image signal of the main pixel and the captured image signal of the sub-pixel are added, and this process ends.

信号電荷の電荷混合を行うブロックの場合には、ステップS23の次のステップS28で図14(a)のダミー信号78を出力し、このダミー信号78をメモリ30に保存する(ステップS29)。そして、ステップS30で「主画素+副画素」の電荷混合した撮像画像信号を出力線52に出力し、ステップS31で、メモリ30のダミー信号(出力0)78と加算し、この処理を終了する。   In the case of a block that mixes signal charges, the dummy signal 78 shown in FIG. 14A is output in step S28 following step S23, and the dummy signal 78 is stored in the memory 30 (step S29). Then, in step S30, the captured image signal in which the charge of “main pixel + subpixel” is mixed is output to the output line 52, and in step S31, it is added to the dummy signal (output 0) 78 of the memory 30, and this process is terminated. .

ステップS25に対しステップS28を設け、ステップS26に対しステップS29を設けたのは、信号処理回路26が行う処理手順を、画素加算方法が異なるブロック行で同じ信号処理とするためである。   The reason why Step S28 is provided for Step S25 and Step S29 is provided for Step S26 is that the processing procedure performed by the signal processing circuit 26 is the same signal processing in block rows with different pixel addition methods.

本実施形態によれば、分割ブロック毎に画素加算方法を変えたが、画素加算方法が異なるだけで、ブロック間で積算の明るさが異なる訳ではないため、ブロックの境界で段差が発生することはない。本実施形態によれば、高輝度部分のダイナミックレンジを拡大することができ、また、低輝度部分の暗時ノイズの低減を図ることが可能となる。   According to the present embodiment, the pixel addition method is changed for each divided block. However, only the pixel addition method is different, and the brightness of integration is not different between blocks, so that a step occurs at the boundary of the block. There is no. According to the present embodiment, the dynamic range of the high luminance part can be expanded, and the dark noise of the low luminance part can be reduced.

なお、上述した実施形態では、図3に示す様に、奇数行の光電変換素子行に対して偶数行の光電変換素子行を1/2ピッチづつずらした所謂ハニカム画素配列としたが、上述した実施形態はこのハニカム画素配列に限るものではなく、画素配列が正方格子配列で、奇数行又は奇数列の各画素(光電変換素子)にカラーフィルタをベイヤ配列し偶数行又は偶数列の各画素にカラーフィルタをベイヤ配列した撮像素子にも同様に適用可能である。   In the above-described embodiment, as shown in FIG. 3, a so-called honeycomb pixel array in which even-numbered photoelectric conversion element rows are shifted by 1/2 pitch with respect to odd-numbered photoelectric conversion element rows is used. The embodiment is not limited to this honeycomb pixel arrangement, and the pixel arrangement is a square lattice arrangement, and color filters are Bayer-arranged in pixels (photoelectric conversion elements) in odd rows or odd columns, and are arranged in even rows or even columns. The present invention can be similarly applied to an image sensor in which color filters are arranged in a Bayer array.

また、上述した実施形態では、光電変換素子として半導体基板に形成したフォトダイオードを用いたが、本発明はこれに限るものではなく、半導体基板の上層に例えば有機膜でなる光電変換膜を積層し、この光電変換膜を共通電極膜と画素毎の画素電極膜で挟んだ撮像素子にも適用可能である。   In the above-described embodiment, the photodiode formed on the semiconductor substrate is used as the photoelectric conversion element. However, the present invention is not limited to this, and a photoelectric conversion film made of, for example, an organic film is stacked on the semiconductor substrate. The present invention can also be applied to an image sensor in which this photoelectric conversion film is sandwiched between a common electrode film and a pixel electrode film for each pixel.

更に、上述した実施形態では、主画素と副画素の各受光面積を同じ受光面積として説明したが、主画素の受光面積に対して副画素の受光面積を小面積とした撮像素子にも上述した各実施形態を適用可能である。   Further, in the above-described embodiment, the light receiving areas of the main pixel and the sub-pixel are described as the same light receiving area, but the above-described image sensor is also described in which the light receiving area of the sub-pixel is smaller than the light receiving area of the main pixel. Each embodiment is applicable.

以上述べた実施形態の撮像装置及びその画素加算方法は、複数の光電変換素子が半導体基板上に二次元アレイ状に配列形成される共に、隣接する2つの前記光電変換素子をペア画素とし該ペア画素を1単位としてカラーフィルタがベイヤ配列され、該ペア画素毎に前記半導体基板にMOSトランジスタ回路でなる信号読出回路が形成される撮像素子と、前記撮像素子に付設され該撮像素子の前記信号読出回路から出力される撮像画像信号を処理する信号処理回路とを備える撮像装置及びその画素加算方法であって、
前記ペア画素を構成する2つの前記光電変換素子の各検出電荷に応じた撮像画像信号を個別に前記信号読出回路で読み出し前記信号処理回路で信号加算させる第1画素加算駆動モードと、前記ペア画素の2つの前記光電変換素子の各検出電荷を混合し、該混合した電荷量に応じた撮像画像信号を前記信号読出回路で読み出す第2画素加算駆動モードとを、前記撮像素子で被写体画像を撮影するときの撮影状態に応じて切り換える撮像素子駆動手段とを備えることを特徴とする。
In the imaging apparatus and the pixel addition method thereof according to the embodiments described above, a plurality of photoelectric conversion elements are arranged in a two-dimensional array on a semiconductor substrate, and two adjacent photoelectric conversion elements are used as a pair pixel. An image sensor in which a color filter is Bayer-arrayed with one pixel as a unit, and a signal readout circuit composed of a MOS transistor circuit is formed on the semiconductor substrate for each paired pixel, and the signal readout of the image sensor attached to the image sensor An image pickup apparatus including a signal processing circuit that processes a picked-up image signal output from a circuit and a pixel addition method thereof,
A first pixel addition drive mode in which captured image signals corresponding to the detected charges of the two photoelectric conversion elements constituting the pair pixel are individually read out by the signal readout circuit and added by the signal processing circuit; and the pair pixel The detection charges of the two photoelectric conversion elements are mixed, and a second pixel addition drive mode in which a captured image signal corresponding to the mixed charge amount is read by the signal readout circuit, and a subject image is captured by the imaging element And an image sensor driving means for switching in accordance with a shooting state at the time of shooting.

また、実施形態の撮像装置及びその画素加算方法の前記撮像素子は、奇数行の光電変換素子行が偶数行の光電変換素子行に対して1/2ピッチづつずらして形成されることを特徴とする。   Further, the imaging device of the imaging device and the pixel addition method thereof according to the embodiment is characterized in that the odd-numbered photoelectric conversion element rows are formed by being shifted by 1/2 pitch with respect to the even-numbered photoelectric conversion element rows. To do.

また、実施形態の撮像装置及びその画素加算方法は、前記第1画素加算駆動モードと前記第2画素加算駆動モードとの切換を判断する前記撮影状態は、前記ペア画素の一方の光電変換素子が検出した電荷量が第1閾値以上であるか否かで判断することを特徴とする。   In the imaging apparatus and the pixel addition method thereof according to the embodiment, one photoelectric conversion element of the pair of pixels is in the photographing state in which switching between the first pixel addition drive mode and the second pixel addition drive mode is determined. Judgment is made based on whether or not the detected charge amount is equal to or greater than a first threshold value.

また、実施形態の撮像装置及びその画素加算方法は、前記ペア画素の一方の前記光電変換素子が検出した電荷量が前記第1閾値より大きな第2閾値以上のときは該一方の前記光電変換素子の検出した電荷により前記被写体画像を生成することを特徴とする。   Further, in the imaging apparatus and the pixel addition method thereof according to the embodiment, when the amount of charge detected by one of the photoelectric conversion elements of the paired pixels is equal to or larger than a second threshold value that is larger than the first threshold value, the one photoelectric conversion element The subject image is generated based on the detected charges.

また、実施形態の撮像装置及びその画素加算方法は、連写モードによって前記被写体画像が撮影されたときは前記第2画素加算駆動モードを強制的に実行することを特徴とする。   In addition, the imaging apparatus and the pixel addition method thereof according to the embodiment are characterized in that the second pixel addition drive mode is forcibly executed when the subject image is captured in the continuous shooting mode.

また、実施形態の撮像装置及びその画素加算方法は、前記被写体画像を撮影するときのISO感度が所定ISO感度より低いとき前記第1画素加算駆動モードを強制的に実行し、所定ISO感度より高いとき前記第2画素加算駆動モードを強制的に実行することを特徴とする。   In addition, the imaging apparatus and the pixel addition method thereof according to the embodiment forcibly execute the first pixel addition drive mode when the ISO sensitivity when shooting the subject image is lower than the predetermined ISO sensitivity, and is higher than the predetermined ISO sensitivity. The second pixel addition drive mode is forcibly executed.

また、実施形態の撮像装置及びその画素加算方法は、前記光電変換素子が形成された前記撮像素子の受光面を複数ブロックに領域分割し、各分割ブロック毎に、前記撮像素子駆動手段は前記第1画素加算駆動モードと前記第2画素加算駆動モードとを切り換えることを特徴とする。   In the imaging apparatus and the pixel addition method thereof according to the embodiment, the light receiving surface of the imaging element on which the photoelectric conversion element is formed is divided into a plurality of blocks, and the imaging element driving unit is configured to The one-pixel addition drive mode and the second pixel addition drive mode are switched.

また、実施形態の撮像装置及びその画素加算方法は、前記第1画素加算駆動モードと前記第2画素加算駆動モードとが混在した状態で同一行の前記ペア画素行から前記信号読出回路が前記撮像画像信号を読み出すとき、前記第2画素加算駆動モードによる前記撮像素子の出力タイミングのうち、前記第1画素加算駆動モードで出力される前記ペア画素のうちの最初に読み出される撮像画像信号の出力タイミングと同じ位置にダミー信号を出力させ、該ダミー信号と前記混合した電荷量に応じた撮像画像信号とを前記信号処理回路で信号加算し、該信号処理回路による信号処理を、前記第1画素加算駆動モードにより前記撮像素子から出力された信号の信号加算処理と同じ処理としたことを特徴とする。   In the imaging apparatus and the pixel addition method thereof according to the embodiment, the signal readout circuit captures the image from the paired pixel rows in the same row in a state where the first pixel addition drive mode and the second pixel addition drive mode are mixed. When reading out an image signal, among the output timings of the image sensor in the second pixel addition drive mode, the output timing of the imaged image signal read out first among the pair of pixels output in the first pixel addition drive mode A dummy signal is output at the same position as the signal, and the dummy signal and the captured image signal corresponding to the mixed charge amount are added by the signal processing circuit, and the signal processing by the signal processing circuit is added to the first pixel. The processing is the same as the signal addition processing of the signal output from the image sensor in the driving mode.

以上述べた実施形態によれば、撮影状態,撮影条件に応じて、画素加算方法を適切な方法にするため、撮影状態,撮影条件によらずに常に最適な品質の被写体画像を撮像することが可能となる。   According to the embodiment described above, in order to make the pixel addition method appropriate according to the shooting state and shooting conditions, it is possible to always capture a subject image of optimum quality regardless of the shooting state and shooting conditions. It becomes possible.

本発明に係る画素加算方法選択処理は、撮影条件等に応じて適切な画素加算方法が選択されるため、高品質や広ダイナミックレンジの撮像画像を撮影することが可能となり、デジタルスチルカメラやデジタルビデオカメラ,カメラ付携帯電話機,カメラ付電子機器,内視鏡等の各種デジタルカメラに適用すると有用である。   In the pixel addition method selection processing according to the present invention, since an appropriate pixel addition method is selected according to the shooting conditions and the like, it becomes possible to capture a high-quality and wide dynamic range captured image, and a digital still camera or digital It is useful when applied to various digital cameras such as video cameras, camera-equipped mobile phones, electronic devices with cameras, and endoscopes.

10 撮像装置
21 撮像素子
22 アナログ信号処理部
24 駆動部
26 デジタル信号処理部
29 システム制御部(CPU)
30 メモリ
41 半導体基板
43 画素(光電変換素子)
43a 主画素
43b 副画素
44 水平走査回路
45 垂直走査回路
50 信号読出回路
51 主画素,副画素の共有の出力トランジスタ(FDトランジスタ)
51a,51b 読出ゲート
51c FDトランジスタの主画素,副画素共有のn領域
52 出力線
53 リセットトランジスタ
54 行選択トランジスタ
54 主画素の読出パルス印加線(主画素TG線)
55 副画素の読出パルス印加線(副画素TG線)
61,62 読出パルス
64,66,69,71,72,73 出力信号
63,65,68 行選択線
67,70 リセット信号
76 マスク信号発生回路
77 加算回路
78 ダミー出力
DESCRIPTION OF SYMBOLS 10 Imaging device 21 Imaging device 22 Analog signal processing part 24 Drive part 26 Digital signal processing part 29 System control part (CPU)
30 Memory 41 Semiconductor substrate 43 Pixel (photoelectric conversion element)
43a main pixel 43b subpixel 44 horizontal scanning circuit 45 vertical scanning circuit 50 signal readout circuit 51 shared output transistor (FD transistor) of main pixel and subpixel
51a, 51b Read gate 51c FD transistor main pixel, subpixel shared n region 52 Output line 53 Reset transistor 54 Row selection transistor 54 Read pulse application line for main pixel (main pixel TG line)
55 Sub-pixel readout pulse application line (sub-pixel TG line)
61, 62 Read pulse 64, 66, 69, 71, 72, 73 Output signal 63, 65, 68 Row selection line 67, 70 Reset signal 76 Mask signal generation circuit 77 Addition circuit 78 Dummy output

Claims (6)

複数の光電変換素子が半導体基板上に二次元アレイ状に配列形成される共に、隣接する2つの前記光電変換素子をペア画素とし該ペア画素を1単位としてカラーフィルタがベイヤ配列され、該ペア画素毎に前記半導体基板にMOSトランジスタ回路でなる信号読出回路が形成される撮像素子と、
前記撮像素子に付設され該撮像素子の前記信号読出回路から出力される撮像画像信号を処理する信号処理回路と、
前記ペア画素を構成する2つの前記光電変換素子の各検出電荷に応じた撮像画像信号を個別に前記信号読出回路で読み出し前記信号処理回路で信号加算させる第1画素加算駆動モードと、前記ペア画素の2つの前記光電変換素子の各検出電荷を混合し、該混合した電荷量に応じた撮像画像信号を前記信号読出回路で読み出す第2画素加算駆動モードとを、前記撮像素子で被写体画像を撮影するときの撮影状態に応じて切り換える撮像素子駆動手段とを備え、
前記光電変換素子が形成された前記撮像素子の受光面を複数ブロックに領域分割し、各分割ブロック毎に、前記撮像素子駆動手段は前記第1画素加算駆動モードと前記第2画素加算駆動モードとを切り換え、
前記第1画素加算駆動モードと前記第2画素加算駆動モードとが混在した状態で同一行の前記ペア画素から前記信号読出回路が前記撮像画像信号を読み出すとき、前記第2画素加算駆動モードによる前記撮像素子の出力タイミングのうち、前記第1画素加算駆動モードで出力される前記ペア画素のうちの最初に読み出される撮像画像信号の出力タイミングと同じ位置にダミー信号を出力させ、該ダミー信号と前記混合した電荷量に応じた撮像画像信号とを前記信号処理回路で信号加算し、該信号処理回路による信号処理を、前記第1画素加算駆動モードにより前記撮像素子から出力された信号の信号加算処理と同じ処理とした撮像装置。
A plurality of photoelectric conversion elements are formed in a two-dimensional array on a semiconductor substrate, and two adjacent photoelectric conversion elements are used as a pair pixel, and a color filter is Bayer arrayed using the pair of pixels as a unit. An image sensor in which a signal readout circuit composed of a MOS transistor circuit is formed on the semiconductor substrate every time,
A signal processing circuit which is attached to the image sensor and processes a captured image signal output from the signal readout circuit of the image sensor;
A first pixel addition drive mode in which captured image signals corresponding to the detected charges of the two photoelectric conversion elements constituting the pair pixel are individually read out by the signal readout circuit and added by the signal processing circuit; and the pair pixel The detection charges of the two photoelectric conversion elements are mixed, and a second pixel addition drive mode in which a captured image signal corresponding to the mixed charge amount is read by the signal readout circuit, and a subject image is captured by the imaging element and an imaging element driving means for switching in accordance with the shooting state at the time of,
The light receiving surface of the imaging element on which the photoelectric conversion element is formed is divided into a plurality of blocks, and the imaging element driving means is configured to perform the first pixel addition driving mode and the second pixel addition driving mode for each divided block. Switch
When the signal readout circuit reads the captured image signal from the paired pixels in the same row in a state where the first pixel addition drive mode and the second pixel addition drive mode coexist, the second pixel addition drive mode Among the output timings of the image sensor, a dummy signal is output at the same position as the output timing of the captured image signal read out first among the pair of pixels output in the first pixel addition drive mode, and the dummy signal and the The captured image signal corresponding to the mixed charge amount is signal-added by the signal processing circuit, and the signal processing by the signal processing circuit is added to the signal output from the image sensor in the first pixel addition drive mode. Imaging device with the same processing .
請求項1に記載の撮像装置であって、奇数行の光電変換素子行が偶数行の光電変換素子行に対して1/2ピッチづつずらして形成される撮像装置。   2. The imaging apparatus according to claim 1, wherein odd-numbered photoelectric conversion element rows are formed so as to be shifted by ½ pitch with respect to even-numbered photoelectric conversion element rows. 請求項1又は請求項2に記載の撮像装置であって、前記第1画素加算駆動モードと前記第2画素加算駆動モードとの切換を判断する前記撮影状態は、前記ペア画素の一方の前記光電変換素子が検出した電荷量が第1閾値以上であるか否かで判断する撮像装置。   3. The imaging device according to claim 1, wherein the photographing state in which switching between the first pixel addition drive mode and the second pixel addition drive mode is determined is the photoelectric of one of the paired pixels. An imaging apparatus that determines whether or not the amount of charge detected by a conversion element is equal to or greater than a first threshold value. 複数の光電変換素子が半導体基板上に二次元アレイ状に配列形成される共に、隣接する2つの前記光電変換素子をペア画素とし該ペア画素を1単位としてカラーフィルタがベイヤ配列され、該ペア画素毎に前記半導体基板にMOSトランジスタ回路でなる信号読出回路が形成される撮像素子と、
前記撮像素子に付設され該撮像素子の前記信号読出回路から出力される撮像画像信号を処理する信号処理回路と
を備える撮像装置の画素加算方法であって、
前記ペア画素を構成する2つの前記光電変換素子の各検出電荷に応じた撮像画像信号を個別に前記信号読出回路で読み出し前記信号処理回路で信号加算させる第1画素加算駆動モードと、前記ペア画素の2つの前記光電変換素子の各検出電荷を混合し、該混合した電荷量に応じた撮像画像信号を前記信号読出回路で読み出す第2画素加算駆動モードとを、前記撮像素子で被写体画像を撮影するときの撮影状態に応じて切り換える駆動ステップを備え、
前記駆動ステップでは、前記光電変換素子が形成された前記撮像素子の受光面を複数ブロックに領域分割し、各分割ブロック毎に前記第1画素加算駆動モードと前記第2画素加算駆動モードとを切り換え、
前記第1画素加算駆動モードと前記第2画素加算駆動モードとが混在した状態で同一行の前記ペア画素から前記信号読出回路が前記撮像画像信号を読み出すとき、前記第2画素加算駆動モードによる前記撮像素子の出力タイミングのうち、前記第1画素加算駆動モードで出力される前記ペア画素のうちの最初に読み出される撮像画像信号の出力タイミングと同じ位置にダミー信号を出力させ、該ダミー信号と前記混合した電荷量に応じた撮像画像信号とを前記信号処理回路で信号加算し、該信号処理回路による信号処理を、前記第1画素加算駆動モードにより前記撮像素子から出力された信号の信号加算処理と同じ処理とした撮像装置の画素加算方法。
A plurality of photoelectric conversion elements are formed in a two-dimensional array on a semiconductor substrate, and two adjacent photoelectric conversion elements are used as a pair pixel, and a color filter is Bayer arrayed using the pair of pixels as a unit. An image sensor in which a signal readout circuit composed of a MOS transistor circuit is formed on the semiconductor substrate every time,
A pixel addition method for an imaging device, comprising: a signal processing circuit that is attached to the imaging device and processes a captured image signal output from the signal readout circuit of the imaging device,
A first pixel addition drive mode in which captured image signals corresponding to the detected charges of the two photoelectric conversion elements constituting the pair pixel are individually read out by the signal readout circuit and added by the signal processing circuit; and the pair pixel The detection charges of the two photoelectric conversion elements are mixed, and a second pixel addition drive mode in which a captured image signal corresponding to the mixed charge amount is read by the signal readout circuit, and a subject image is captured by the imaging element A drive step for switching according to the shooting state when
In the driving step, the light receiving surface of the imaging element on which the photoelectric conversion element is formed is divided into a plurality of blocks, and the first pixel addition driving mode and the second pixel addition driving mode are switched for each divided block. ,
When the signal readout circuit reads the captured image signal from the paired pixels in the same row in a state where the first pixel addition drive mode and the second pixel addition drive mode coexist, the second pixel addition drive mode Among the output timings of the image sensor, a dummy signal is output at the same position as the output timing of the captured image signal read out first among the pair of pixels output in the first pixel addition drive mode, and the dummy signal and the The captured image signal corresponding to the mixed charge amount is signal-added by the signal processing circuit, and the signal processing by the signal processing circuit is added to the signal output from the image sensor in the first pixel addition drive mode. The pixel addition method of the imaging device, which is the same processing as in FIG .
請求項に記載の撮像装置の画素加算方法であって、奇数行の光電変換素子行が偶数行の光電変換素子行に対して1/2ピッチづつずらして形成される撮像装置の画素加算方法。 5. The pixel addition method for an image pickup apparatus according to claim 4 , wherein odd-numbered photoelectric conversion element rows are formed by being shifted by 1/2 pitch with respect to even-numbered photoelectric conversion element rows. . 請求項又は請求項に記載の撮像装置の画素加算方法であって、前記第1画素加算駆動モードと前記第2画素加算駆動モードとの切換を判断する前記撮影状態は、前記ペア画素の一方の前記光電変換素子が検出した電荷量が第1閾値以上であるか否かで判断する撮像装置の画素加算方法。 A pixel addition method of an imaging apparatus according to claim 4 or claim 5, wherein the imaging condition for determining the switching between the first pixel addition driving mode and the second pixel addition driving mode, the pair of pixels A pixel addition method for an imaging apparatus that determines whether the amount of charge detected by one of the photoelectric conversion elements is equal to or greater than a first threshold value.
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