ES546600A0 - Disposicion de circuito para sincronizar la fase de una se- nal de frecuencia dividida - Google Patents

Disposicion de circuito para sincronizar la fase de una se- nal de frecuencia dividida

Info

Publication number
ES546600A0
ES546600A0 ES546600A ES546600A ES546600A0 ES 546600 A0 ES546600 A0 ES 546600A0 ES 546600 A ES546600 A ES 546600A ES 546600 A ES546600 A ES 546600A ES 546600 A0 ES546600 A0 ES 546600A0
Authority
ES
Spain
Prior art keywords
synchronize
phase
frequency signal
divided frequency
circuit provision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES546600A
Other languages
English (en)
Other versions
ES8705721A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of ES546600A0 publication Critical patent/ES546600A0/es
Publication of ES8705721A1 publication Critical patent/ES8705721A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)
ES546600A 1984-09-03 1985-08-30 Disposicion de circuito para sincronizar la fase de una se- nal de frecuencia dividida Expired ES8705721A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843432313 DE3432313A1 (de) 1984-09-03 1984-09-03 Schaltungsanordnung zum synchronisieren eines signals

Publications (2)

Publication Number Publication Date
ES546600A0 true ES546600A0 (es) 1987-05-01
ES8705721A1 ES8705721A1 (es) 1987-05-01

Family

ID=6244511

Family Applications (1)

Application Number Title Priority Date Filing Date
ES546600A Expired ES8705721A1 (es) 1984-09-03 1985-08-30 Disposicion de circuito para sincronizar la fase de una se- nal de frecuencia dividida

Country Status (6)

Country Link
US (1) US4672447A (es)
EP (1) EP0174049A3 (es)
JP (1) JPS6171722A (es)
KR (1) KR860002905A (es)
DE (1) DE3432313A1 (es)
ES (1) ES8705721A1 (es)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0202015B1 (en) * 1985-04-12 1992-08-19 Tektronix, Inc. Digital phase-locked loops
JPS6269776A (ja) * 1985-09-20 1987-03-31 Nec Corp Ｐｌｌ装置
US4686560A (en) * 1986-05-30 1987-08-11 Rca Corporation Phase locked loop system including analog and digital components
EP0285350B1 (en) * 1987-03-31 1994-02-09 RCA Thomson Licensing Corporation Television receiver having skew corrected clock
FR2623675A1 (fr) * 1987-11-25 1989-05-26 Dassault Electronique Dispositif de synchronisation d'une horloge par rapport a un signal numerique incident, notamment a haut debit
US4847869A (en) * 1987-12-04 1989-07-11 Motorla, Inc. Rapid reference acquisition and phase error compensation for radio transmission of data
US4996596A (en) * 1988-09-02 1991-02-26 Sanyo Electric Co., Ltd. Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization
US4856029A (en) * 1988-10-11 1989-08-08 Eastman Kodak Company Technique for processing a digital signal having zero overhead sync
US4929918A (en) * 1989-06-07 1990-05-29 International Business Machines Corporation Setting and dynamically adjusting VCO free-running frequency at system level
DE3935453A1 (de) * 1989-10-25 1991-05-02 Philips Patentverwaltung Digitale schaltungsanordnung zur verarbeitung eines analogen fernsehsignals mit einem unverkoppelten systemtakt
JP2846002B2 (ja) * 1989-11-22 1999-01-13 株式会社日立製作所 伝送装置
US5155746A (en) * 1990-01-08 1992-10-13 Reliance Comm/Tec Corporation Clock synchronization scheme for digital transmission
US5235622A (en) * 1990-06-26 1993-08-10 Nec Corporation Clock recovery circuit with open-loop phase estimator and wideband phase tracking loop
US5140278A (en) * 1991-03-11 1992-08-18 California Institute Of Technology Phase-locked loop FM demodulator
JP3134426B2 (ja) * 1991-11-29 2001-02-13 日本電気株式会社 シンボル同期回路
FR2685584B1 (fr) * 1991-12-18 1994-03-25 Philips Electronique Grand Publi Dispositif generateur de signal de synchronisation.
US5159292A (en) * 1992-02-25 1992-10-27 Thomson Consumer Electronics, Inc. Adaptive phase locked loop
JPH05335962A (ja) * 1992-05-28 1993-12-17 Sharp Corp 復調装置の位相調整回路
US5388127A (en) * 1993-02-09 1995-02-07 Hitachi America, Ltd. Digital timing recovery circuit
US5835544A (en) * 1993-12-24 1998-11-10 Sony Corporation Clock signal reproduction circuit and data reproduction circuit
JPH0818817A (ja) * 1994-06-30 1996-01-19 Mitsubishi Denki Semiconductor Software Kk 水平同期信号生成回路
US5646968A (en) * 1995-11-17 1997-07-08 Analog Devices, Inc. Dynamic phase selector phase locked loop circuit
US6125158A (en) * 1997-12-23 2000-09-26 Nortel Networks Corporation Phase locked loop and multi-stage phase comparator
JP2000078210A (ja) * 1998-08-28 2000-03-14 Aisin Seiki Co Ltd Ａｓｋ変調回路
US6445423B1 (en) * 1999-07-09 2002-09-03 Thomson Licensing S.A. Controlled oscillator in a digital symbol timing recovery network
US6993105B1 (en) 2000-05-09 2006-01-31 Cypress Semiconductor Corp. Linearized digital phase-locked loop
US6711226B1 (en) 2000-05-12 2004-03-23 Cypress Semiconductor Corp. Linearized digital phase-locked loop
US6535023B1 (en) 2000-05-12 2003-03-18 Cypress Semiconductor Corp. Linearized digital phase-locked loop method
US6366145B1 (en) * 2000-05-12 2002-04-02 Cypress Semiconductor Corp. Linearized digital phase-locked loop
US6950484B1 (en) 2000-05-12 2005-09-27 Cypress Semiconductor Corp. Linearized digital phase-locked loop method
JP4289855B2 (ja) * 2002-09-20 2009-07-01 京セラ株式会社 無線基地装置、参照信号割当方法および参照信号割当プログラム
US7405769B2 (en) * 2004-02-09 2008-07-29 Broadcom Corporation Method and system for 3D comb synchronization and alignment of standard and non-standard video signals
KR101039006B1 (ko) * 2004-06-21 2011-06-07 삼성전자주식회사 아날로그 복합 영상신호의 동기분리장치 및 그 분리방법
US7826581B1 (en) 2004-10-05 2010-11-02 Cypress Semiconductor Corporation Linearized digital phase-locked loop method for maintaining end of packet time linearity
US20060140320A1 (en) * 2004-12-23 2006-06-29 Jensen Richard S Mechanism to adjust a clock signal based on embedded clock information
US20060291082A1 (en) * 2005-06-23 2006-12-28 Steve Bounds Extending lock-in range of a PLL or DLL
US7558275B2 (en) * 2005-09-13 2009-07-07 Sony Corporation System and method for clock replication using reference clock
JP4356946B2 (ja) 2006-03-31 2009-11-04 日本電波工業株式会社 Ｐｌｌ装置
JP2008182314A (ja) * 2007-01-23 2008-08-07 Matsushita Electric Ind Co Ltd 位相調整装置およびその関連技術
JP5098042B2 (ja) * 2008-02-13 2012-12-12 株式会社ワコム 位置検出装置及び位置検出方法
US7930121B2 (en) * 2008-07-03 2011-04-19 Texas Instrument Incorporated Method and apparatus for synchronizing time stamps
US20120033772A1 (en) * 2010-08-08 2012-02-09 Freescale Semiconductor, Inc Synchroniser circuit and method
JP5926371B2 (ja) * 2011-04-26 2016-05-25 テレフオンアクチーボラゲット エルエム エリクソン（パブル） 基地局同期

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL169811C (nl) * 1975-10-03 1982-08-16 Philips Nv Beeldregelsynchronisatieschakeling, alsmede televisieontvanger daarvan voorzien.
GB1519933A (en) * 1977-01-24 1978-08-02 Philips Electronic Associated Digital phase comparison apparatus
NL7714033A (nl) * 1977-12-19 1979-06-21 Philips Nv Televisie-ontvanger met een lijnsynchroniseer- schakeling.
FR2474794A1 (fr) * 1980-01-25 1981-07-31 Labo Electronique Physique Circuit de correction des ecarts de phase entre les signaux de commande de balayage et les signaux de synchronisation lignes dans un recepteur de television
NL8005054A (nl) * 1980-09-08 1982-04-01 Philips Nv Schakeling voor het opwekken van een periodiek zaagtandvormig signaal.
JPS5797251A (en) * 1980-12-09 1982-06-16 Fujitsu Ltd High speed phase lock system for digital phase locking circuit
US4458214A (en) * 1981-09-28 1984-07-03 The Bendix Corporation Fast sampling phase locked loop frequency synthesizer
US4535358A (en) * 1982-04-13 1985-08-13 U.S. Philips Corporation Line synchronizing circuit for a picture display devices and picture display device comprising such a circuit
US4574307A (en) * 1982-09-14 1986-03-04 U.S. Philips Corporation Line synchronizing circuit for a picture display device

Also Published As

Publication number Publication date
EP0174049A3 (de) 1988-05-18
ES8705721A1 (es) 1987-05-01
DE3432313A1 (de) 1986-03-13
KR860002905A (ko) 1986-04-30
JPS6171722A (ja) 1986-04-12
EP0174049A2 (de) 1986-03-12
US4672447A (en) 1987-06-09

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