ES415871A1 - Un metodo para formar un sustrato para pastillas de circui-tos integrados. - Google Patents
Un metodo para formar un sustrato para pastillas de circui-tos integrados.Info
- Publication number
- ES415871A1 ES415871A1 ES415871A ES415871A ES415871A1 ES 415871 A1 ES415871 A1 ES 415871A1 ES 415871 A ES415871 A ES 415871A ES 415871 A ES415871 A ES 415871A ES 415871 A1 ES415871 A1 ES 415871A1
- Authority
- ES
- Spain
- Prior art keywords
- thin film
- metallized
- interconnect design
- integrated circuit
- bonding force
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26284872A | 1972-06-14 | 1972-06-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES415871A1 true ES415871A1 (es) | 1976-02-01 |
Family
ID=22999323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES415871A Expired ES415871A1 (es) | 1972-06-14 | 1973-06-13 | Un metodo para formar un sustrato para pastillas de circui-tos integrados. |
Country Status (9)
Country | Link |
---|---|
JP (1) | JPS4944673A (es) |
AU (1) | AU467287B2 (es) |
CA (1) | CA974664A (es) |
CH (1) | CH557128A (es) |
ES (1) | ES415871A1 (es) |
FR (1) | FR2196570B1 (es) |
GB (1) | GB1416205A (es) |
IT (1) | IT981607B (es) |
SE (1) | SE401767B (es) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1414836A (fr) * | 1963-08-08 | 1965-10-22 | Ibm | Composants fonctionnels |
US3484534A (en) * | 1966-07-29 | 1969-12-16 | Texas Instruments Inc | Multilead package for a multilead electrical device |
FR1534329A (fr) * | 1966-08-16 | 1968-07-26 | Signetics Corp | Procédé de montage de circuits intégrés |
-
1973
- 1973-03-26 IT IT2209373A patent/IT981607B/it active
- 1973-04-19 FR FR7315241A patent/FR2196570B1/fr not_active Expired
- 1973-05-04 SE SE7306255A patent/SE401767B/xx unknown
- 1973-05-15 CA CA171,631A patent/CA974664A/en not_active Expired
- 1973-05-18 GB GB2371473A patent/GB1416205A/en not_active Expired
- 1973-05-30 CH CH778473A patent/CH557128A/xx not_active IP Right Cessation
- 1973-06-01 JP JP6098473A patent/JPS4944673A/ja active Pending
- 1973-06-13 ES ES415871A patent/ES415871A1/es not_active Expired
- 1973-06-14 AU AU56950/73A patent/AU467287B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS4944673A (es) | 1974-04-26 |
FR2196570A1 (es) | 1974-03-15 |
CH557128A (de) | 1974-12-13 |
AU5695073A (en) | 1974-12-19 |
FR2196570B1 (es) | 1976-11-12 |
IT981607B (it) | 1974-10-10 |
CA974664A (en) | 1975-09-16 |
GB1416205A (en) | 1975-12-03 |
DE2329052A1 (de) | 1973-12-20 |
SE401767B (sv) | 1978-05-22 |
DE2329052B2 (de) | 1977-02-17 |
AU467287B2 (en) | 1975-11-27 |
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