ES374314A1 - A disposition of bistable circuit, main-subordinated, transistorized. (Machine-translation by Google Translate, not legally binding) - Google Patents

A disposition of bistable circuit, main-subordinated, transistorized. (Machine-translation by Google Translate, not legally binding)

Info

Publication number
ES374314A1
ES374314A1 ES374314A ES374314A ES374314A1 ES 374314 A1 ES374314 A1 ES 374314A1 ES 374314 A ES374314 A ES 374314A ES 374314 A ES374314 A ES 374314A ES 374314 A1 ES374314 A1 ES 374314A1
Authority
ES
Spain
Prior art keywords
flip
flop
main
translation
transistorized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES374314A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL6817658A external-priority patent/NL6817658A/xx
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of ES374314A1 publication Critical patent/ES374314A1/en
Expired legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

A bistable, master-slave, transistorized circuit arrangement, including a first gate circuit, which is controlled by clock signals and by the output of the slave flip flop and is connected to the main flip flop, and a second gate circuit that is controlled by clock signals and by the output of the main flip-flop, and is connected to the slave float, characterized in that the gate circuit connected to the first flip-flop comprises two partial gate circuits, each comprising the series connection of the gate paths. Main current of a transistor controlled by the clock signal and a transistor controlled by the output signal of the second flip-flop, while the gate circuit connected to this second flip-flop comprises two partial gate circuits, each comprising the parallel connection of the main current paths of a transistor controlled by the signal of clock and a transistor controlled by the output signal of the flip-flop. (Machine-translation by Google Translate, not legally binding)
ES374314A 1968-12-10 1969-12-06 A disposition of bistable circuit, main-subordinated, transistorized. (Machine-translation by Google Translate, not legally binding) Expired ES374314A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL6817658A NL6817658A (en) 1968-12-10 1968-12-10
NL6914950A NL6914950A (en) 1968-12-10 1969-10-03

Publications (1)

Publication Number Publication Date
ES374314A1 true ES374314A1 (en) 1971-12-16

Family

ID=26644375

Family Applications (1)

Application Number Title Priority Date Filing Date
ES374314A Expired ES374314A1 (en) 1968-12-10 1969-12-06 A disposition of bistable circuit, main-subordinated, transistorized. (Machine-translation by Google Translate, not legally binding)

Country Status (1)

Country Link
ES (1) ES374314A1 (en)

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