ES345061A2 - Analogue-to-Digital Multiplex Coder - Google Patents

Abstract

Specification 1,100,357 is modified in that the coding cycle is divided into two halves- during the first half-cycle m/2 analogue input signals on independent lines are digitized whilst input signals digitized during the proceeding half cycle are transmitted to a utilization circuit and during the second half cycle a further m/2 analogue input signals on different lines are digitized while the previously digitized signals are transmitted. In the embodiment described in which m = 32, comparators M16- M31 (Fig. 3) are enabled during the first half cycle by the output C10 of the most significant bit of a binary counter CN so that when the analogue inputs N16-N31 coincide with the output from a sawtooth generator FG, the count in the seven least significant bit positions of counter CN is entered into a matrix memory MR2 under the control of gates P4 enabled by the most significant bit. At the same time the matrix memory MR1 is read out, signals V16-V31 from a decoder D1 receiving the five most significant bits of counter CM being applied to the rows and signals t 1 -t 7 from a decoder D2 receiving the three least significant bits of the counter being applied to the columns. During the next half cycle signals V0-V15 sequentially enable the rows of matrix memory MR2 for read out whilst the digitized values of analogue inputs on lines N0-N15 are stored in memory MR1. The sawtooth wave generator is reset by coincidence of output t 7 of decoder D2 and either signal V15 or V31 from decoder D1, i.e. every half cycle. One of the analogue input leads may be used to apply a reference signal, the slope of the sawtooth signal Z being modified if the signal is incorrectly digitized. The sawtooth signal may be replaced by a staircase signal.