ES2655503T3 - Gestión remota de pruebas de circuitos lógicos digitales - Google Patents
Gestión remota de pruebas de circuitos lógicos digitales Download PDFInfo
- Publication number
- ES2655503T3 ES2655503T3 ES14706138.6T ES14706138T ES2655503T3 ES 2655503 T3 ES2655503 T3 ES 2655503T3 ES 14706138 T ES14706138 T ES 14706138T ES 2655503 T3 ES2655503 T3 ES 2655503T3
- Authority
- ES
- Spain
- Prior art keywords
- test
- electronic device
- logic circuit
- digital logic
- signature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 586
- 238000000034 method Methods 0.000 claims description 49
- 230000004044 response Effects 0.000 claims description 48
- 238000004590 computer program Methods 0.000 claims description 16
- 230000005540 biological transmission Effects 0.000 claims description 14
- 238000013461 design Methods 0.000 claims description 13
- 238000010998 test method Methods 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 12
- 238000005056 compaction Methods 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 description 33
- 230000008901 benefit Effects 0.000 description 7
- 238000012544 monitoring process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000008000 CHES buffer Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- ZXQYGBMAQZUVMI-GCMPRSNUSA-N gamma-cyhalothrin Chemical compound CC1(C)[C@@H](\C=C(/Cl)C(F)(F)F)[C@H]1C(=O)O[C@H](C#N)C1=CC=CC(OC=2C=CC=CC=2)=C1 ZXQYGBMAQZUVMI-GCMPRSNUSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004092 self-diagnosis Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/SE2014/050145 WO2015119540A1 (en) | 2014-02-05 | 2014-02-05 | Remote test management of digital logic circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2655503T3 true ES2655503T3 (es) | 2018-02-20 |
Family
ID=50156877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES14706138.6T Active ES2655503T3 (es) | 2014-02-05 | 2014-02-05 | Gestión remota de pruebas de circuitos lógicos digitales |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9952278B2 (https=) |
| EP (1) | EP3102957B1 (https=) |
| BR (1) | BR112016016518B1 (https=) |
| ES (1) | ES2655503T3 (https=) |
| PL (1) | PL3102957T3 (https=) |
| WO (1) | WO2015119540A1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9829536B2 (en) * | 2016-02-03 | 2017-11-28 | Nvidia Corporation | Performing on-chip partial good die identification |
| DE102019201487A1 (de) * | 2019-02-06 | 2020-08-06 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Integritätsprüfung eines Künstlichen-Intelligenz-Moduls eines Roboters und Verfahren sowie System zur serverseitigen Integritätsprüfung |
| US12613999B2 (en) * | 2019-06-25 | 2026-04-28 | International Business Machines Corporation | Detecting electronic system modification |
| US11568046B2 (en) * | 2019-07-01 | 2023-01-31 | University Of Florida Research Foundation, Inc. | Trigger activation by repeated maximal clique sampling |
| JP7410476B2 (ja) * | 2020-06-25 | 2024-01-10 | 東芝情報システム株式会社 | ハードウエアトロイ検出方法、ハードウエアトロイ検出装置及びハードウエアトロイ検出用プログラム |
| IT202100007856A1 (it) * | 2021-03-30 | 2022-09-30 | St Microelectronics Srl | Architettura di test per circuiti elettronici, dispositivo e procedimento corrispondenti |
| US11574695B1 (en) * | 2021-07-29 | 2023-02-07 | International Business Machines Corporation | Logic built-in self-test of an electronic circuit |
| CN114048520B (zh) * | 2022-01-11 | 2022-04-08 | 沐曦集成电路(上海)有限公司 | 跨芯片访问控制的检测系统 |
| US20240264231A1 (en) * | 2023-02-06 | 2024-08-08 | Intel Corporation | Techniques for infield testing of cryptographic circuitry |
| CN115856587A (zh) * | 2023-02-21 | 2023-03-28 | 成都天成电科科技有限公司 | 一种芯片测试的方法、装置、存储介质及电子设备 |
| US20250306101A1 (en) * | 2024-03-28 | 2025-10-02 | Intel Corporation | Secure built-in self-test (bist) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002511701A (ja) * | 1998-04-13 | 2002-04-16 | エイディシィ・テレコミュニケーションズ・インコーポレイテッド | 通信回線ネットワークを交差接続するためのアクセス且つ作業モニタリングシステム及び方法 |
| US7181663B2 (en) * | 2004-03-01 | 2007-02-20 | Verigy Pte, Ltd. | Wireless no-touch testing of integrated circuits |
| US7395473B2 (en) | 2004-12-10 | 2008-07-01 | Wu-Tung Cheng | Removing the effects of unknown test values from compacted test responses |
| US7900112B2 (en) * | 2008-07-15 | 2011-03-01 | International Business Machines Corporation | System and method for digital logic testing |
| US9081063B2 (en) * | 2010-11-22 | 2015-07-14 | Texas Instruments Incorporated | On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems |
| US20120159274A1 (en) * | 2010-12-21 | 2012-06-21 | Balakrishnan Kedarnath J | Apparatus to facilitate built-in self-test data collection |
-
2014
- 2014-02-05 BR BR112016016518-7A patent/BR112016016518B1/pt not_active IP Right Cessation
- 2014-02-05 WO PCT/SE2014/050145 patent/WO2015119540A1/en not_active Ceased
- 2014-02-05 EP EP14706138.6A patent/EP3102957B1/en active Active
- 2014-02-05 US US15/114,472 patent/US9952278B2/en active Active
- 2014-02-05 PL PL14706138T patent/PL3102957T3/pl unknown
- 2014-02-05 ES ES14706138.6T patent/ES2655503T3/es active Active
Also Published As
| Publication number | Publication date |
|---|---|
| BR112016016518A2 (https=) | 2017-08-08 |
| WO2015119540A1 (en) | 2015-08-13 |
| EP3102957B1 (en) | 2017-11-01 |
| EP3102957A1 (en) | 2016-12-14 |
| US9952278B2 (en) | 2018-04-24 |
| PL3102957T3 (pl) | 2018-04-30 |
| BR112016016518B1 (pt) | 2022-01-18 |
| US20160349314A1 (en) | 2016-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ES2655503T3 (es) | Gestión remota de pruebas de circuitos lógicos digitales | |
| US11880468B2 (en) | Autonomous, self-authenticating and self-contained secure boot-up system and methods | |
| US8701205B2 (en) | Validation and/or authentication of a device for communication with network | |
| CN102567671B (zh) | 一种fpga配置数据的加密系统及其加密方法 | |
| Das et al. | PUF-based secure test wrapper design for cryptographic SoC testing | |
| Cui et al. | A new PUF based lock and key solution for secure in-field testing of cryptographic chips | |
| TW200935369A (en) | Configurable asic-embedded cryptographic processing engine | |
| US9158499B2 (en) | Cryptographic processing with random number generator checking | |
| US10069635B2 (en) | Methods and systems for achieving system-level counterfeit protection in integrated chips | |
| Muñoz et al. | A test environment for wireless hacking in domestic IoT scenarios | |
| US20160103173A1 (en) | Apparatus and a method for providing an output parameter and a sensor device | |
| US10001524B2 (en) | Semiconductor integrated circuit and test method thereof | |
| WO2015119541A1 (en) | Configurable built-in self-tests of digital logic circuits | |
| Wang et al. | EasiSec: a SoC security coprocessor based on fingerprint–based key management for WSN | |
| JP2016091134A (ja) | 半導体装置、及び半導体装置の信頼性テスト方法 | |
| US20220357394A1 (en) | Reconfigurable jtag architecture for implementation of programmable hardware security features in digital designs | |
| Feller et al. | TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms | |
| Liang et al. | Achilles: A Formal Framework of Leaking Secrets from Signature Schemes via Rowhammer | |
| US20180329714A1 (en) | Method for Operating a System on Chip Comprising a Bootable Processor | |
| EP4485244A1 (en) | Method for protecting against software-based side channel attacks an electronic system comprising a secure processor and an integrated sensor | |
| Santikellur et al. | Hardware Security in the Context of Internet of Things: Challenges and Opportunities | |
| US10635401B2 (en) | Method for optimal arrangement of a random number generator | |
| Blair | Development of a Reference Design for a Cyber-Physical System | |
| Pellicer | Security assessment for automotive controllers using side channel and fault injection attacks | |
| Zadeh et al. | Physically Unclonable Functions for Secure IoT Authentication and Hardware-Anchored AI Model Integrity |