PL3102957T3 - Zdalne zarządzanie testem cyfrowych układów logicznych - Google Patents
Zdalne zarządzanie testem cyfrowych układów logicznychInfo
- Publication number
- PL3102957T3 PL3102957T3 PL14706138T PL14706138T PL3102957T3 PL 3102957 T3 PL3102957 T3 PL 3102957T3 PL 14706138 T PL14706138 T PL 14706138T PL 14706138 T PL14706138 T PL 14706138T PL 3102957 T3 PL3102957 T3 PL 3102957T3
- Authority
- PL
- Poland
- Prior art keywords
- logic circuits
- digital logic
- test management
- remote test
- remote
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/SE2014/050145 WO2015119540A1 (en) | 2014-02-05 | 2014-02-05 | Remote test management of digital logic circuits |
EP14706138.6A EP3102957B1 (en) | 2014-02-05 | 2014-02-05 | Remote test management of digital logic circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
PL3102957T3 true PL3102957T3 (pl) | 2018-04-30 |
Family
ID=50156877
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PL14706138T PL3102957T3 (pl) | 2014-02-05 | 2014-02-05 | Zdalne zarządzanie testem cyfrowych układów logicznych |
Country Status (6)
Country | Link |
---|---|
US (1) | US9952278B2 (pl) |
EP (1) | EP3102957B1 (pl) |
BR (1) | BR112016016518B1 (pl) |
ES (1) | ES2655503T3 (pl) |
PL (1) | PL3102957T3 (pl) |
WO (1) | WO2015119540A1 (pl) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9829536B2 (en) * | 2016-02-03 | 2017-11-28 | Nvidia Corporation | Performing on-chip partial good die identification |
DE102019201487A1 (de) * | 2019-02-06 | 2020-08-06 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Integritätsprüfung eines Künstlichen-Intelligenz-Moduls eines Roboters und Verfahren sowie System zur serverseitigen Integritätsprüfung |
US20200411047A1 (en) * | 2019-06-25 | 2020-12-31 | International Business Machines Corporation | Detecting electronic system modification |
US11568046B2 (en) * | 2019-07-01 | 2023-01-31 | University Of Florida Research Foundation, Inc. | Trigger activation by repeated maximal clique sampling |
IT202100007856A1 (it) * | 2021-03-30 | 2022-09-30 | St Microelectronics Srl | Architettura di test per circuiti elettronici, dispositivo e procedimento corrispondenti |
US11574695B1 (en) * | 2021-07-29 | 2023-02-07 | International Business Machines Corporation | Logic built-in self-test of an electronic circuit |
CN114048520B (zh) * | 2022-01-11 | 2022-04-08 | 沐曦集成电路(上海)有限公司 | 跨芯片访问控制的检测系统 |
CN115856587A (zh) * | 2023-02-21 | 2023-03-28 | 成都天成电科科技有限公司 | 一种芯片测试的方法、装置、存储介质及电子设备 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6453014B1 (en) * | 1998-04-13 | 2002-09-17 | Adc Telecommunications, Inc. | Test access and performance monitoring system and method for cross-connect communication network |
US7181663B2 (en) * | 2004-03-01 | 2007-02-20 | Verigy Pte, Ltd. | Wireless no-touch testing of integrated circuits |
US7395473B2 (en) | 2004-12-10 | 2008-07-01 | Wu-Tung Cheng | Removing the effects of unknown test values from compacted test responses |
US7900112B2 (en) * | 2008-07-15 | 2011-03-01 | International Business Machines Corporation | System and method for digital logic testing |
US9081063B2 (en) * | 2010-11-22 | 2015-07-14 | Texas Instruments Incorporated | On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems |
US20120159274A1 (en) * | 2010-12-21 | 2012-06-21 | Balakrishnan Kedarnath J | Apparatus to facilitate built-in self-test data collection |
-
2014
- 2014-02-05 BR BR112016016518-7A patent/BR112016016518B1/pt active IP Right Grant
- 2014-02-05 WO PCT/SE2014/050145 patent/WO2015119540A1/en active Application Filing
- 2014-02-05 ES ES14706138.6T patent/ES2655503T3/es active Active
- 2014-02-05 PL PL14706138T patent/PL3102957T3/pl unknown
- 2014-02-05 EP EP14706138.6A patent/EP3102957B1/en active Active
- 2014-02-05 US US15/114,472 patent/US9952278B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
BR112016016518A2 (pl) | 2017-08-08 |
WO2015119540A1 (en) | 2015-08-13 |
US20160349314A1 (en) | 2016-12-01 |
EP3102957B1 (en) | 2017-11-01 |
BR112016016518B1 (pt) | 2022-01-18 |
US9952278B2 (en) | 2018-04-24 |
ES2655503T3 (es) | 2018-02-20 |
EP3102957A1 (en) | 2016-12-14 |
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