ES2503590T3 - Control de energía de un dispositivo externo durante el modo de dormir de baja potencia sin intervención de la unidad de procesamiento central - Google Patents

Control de energía de un dispositivo externo durante el modo de dormir de baja potencia sin intervención de la unidad de procesamiento central Download PDF

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Publication number
ES2503590T3
ES2503590T3 ES11703752.3T ES11703752T ES2503590T3 ES 2503590 T3 ES2503590 T3 ES 2503590T3 ES 11703752 T ES11703752 T ES 11703752T ES 2503590 T3 ES2503590 T3 ES 2503590T3
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Spain
Prior art keywords
external device
sleep mode
wake
time
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES11703752.3T
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English (en)
Inventor
Michael Simmons
Michael Catherwood
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Microchip Technology Inc
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Microchip Technology Inc
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Publication date
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Publication of ES2503590T3 publication Critical patent/ES2503590T3/es
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Facsimiles In General (AREA)

Abstract

Un dispositivo digital de circuito integrado operable para determinar el control y el estado de un dispositivo externo con independencia del momento en el que el dispositivo (202) digital está en un modo de dormir de baja potencia, que comprende: un procesador (204) digital que incorpora una entrada de despertar, la entrada de despertar despierta el procesador (204) digital de un modo de dormir a un modo operativo cuando un primer nivel lógico es aplicado a aquél y no despierta el procesador (204) digital cuando un segundo nivel lógico es aplicado a aquél; un temporizador (224) de energización acoplado con un primer nodo (216), en el que el temporizador (224) de energización proporciona una señal de energización del dispositivo externo en el primer nodo (216) durante un primer periodo de tiempo; un temporizador (214) de muestras, en el que el temporizador (214) de muestras provoca que una señal de salida del dispositivo externo recibida en un segundo nodo sea aplicada a la entrada de despertar del procesador (204) durante un segundo periodo de tiempo, en el que durante el segundo periodo de tiempo, la señal de salida del dispositivo externo define si el procesador (204) se despierta al modo operativo o permanece en el modo de dormir.

Description

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Claims (1)

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    imagen2
ES11703752.3T 2010-01-21 2011-01-19 Control de energía de un dispositivo externo durante el modo de dormir de baja potencia sin intervención de la unidad de procesamiento central Active ES2503590T3 (es)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29694710P 2010-01-21 2010-01-21
US296947P 2010-01-21
US12/818,547 US8645729B2 (en) 2010-01-21 2010-06-18 External device power control during low power sleep mode without central processing unit intervention
US818547 2010-06-18
PCT/US2011/021689 WO2011091017A1 (en) 2010-01-21 2011-01-19 External device power control during low power sleep mode without central processing unit intervention

Publications (1)

Publication Number Publication Date
ES2503590T3 true ES2503590T3 (es) 2014-10-07

Family

ID=44278428

Family Applications (1)

Application Number Title Priority Date Filing Date
ES11703752.3T Active ES2503590T3 (es) 2010-01-21 2011-01-19 Control de energía de un dispositivo externo durante el modo de dormir de baja potencia sin intervención de la unidad de procesamiento central

Country Status (7)

Country Link
US (1) US8645729B2 (es)
EP (1) EP2526466B1 (es)
KR (1) KR101771674B1 (es)
CN (1) CN102656541B (es)
ES (1) ES2503590T3 (es)
TW (1) TWI539271B (es)
WO (1) WO2011091017A1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8230247B2 (en) 2011-12-30 2012-07-24 Intel Corporation Transferring architectural functions of a processor to a platform control hub responsive to the processor entering a deep sleep state
KR102050385B1 (ko) * 2012-10-30 2019-11-29 엘지디스플레이 주식회사 터치 센싱 시스템과 그 지연 시간 감소 방법
WO2014209400A1 (en) * 2013-06-28 2014-12-31 Intel Corporation Techniques and system for managing activity in multicomponent platform
EP2829929B1 (de) * 2013-07-24 2019-10-23 VEGA Grieshaber KG Feldgerät mit einem trennbaren Anzeige- und/oder Bedienmodul
US9664571B2 (en) * 2013-12-27 2017-05-30 Microchip Technology Incorporated Digital temperature sensor with integrated timer and burst mode
US10416750B2 (en) 2014-09-26 2019-09-17 Qualcomm Incorporated Algorithm engine for ultra low-power processing of sensor data
US9495000B1 (en) * 2015-04-30 2016-11-15 Qualcomm Technologies International, Ltd. Power management of a wireless device
US9880894B2 (en) * 2015-07-08 2018-01-30 Microsoft Technology Licensing, Llc High availability and energy-efficient watchdog timer
US10249178B1 (en) * 2017-11-16 2019-04-02 Aktiebolaget Skf Condition monitoring sensor system and method for monitoring the condition of a system
CN111400074A (zh) * 2019-01-02 2020-07-10 珠海格力电器股份有限公司 一种模拟看门狗装置及其控制方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11503258A (ja) * 1995-09-19 1999-03-23 マイクロチップ テクノロジー インコーポレイテッド ディジタル的にプログラム可能な閾値を有するマイクロコントローラ起立機能
TW493120B (en) * 2000-02-11 2002-07-01 Rf Link Systems Inc Waking up system and method for universal serial bus of wireless computer input device
US6622178B1 (en) * 2000-07-07 2003-09-16 International Business Machines Corporation Method and apparatus for activating a computer system in response to a stimulus from a universal serial bus peripheral
US6586963B2 (en) * 2001-03-26 2003-07-01 Samsung Electronics Co., Ltd. Integrated circuit devices having power control logic that inhibits internal leakage current loss during sleep mode operation and method of operating same
JP2005144814A (ja) * 2003-11-13 2005-06-09 Sharp Corp 画像形成装置
TWI248568B (en) 2004-05-24 2006-02-01 Avision Inc Power-saving system of computer peripheral apparatus
DE102004028070B3 (de) 2004-06-09 2005-12-01 Fujitsu Siemens Computers Gmbh Verfahren zum Zugriff einer Datenverarbeitungsvorrichtung auf ein angeschlossenes externes Gerät und entsprechend eingerichtete Datenverarbeitungsvorrichtung
US20070260905A1 (en) 2006-05-01 2007-11-08 Integration Associates Inc. Wireless controlled wake up
US20090077404A1 (en) 2007-09-14 2009-03-19 Gainspan, Inc. Method and system of reducing power consumption of system on chip based on analog-to-digital control circuitry
CN101477397A (zh) * 2008-01-03 2009-07-08 佳世达科技股份有限公司 显示器的外接装置控制方法

Also Published As

Publication number Publication date
KR20120135187A (ko) 2012-12-12
US8645729B2 (en) 2014-02-04
CN102656541A (zh) 2012-09-05
US20110179297A1 (en) 2011-07-21
TW201140307A (en) 2011-11-16
EP2526466B1 (en) 2014-07-16
WO2011091017A1 (en) 2011-07-28
KR101771674B1 (ko) 2017-09-05
EP2526466A1 (en) 2012-11-28
TWI539271B (zh) 2016-06-21
CN102656541B (zh) 2016-06-29

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