ES2328503T5 - Electronic filter device for receiving TV signals - Google Patents

Abstract

An electronic filter device for the reception of TV-signals, comprising a plurality of frequency determining elements settable by means of an analog setting voltage, a memory (2) for storing digital values representative of the analog setting voltages and conversion circuitry (11-14) for converting the digital values into the analog setting voltages. The conversion circuitry comprises a first part (11-13) for generating a digitally modulated signal for each digital value, the digitally modulated signal having a modulated characteristic representative of the digital value, and a second part (14) for converting each of the digitally modulated signals into the analog setting voltages.

Description

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DESCRIPTION

Electronic filter device for receiving TV signals Technical Field

The present invention relates to an electronic filter device for receiving TV signals according to the preamble of claim 1.

Previous Technique

In the 1980s, a fixed filter was ordinarily used to filter and combine different aerial signals over a cable. Fixed means that the installer needed to replace the filter with a completely new filter if the frequencies of the channels (or simply the entire application) changed.

In the 1990s, programmable filters appeared on the market, which could be reprogrammed by the installer in place to serve different frequencies or new applications, avoiding the need to replace them with new filters. The filter was suitable for all possible applications at that time, so there was no need to develop, produce and store different versions.

An example of that type of filter is described in GB-A-2272341. To filter the desired TV channels of the incoming signal, the device comprises a plurality of elements that determine the frequency (mainly (variable regulation capsules) that can be set by means of analog setting voltages. To generate these voltages, the values of the voltage stored digitally are converted into analog voltages by means of Digital to Analog Converters (DAC), which are expensive components.To limit the number of DACs, a special algorithm is used in the GB-A-2272341 device: a a smaller amount of DACs generates more analog voltages by multiplexing each DAC output in several "analog memory locations" (which are for example retention and sampling circuits) in a "dynamic memory", in which the analog voltages are stored and passed over the elements that determine the frequency.

The device known from GB-A-2272341 has, however, the disadvantage that, in order to keep the voltages in the dynamic memory at the desired level, a continuous reactivation algorithm is necessary to connect the DAC output at regular time intervals to analog memory locations. This continuous reactivation of analog voltages requires a huge portion of microcontroller resources. This causes the need to oversize the microcontroller, which again increases the cost of the device.

Description of the Invention

An object of the present invention is to provide an electronic filter device for the reception of TV signals with alternative conversion circuits for DAC, whereby the need for an oversized microcontroller can be avoided.

This object is achieved according to the invention with an electronic filter device that shows the technical characteristics of the first claim.

The electronic filter device for receiving TV signals according to the invention comprises a plurality of frequency determining elements that are established by means of an analog setting voltage. The device further comprises a memory in which digital values representative of the analog setting voltages and conversion circuits are stored to convert the digital values into analog setting voltages. The device is characterized in that the conversion circuit comprises a first part to generate a digitally modulated signal for each digital value, the digitally modulated signal having a characteristic representative of the digital value, and a second part to convert each of the digitally modulated signals into analog setting voltages.

The digitally modulated signals, which are generated by the first part of the conversion circuit of the device according to the invention, are digital signals whose binary value changes between '0' and '1' in a certain way, for example according to a regular model, in that the signal carries a characteristic that represents the digital value from which the signal originates and that can be interpreted. The characteristic can be for example a duty cycle, that is, the time in which the signal is '1' or the time in which the signal is '0', divided by the period, or a frequency at which the signal switch between '1' and '0' and in the opposite direction, or any other feature that can be digitally modulated.

In the electronic filter device of the invention, a deflection is used to convert the analog setting voltages from the digital signals. The obvious way would be to use DACs (one for each voltage to be generated), but as mentioned this is undesirable in view of its cost. According to the invention, the digital values are first converted into digitally modulated signals, which are in turn converted to the analog setting voltages. The first part of the conversion circuit adds

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some digital components to the device, but these are generally economical and the digitally generated modulated signals by them are convertible into analog setting voltages by means of components less expensive than DACs, such as for example resistors and capacitors. As a result of the use of the diversion, each of the analog voltages can be generated through its own dedicated part of the conversion circuit, there is no longer a need to share different analog voltages on the same line, as occurs in the prior art device on the output of the DACs, or using a dynamic switch to connect the right voltage to the right storage location in the dynamic memory. This eliminates the need for a reactivation algorithm and an oversized microcontroller.

In addition, since there is no need to share different analog voltages on the same line, as in the prior art device on the output of the DACs, or to use a dynamic switch to connect the right voltage to the storage location Analog right in dynamic memory, these quite expensive components can also be dispensed, which can also involve a reduction in the cost of the device. The elimination of the continuous reactivation of the analog voltages also has the advantage that the voltages no longer show a fluctuation, which is being distributed over a large part of the printed circuit board that is always present on the voltages that need to be reactivated. continually. In this way the need for additional filtration components to eliminate the fluctuation of stresses and prevent a residual of the fluctuation from appearing on the TV image is also avoided, which can also reduce the cost of the device of the invention.

Moreover, since the first part of the conversion circuit can be completely digital, component integration is an option and all or at least some of the components can be integrated into a single chip. This can further reduce the number of separate components and consequently reduce their price further.

In the electronic filter device of the invention, the first part of the conversion circuit comprises a plurality of comparators, one for each digitally modulated signal, to compare one of the digital signals with a counter value, the counter value being supplied by a counter that is provided to count repeatedly through a predetermined range of values comprising all possible digital values. In this invention, each comparator generates a '0' while its comparison condition is not satisfied, and a '1' when its comparison condition is satisfied, or vice versa. Therefore, a digitally modulated signal is generated as defined above with an indicative of the duty cycle of the digital value at the comparator input, and therefore indicative of the analog setting voltage. This invention has the advantage of being a simple and direct solution for generating digitally modulated signals from digital values.

The counter can count forward or backward through its range of values. To obtain the repeated count through the range of values, it can be periodically reset by a device microcontroller or it can work in an endless loop. The comparison condition may be "x less than y", "x equal to or less than y", "x greater than y" or "x equal to or greater than y". Instead of the counter or counters and the comparators, other components can also be used to generate the digitally modulated signals from the digital values.

The counter is preferably common for all comparators, so it is only necessary to generate a counter value. Alternative solutions are that each comparator has its own counter or that the counters be provided for groups of comparators. When the bit width of the digital values stored in the device memory is N, the comparators are at least N bits wide and the counter is provided to repeatedly count between 0 and at least 2N-1 to cover all values digital possible.

The first part of the conversion circuit preferably comprises a common register for storing copies of the digital values stored in memory. This keeps the memory separate from the conversion circuit and unintended changes can be avoided. Registration is preferably common for all comparators, but separate records are also possible for a comparator or groups of comparators. An alternative is that comparators are directly coupled to memory.

In a preferred embodiment of the device of the invention, the first part of the conversion circuit is integrated in a Field Programmable Gate Management (FPGA), a Programmable Logic Device (PLD), a Complex Programmable Logic Device (CPLD), a Circuit Integrated Concrete Application (ASIC), or any other similar programmable integrated circuit known to the person skilled in the art. FPGA is preferred for the reasons that it is the best compromise available between price and ease of integration and because it is becoming widely used in the field.

One or more of the following optional components of the device of the invention can be integrated together with the first part of the conversion circuit within the same chip: a microcontroller, a PC interface, an RF detection circuit and / or interface logic of user. The memory in which the digital values are stored can also be integrated into this chip.

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The second part of the conversion circuit comprises a plurality of integrators, one for each digitally modulated signal, These integrators, which can be conveniently incorporated in the form of RC networks, generating the desired analog setting voltages from the digitally modulated signals . Integrators are preferred for the reasons that they are low complexity and economical.

The memory in which the digital values are stored is preferably a non-volatile memory, such as an EEPROM, so that the device can be reprogrammed in place. To allow reprogramming in place the device comprises a user interface to allow a user to reprogram the digital values.

Brief description of the drawings

The invention will be better explained by means of the following description and the Figures that are added.

Figure 1 shows an electronic filter device of the prior art.

Figure 2 shows a first preferred embodiment of the electronic filter device of the invention.

Figure 3 shows a second preferred embodiment of the electronic filter device of the invention.

Ways to practice the invention

The prior art device of Figure 1 is the one known from GB-A-2272341. It comprises a microcontroller 1, a non-volatile memory (NVM) 2 for storing factory data and adjustments made in the field by the installer, a PC interface 3, for example for higher degrees of wired microprogramming or changing the device settings , a user interface logic 4 with user interface input devices 5 and user interface output devices 6, an RF detection circuit 7 to detect the level of RF necessary for an automatic compensation function, a plurality of DACs 8 for generating analog voltages, a plurality of switches 9 (or dynamic multiplexers), and dynamic memory 10 with "analog storage locations" for storing analog voltages. The analog voltages are supplied by a bank 17 of voltage outputs and are used to establish elements for determining the frequencies of the RF circuit. In Figure 1, the number of DACs is P, the number of dynamic switches is also P and the number of outputs per dynamic switch is Q. A complex dynamic algorithm controlled by the microcontroller is continuously active and synchronizes the operation of the DACs and dynamic switches. In time slot 1, the DACs are generating the analog voltages for output 1 and all dynamic switches are set to output 1. In time slot 2, the DACs are generating the analog voltages for output 2 and all The dynamic switches are set to output 2. This continues until the last analog voltages are generated in the time slot Q and directed to the last outputs. The result is that dynamic memory now contains all analog voltages P * Q at P * Q storage locations, which are connected to the P * Q outputs in bank 17. As dynamic memory is not perfect and there is consumption in the analog voltages, the dynamic algorithm has to reactivate all P * Q values by continuously repeating the actions taken from time slot 1 to time slot Q. It is clear that this complex and non-stop algorithm consumes a large amount of microcontroller resources. Another drawback is the unwanted distribution of high frequency signals, which originate from the complex algorithm, between DACs and dynamic switches. There is no possibility of filtering these unwanted signals outside, as this would completely destroy the complex algorithm, but nonetheless they are present in a large part of the PCB.

In Figure 2, a first possible embodiment of the device of the invention is shown. This embodiment comprises the following components that are similar to those of the prior art device of Figure 1: a microcontroller 1, a non-volatile memory 2 for storing all factory data and all adjustments made in the field by the installer, a PC interface 3, for example higher degrees of wired microprogramming or change of device settings, a user interface logic 4 with user interface input devices 5 and user interface output devices 6, where articles 4 to 6 are used for example to change the settings, to show an automatic matching function, and any other possible functions, and an RF detection circuit 7 to detect the level of RF needed for the automatic matching function. The device of Figure 2 differs from that of Figure 1 in the conversion circuit, which comprises a counter N of 11 bits, a recorder 12 comprising at least M * N bits, M comparators 13 (at least N bits wide ), an integrating bank 14 with M integrators (one for each comparator), and an output bank 17 in which the analog M voltages are presented for use in the RF circuit (not shown) of the device. The integrators 14 can be conveniently applied as RC networks, but other applications are possible. The analog voltages that are generated are used at least for the frequency determined by the elements of the RF circuit (not shown), but can also be used for some other input or output circuits and possibly also other components.

In the embodiment shown in Figure 2, the user interface 4-6 is part of the electronic filter device. Alternatively, the user interface can also be disconnected from the device.

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The counter 11, the register 12 and the comparators 13 form a first part of the conversion circuit that is provided to convert the digital values stored in the memory 2 into digitally modulated signals that have a duty cycle indicative of the digital value and therefore the analog setting value.

The first part of the conversion circuit works as follows. The N-bit counter 11 is counting in an endless loop between 0 and 2N-1 and increments each time by 1 in the clock regime. When it reaches 2N-1, it starts again at 0 in a repetitive procedure without arrests. At the same rate as the clock, this value of the N-bit counter is applied to inputs A, A ', ... of all M comparators 13. Recorder 12 contains at least M * N bits sent once from memory 2 non-volatile by microcontroller 1 after restart or reprogramming of the device, which can be triggered by an installer via user interface 4-6. Therefore, the register 12 stores a copy of the digital values stored in the non-volatile memory 2. The register 12 in turn applies this data to input B, B ', ... of the respective comparator 13. As a result, each comparator 13 has 2 N-bit width signals that it compares to the clock rate. It is assumed that the condition that is considered by each comparator 13 is "A less than or equal to B". The first comparator 13 will then emit a binary '1' as long as the value on input A, that is, the counter value; It is less than or equal to the value on input B, that is, one of the digital values. Once the value on input A becomes greater than the value on input B, the comparator will generate a binary '0'. In this way a digitally modulated signal is generated with a duty cycle that is a representation of the digital value that originates from the NVM 2. Therefore the duty cycle is a digitally modulated feature that is linked to the stored digital value. As an alternative, the comparison condition may also be "A less than B", "A greater than B" or "A greater than or equal to B". Instead of the counter (s) and the comparators, other components can also be used to generate the digitally modulated signals of the digital values.

The integrators 14 form a second part of the conversion circuit and are provided to convert the digitally modulated signals into the analog setting voltages. Instead of the integrators 14, filters can also be used or any other circuit that can establish a relationship between the duty cycle of the digitally modulated signal and the analog voltage.

In the embodiment of Figure 2, the recorder 12 and the counter 11 operate autonomously, without the need for control by the microcontroller 1. Only at discrete moments, such as starting, or after a change of the settings, the microcontroller 1 is directed to register 12. As a result, microcontroller 1 does not need resources to execute a continuous refresh algorithm as in the prior art.

The above description is an example, but surely it is not the only possible solution. Instead of a single counter, a certain number of counters can also be used. Similarly, a certain number of registrars can also be used instead of a single one. In the extreme case, a counter and a recorder are used per comparator, where the counters can operate independently and not synchronized with each other. The number of filter integrators may be equal to the number of comparators, but may also be less. The counter or counters do not need to work in an endless loop; Other modes of operation are possible, such as a periodic reset by the microcontroller.

In an alternative embodiment (not shown), digitally modulated signals are generated by means of frequency converters in voltage. In this embodiment, the NVM can, for example, store a divider ratio of a time regime for each voltage that is generated, whose divider ratio is then used to generate an oscillation signal, in synchronization with the hourly signal. This oscillation signal can be generated by means of a first completely digital part of the conversion circuit. The oscillation signal is then supplied to the frequency converters in voltage, which form a second part of the conversion circuit. In this embodiment the stored divider ratio is therefore also a digital value representative of the analog voltage to be generated. The oscillation signal is a digitally modulated signal as defined above, its frequency being the modulated characteristic that is linked to the stored digital value and therefore with the voltage to be generated. In addition, alternative embodiments are feasible.

As a result of using comparators 13, recorder 12 and counter 11, the need for expansive DACs, and dynamic switches and dynamic memory that consume space are eliminated. In addition, component integration becomes an option. As there is now a completely digital circuit that replaces DACs, the path is open to the integration of most digital circuits. This can be done in a PLD (Programmable Logic Device), a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Management), or an ASlC (Application Specific Integrated Circuit) or other equivalent integrated circuits. There are circuits available such that they have sufficient resources to integrate all the comparators as well as the recorder and the counter, which is what is done in the embodiment of Figure 2. For example, in an embodiment in which 64 electrical voltages of analogue setting, the N-bit counter 11, the register 12 with at least 64 N-bit words and at least 64 comparators 13 can be integrated within a single FPGA to generate these voltages. The number of electrical voltages and consequently the size of the recorder and the number of comparator circuits can of course vary depending on the needs and circumstances.

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When an FPGA is used for integration, different embodiments are possible. In the first embodiment shown in Figure 2, the FPGA 15 is of the volatile type, thus being because a separate NVM 2 is included to store the configuration bits to configure the FPGA 15. This nVm 2 is also the memory in the that the manufacturing data and the digital values representative of the analog setting voltages are stored, but an NVM separated by the configuration bits is also possible. During startup, FPGA 15 configures itself by downloading its NVM program.

In an alternative embodiment shown in Figure 3, FPGA 16 is of the non-volatile type, which means that it has a built-in NVM so that there is no need to store the configuration bits in a separate nVm. In this embodiment, even the rest of the data can be stored within the FPGA 16.

In the embodiment of Figure 3, even more data is integrated into the FPGA 16, ie the logic 4 of the user interface, to which both input and output devices 5, 6 can be connected, either permanently or Detachable mode, microcontroller 1, RF detection circuit 7 and PC interface 3. The digital components can also be integrated into the FPGA. In Figure 3, all digital circuits are integrated, including circuits with analog inputs or outputs that lead to an electronic filter device that can be manufactured at a very low cost.

The advantages of the device of Figures 2 or 3 compared to that of Figure 1 are numerous. As already mentioned, a first benefit is the elimination of the complex reactivation algorithm, which has been replaced by a simpler direct algorithm. Microcontroller 1 is no longer working continuously on the algorithm, the only time the microcontroller needs to coordinate the generation of analog voltages, is the start-up or when the electronic filter device settings are being changed. This can be done by means of a microcontroller 1 with much less resources, therefore much cheaper.

A second advantage is that changes in the design can be made much easier than with the prior art. In the device of Figures 2 and 3, the microcontroller 1 is mainly coupled with the communication triggered by a discontinuous event, such as an installer that changes the settings. In the prior art device of Figure 1 the microcontroller had to organize both the continuous (full algorithm) and the non-continuous procedures (as a change of the settings). When an event occurred and the microcontroller needed, for example, to monitor the input user interface device, the complex algorithm was still running, making the microprogramming wired inside the complex microcontroller and difficult to change. As a result of the elimination of the reactivation algorithm, changes in the product (improvements, updates, new versions, ...) can be introduced more quickly and easily.

A further advantage is the possibility of integration of multiple components, which leads to cheaper designs. This works in two ways: on the one hand the number of components is reduced and on the other hand space is saved. Less occupied space means smaller PCBs, smaller accommodations, ..., cheaper and commercially more attractive products.

Due to the absence of the dynamic switch in the devices of Figures 2 and 3, there is no longer a source that causes interference that may lead to disturbances in the RF signal. In the prior art device of Figure 1, special attention had to be given to this EMC issue, since the dynamic algorithm with its high frequency transitions was distributed over a large part of the PCB, causing it to radiate. In the devices of Figures 2 and 3, the dynamic algorithm responsible for a substantial part of the EMC problems is eliminated and replaced by an algorithm (static) that operates within the FPGA component facilitating the filtering of all undesirable impulses directly at the output of the component. Any radiation is contained within the component and will not substantially influence the RF signal. As an additional advantage (if necessary) the microcontroller 1 (also responsible for a portion of the radiation) can operate at a slower clock frequency reducing the risk of disturbing the radiation.

The devices of Figures 2 and 3 also show increased higher gradability. On the software level, these devices are at least as flexible as the prior art device of Figure 1; New frequency regulations determine elements of the wired filters that can be obtained by changing the established electrical voltages. But in the devices of Figures 2 and 3, the hardware characteristics can be modified; new features can be added, more robust microcontrollers can be installed, greater accuracy can be obtained by increasing the number of bits in the counter, register and comparators, and so on.

A further advantage is a reduced time to generate the manufacturing data in the production stage. The DAC and the dynamic reactivation algorithm of the prior art device of Figure 1 delayed this procedure because a few DACs, through the simultaneous transmission system had to supply a large number of analog voltages. With the devices of Figures 2 and 3, the speed can be increased as all analog voltages can be generated simultaneously. A huge benefit of this increased speed lies in the calibration of the NVM in the production stage. The speed of the test equipment in the production stage is no longer limited by the speed of the DACs and the simultaneous transmission algorithm, being able to reduce the production time and lead to a reduction in production costs.

Reference List

 one.

 Microcontroller

 2.

 Non volatile memory

 3.

 PC interface

 5 4.

 User Interface Logic

 5.

 User interface input devices

 6.

 User interface output devices

 7.

 RF detection circuit

 8.

 DAC

 10 9.

 Dynamic switch

 10.

 Dynamic memory

 eleven.

 N bit counter

 12.

 Recorder (N * M bits)

 13.

 N bit comparator

 15 14.

 Integrating bank

 fifteen.

 FPGA

 16.

 FPGA

 17.

 Analog voltage output bank.

Claims (5)

5 10 fifteen twenty 25 30 1. An electronic filter device for receiving TV signals, comprising an RF circuit having a plurality of frequency determining elements for filtering a plurality of desired TV channels of an incoming signal, each determining element being of the adjustable frequency by means of an analog setting voltage, a memory (2) for storing digital values representative of the values of the analog setting voltages and a conversion circuit (11-14) to convert the digital values into analog setting voltages, characterized in that the conversion circuit comprises: a completely digital first part (11-13) integrated in a single chip, comprising an N-bit counter (11), a recorder (12) comprising at least M * N bits, and M comparators (13), which is at least N bits wide to generate a digitally modulated signal for each digital value, the digitally modulated signal having a modulated characteristic representative of the digital value, the modulated characteristic being a duty cycle that is linked to the stored digital value and, therefore, to the voltage to be generated; and a second part (14) to convert each of the digitally modulated signals into the analog setting voltages, the second part of the conversion circuit comprising an integrating bank (14) with integrators M, one for each digitally modulated signal, implementing the integrators in the form of RC networks provided to generate the desired analog voltages from the digitally modulated signals, and an output bank (17) where the analog setting voltages are presented, so that all analog setting voltages can be generated simultaneously. 2. An electronic filter device according to claim 1, characterized in that the counter (11) is common for a certain number of, or all, the comparators (13). An electronic filter device according to any one of the preceding claims, characterized in that the first part (11-13) of the conversion circuit is integrated in a programmable gate arrangement (15; 16). An electronic filter device according to claim 3, characterized in that the programmable (15; 16) programmable gate arrangement further integrates one or more of the following: a microcontroller (1), a PC interface (3), a circuit ( 7) RF detection, user interface logic (4) and / or memory (2) in which the digital values are stored. An electronic filter device according to any one of the preceding claims, characterized in that the memory (2) is a non-volatile memory and because the device comprises a user interface (5, 6) to allow a user to reprogram the digital values .