KR100658354B1 - Apparatus for automatic frequency estimation - Google Patents

Abstract

An automatic frequency detector is provided to extract a frequency component of a system clock in order to maintain stable and optimum performance over wide frequency range, by controlling a circuit operation adaptively according to a frequency. A high pass filter(101) has a variable time constant by a control signal. A comparator(102) compares an output signal of the high pass filter with a reference signal. A phase detector(103) detects phase difference between an output signal of the comparator and an input signal of the high pass filter. A controller(104) changes the time constant of the high pass filter on the basis of an output signal of the phase detector.

Description

Automatic frequency detector. {Apparatus for automatic frequency estimation}

1 shows an embodiment of an automatic frequency detection apparatus according to the present invention.

Figure 2 shows an automatic frequency detection device further embodies an embodiment of the present invention.

Figure 3 (a) shows the configuration of a typical RC high pass filter.

Figure 3 (b) shows the waveform of the typical RC high pass filter of Figure 3 (a).

FIG. 3 (c) shows an output waveform of a comparator in which the output of the general RC high pass filter of FIG. 3 (a) and a predetermined reference voltage are input.

Figure 4 (a) shows a variable high pass filter according to the present invention.

Figure 4 (b) shows the output waveform of the variable high pass filter of Figure 4 (a) for the control signal and the reset control signal of the controller.

5 shows a variable resistor in a variable high pass filter according to the present invention.

FIG. 6A illustrates waveforms when the phase of the reference signal REF is faster than the phase of the input signal IN in the phase detector of the present invention.

 FIG. 6 (b) shows waveforms when the phase of the reference signal REF is later than the phase of the input signal IN in the phase detector of the present invention.

FIG. 6C shows waveforms when the phase of the reference signal REF and the phase of the input signal IN are the same in the phase detector of the present invention.

FIG. 7 (a) shows waveforms from the input signal of the variable high pass filter to the output signal of the phase comparator when the time constant value of the variable high pass filter is smaller than the half period of the input signal of the variable high pass filter in the present invention. .

Figure 7 (b) shows the waveform from the input signal of the variable high pass filter to the output signal of the phase comparator when the time constant value of the variable high pass filter is greater than the half period of the input signal of the variable high pass filter in the present invention .

FIG. 8 illustrates a part of the automatic frequency detection device according to the present invention in FIG. 2 in detail.

9 is a flowchart illustrating determining an output relationship of a frequency signal according to a control signal in a controller.

In the past, analog circuits were mainly used in electronic systems, but recently, most systems use digital circuits. Most of these digital electronic systems are clock synchronous systems that store the state of the system through memory circuits such as flip-flops, and all operations are mostly synchronized with a clock signal.

In such a clock synchronization system, a clock signal is generally designed to allow a system to operate in a wide frequency range rather than having a fixed frequency, and then a user selects and uses a frequency within an operating frequency range.

However, the system is optimized for any particular frequency range of the operating frequency range, resulting in poor performance.

For example, in the case of a phase locked loop (PLL), a loop bandwidth should be set so as not to affect system stability.

In general, the loop bandwidth of the PLL is designed for the lowest frequency region of the input clock. However, when a high frequency input clock is applied, there is a problem in that performance such as jitter and locking time is degraded.

 An automatic frequency detector according to the present invention provides an apparatus and method for extracting frequency components of a system clock to adaptively control circuit operation according to frequency to maintain stable and optimal performance over a wide frequency range. have.

The automatic frequency detection device according to the present invention comprises a high pass filter having a variable time constant value by a predetermined control signal, a comparator for comparing the output signal of the high pass filter with a predetermined reference signal, the output signal of the comparator and the high band And a phase detector for detecting a phase difference from an input signal of the pass filter and a controller for outputting the control signal for varying the time constant value of the high pass filter based on the output signal of the phase detector. It is a detection device.

Here, the high pass filter is an automatic frequency detection device, characterized in that it comprises a variable resistor and a capacitor controlled by the control signal.

Herein, the variable resistor includes a plurality of resistors and switches, and each switch is controlled by the control signal.

Here, the input signal of the high pass filter input to the phase detector is an automatic frequency detection device characterized in that the inverted.

Here, the automatic frequency detection device further comprises a handshaking circuit between the phase detector and the controller.

Here, the handshaking circuit is an automatic frequency detection device, characterized in that implemented by flip-flop (flip-flop).

Here, the output signal of the high pass filter is an automatic frequency detection device, characterized in that initialized by a predetermined period by the controller.

Here, the predetermined period is an automatic frequency detection device, characterized in that the half period of the frequency of the input signal of the high pass filter.

Here, the input of the high pass filter is an automatic frequency detection device, characterized in that input to the high pass filter via a divider.

Here, the controller outputs the control signal for controlling the time constant and the frequency signal having the detected frequency information based on the output signal of the phase detector, and determines whether the control signal of a predetermined number of consecutive times is constant to determine the frequency signal. Automatic frequency detection device comprising a digital filter to determine the.

Here, when the control signal is constant, the digital filter corresponds to the frequency signal to the control signal, and when the frequency signal is not constant, the frequency signal corresponds to any one of the smallest value or the largest value of the control signal. It is an automatic frequency detection device characterized in that the corresponding.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows an embodiment of an automatic frequency detection apparatus according to the present invention.

In an embodiment of the present invention, the automatic frequency detection device includes a variable high pass filter 101, a comparator 102, a phase detector 103, and a controller 104.

The input clock signal CLKIN of the automatic frequency detection device is input to a variable high pass filter 101. The output signal of the variable high pass filter 101 is input to a comparator 102. The comparator 102 compares the reference signal VREF with the output signal of the high pass filter 102.

The phase detector 103 detects a phase difference between the output signal of the comparator 102 and the input clock signal CLKIN.

The output signal of the phase detector 103 is input to the controller 104, and the controller 104 outputs a control signal for controlling the variable high pass filter 101 and a frequency signal FREQ_OUT corresponding to the detected frequency. .

By inputting the control signal of the controller 104 to the variable high pass filter 101, the automatic frequency detection device according to the present invention can form a feedback loop.

The frequency signal FREQ_OUT has frequency information of the input clock signal CLKIN and provides frequency information of the input clock signal CLKIN to the system.

Figure 2 shows an automatic frequency detection device further embodies an embodiment of the present invention.

As shown in FIG. 2, the frequency detector according to the present invention may include a divider 201, and an input clock signal CLKIN, which is a system clock input to be detected, is connected to an input signal of the divider 201. It can be used as a clock signal of the controller 207.

The input clock signal CLKIN is input to the divider 201 and the controller 207. The output signal refclk of the divider 201 is input to the variable high pass filter 202. The comparator 203 compares the output signal xCH and the reference signal VREF of the variable high pass filter 202.

The phase detector 205 detects the phase difference between the two signals by inputting the output signal hclk of the comparator 203 and the output signal refclk of the divider 201. The output signal refclk of the divider 201 input to the phase detector 205 may input the inverted signal rclk to the phase detector via the inverter 204.

When the inverter 204 is included, the output signal refclk of the divider 201 is input to the inverter 204 to output the inverted signal rclk. The output signal rclk of the inverter 204 and the output signal hclk of the comparator 203 are input to the phase detector 205.

A handshaking circuit 206 may be included between the phase detector 205 and the controller 207.

When the handshaking circuit 206 is included, the output signal of the phase detector 205 is input to the handshaking circuit 206, and the output signal of the handshaking circuit 206 is input to the controller 207.

The controller 207 controls the frequency component of the reset control signal HPF_RST and the input clock signal CLKIN to reset the control signal Zctrl and the variable high pass filter 202 to control the variable high pass filter 202. Output the included frequency signal FREQ_OUT.

Hereinafter, the automatic frequency detection device shown in FIG. 2 will be described in more detail.

3 shows a typical highpass filter and its waveform.

Figure 3 (a) shows the configuration of a typical RC high pass filter.

The RC high pass filter includes a resistor (R) and a capacitor (C), which are connected to ground (GND).

When a step function input having an amplitude of Vswing is applied to the input of the high pass filter composed of the resistor R and the capacitor C, x (t), as shown in FIG. , y (t) can be expressed as shown in [Equation 1], and the waveform is shown in Fig. 3 (b).

As shown in FIG. 3 (b), y (t) has a correlation with RC time constant value determined by R and C values.

Fig. 3 (c) shows the output waveform of the high pass filter in the comparator, the output waveform when y (t) is compared with the predetermined reference voltage VREF, and d (t).

As shown in FIG. 3 (c), the reference voltage VREF is a voltage signal that is 0.367 times that of Vswing. When the output of the comparator has a lower y (t) than the reference voltage VREF, '1' is obtained. If y (t) is higher than VREF), it is assumed to output '0'. The time width when the output waveform of the comparator, d (t) is '0', is equal to the RC value which is the time constant of the high pass filter. Therefore, when the Vswing, R, and C values are known, the rise time of the output waveform of the comparator and d (t) can be predicted.

Figure 4 shows a variable high pass filter 202 and its waveform in the automatic frequency detection device according to the present invention.

4 (a) shows a variable high pass filter 202 according to the present invention.

FIG. 4 (a) is made of a variable resistor (R) so that the resistance value can be changed according to the control signal (Zctrl) of the controller 207 in the RC high pass filter as shown in FIG. 3 (a).

Although the variable high pass filter 202 may be configured to change the value of the capacitor C, or the variable high pass filter 202 itself may be configured using an active element instead of a passive element, the automatic frequency detection device according to the present invention. In the preferred embodiment, the passive element R is used to simplify the configuration of the circuit.

In FIG. 4A, the output terminal xCH of the variable high pass filter 202 is periodically grounded to the ground GND by the reset control signal HPF_RST of the controller 207.

 The input signal refclk of the variable high pass filter 202 is a signal for full-swinging the ground GND and the power supply voltage VDD of the circuit. In addition, the reference voltage of the variable high pass filter 202 is ground (GND) as shown in FIG.

Therefore, when the rising transition of the input signal (refclk) of the variable high pass filter 202, as shown in the output signal of the high pass filter, y (t) of FIG. On the contrary, when the input signal refclk of the variable high pass filter 202 falls, the output signal xCH of the variable high pass filter 202 goes to 0V in the negative direction based on 0V. Ascend transitions.

Since the output signal xCH of the variable high pass filter 202 is input to the comparator 203, when the input signal refclk of the variable high pass filter 202 falls, the maximum '-' is applied to the input of the comparator 203. The voltage signal of VDD 'is applied to damage the device.

Accordingly, in order to prevent the variable high pass filter 202 from operating when the input signal refclk of the variable high pass filter 202 falls, the reset control signal HPF_RST of the controller 207 is applied to the variable high pass. The output signal xCH of the pass filter 202 is prevented from being filtered in the negative direction.

In addition, when the time constant value of the variable high pass filter 202 determined by RC is too large, the output signal hclk of the comparator 203 may have a different frequency from the output signal refclk of the variable high pass filter 202. As a result, in the phase detector 205, a pulse lock in which the output signal rclk of the inverter 204 and the output signal hclk of the comparator 203 are in phase with the harmonic component can be obtained. This can happen.

However, since the reset control signal HPF_RST of the controller 207 is applied to the falling transition of the input signal refclk of the variable high pass filter 202, even if the RC time constant is too large, the variable high pass filter 202 The output signal xCH is forcibly grounded to ground GND and applied to the comparator 203. The comparator 203 outputs the output signal hclk at the same frequency as the output signal refclk of the variable high pass filter 202. Outputs

FIG. 5 illustrates an example in which the variable resistor R of FIG. 4A is implemented.

As shown in FIG. 5, after connecting a resistor string in series, each intermediate node is connected to the ground GND through a switch. As described above, the control of the switch uses the control signal Zctrl of the controller 207.

If the variable resistor R is controlled by an M-bit digital signal, one of the control signals Zctrl of the M-bit controller is selectively turned on.

When the selected switch is turned on and all others are turned off, the resistance value is the sum of the resistance string values to the switch. Therefore, as the switch is turned on to the Least Significant Bit (LSB) of the control signal Zctrl of the controller 207, the time constant of the variable high pass filter 202 is smaller, and the switch is turned to the Most Significant Bit (MSB). The more turned on, the higher the time constant of the variable high pass filter 202 is.

In terms of the linearity of the time constant, the time constant value can be determined non-linearly according to the control signal Zctrl of the controller 207 without having to necessarily have the same resistance value.

As the control signal Zctrl of the controller 207 increases in the number of resistor strings and the number of switches, the type of time constant that the variable high pass filter 202 may have increases, and the resolution of frequency detection also increases.

6 shows an operating waveform of the phase detector 205.

Referring to FIG. 6A, when the phase of the reference signal REF is faster than the input signal IN, a pulse having a width corresponding to the phase difference is output as an 'UP' pulse.

FIG. 6 (b) shows the opposite direction of FIG. 6 (a), and outputs a 'DN' pulse when the phase of the input signal IN is earlier than the phase of the reference signal REF.

FIG. 6C illustrates a case where a phase difference between the reference signal REF and the input signal IN is '0', and pulses 'UP' and 'DN' of the same width are generated.

FIG. 7 illustrates driving waveforms from the input signal refclk of the variable high pass filter 202 to the output pulses "UP" and "DN" pulses of the phase detector 205.

FIG. 7A shows a case where the time constant of the variable high pass filter 202 is smaller than the half period of the input signal refclk of the variable high pass filter 202, and at the rising transition of the output signal hclk of the comparator 203. Phase is faster than the output signal rclk of the inverter 204, the phase detector 205 outputs a 'DN' pulse, and the controller 207 raises the time constant of the variable highpass filter 202 to increase the comparator ( The phase of the output signal hclk of 203 is controlled to be late.

7B is a case where the time constant of the variable high pass filter 202 is larger than the half period of the input signal refclk of the variable high pass filter 202, and the phase of the output signal hclk of the comparator 203 is half. If it is slower than the phase of the output signal rclk of electricity 204, it outputs a 'UP' pulse, and the controller 207 reduces the time constant of the variable high pass filter 202 so that the output signal hclk of the comparator 203 is reduced. Control the phase so that it will come faster.

The negative feedback loop is formed by the control signal Zctrl applied to the variable high pass filter 202. When the negative feedback loop is repeated, the control signal Zctrl of the controller 207 is specified. It converges to the control signal Zctrl. At this time, since the time constant value of the variable high pass filter 202 and the swing width of the input signal refclk of the variable high pass filter 202 are already known according to the control signal Zctrl, the control signal of the controller 207 ( Zctrl) value determines the frequency value.

8 shows a portion 210 of an automatic frequency detection apparatus according to the present invention for explaining the handshaking circuit 206.

In FIG. 8, when the output signal hclk of the comparator 203 is faster than the output signal rclk of the inverter 204, a signal having a pulse width corresponding to a phase difference between both signals (eg, '1'). ) Is printed as 'UP' terminal. At this time, the 'DN' terminal of the phase detector maintains a value of '0'.

On the contrary, when the output signal rclk of the inverter 204 is out of phase with the output signal hclk of the comparator 203, a signal having a pulse width corresponding to a phase difference between both signals (for example, '1' ') Is output through' DN 'terminal, and' UP 'terminal is maintained at' 0 '.

When the input clock signal CLKIN is used as the clock signal of the controller 207, the 'UP' signal and the 'DN' signal of the phase detector 205 are applied to the input clock signal CLKIN, which is a clock signal of the controller 207. It can be a non-synchronized signal.

Accordingly, the automatic frequency detection apparatus according to the present invention may include a handshaking 206 circuit to resolve a mismatch between the signal of the phase detector 205 and the clock signal of the controller 207.

The output signal of the phase detector 205 is input to the handshaking circuit 206, and the output signal of the handshaking circuit 206 is input to the controller 207.

In a preferred embodiment of the present invention, the handshaking circuit 206 is implemented with two D flip-flops 206a and 206b. Since the frequency of the output signal hclk of the comparator 203 and the output signal rclk of the inverter 204 is lower than the input clock signal CLKIN by the frequency division ratio N, the 'UP' and 'DOWN' signals When the 'UP' pulse is applied using the clock signal, the 'UP_REG' signal remains '1' until the flip-flop is reset by the 'RST_UPDN' signal.

In the same way, when the 'DN' pulse is applied, the 'DN_REG' signal remains '1' until the flip-flop is reset by the 'RST_UPDN' signal.

After the controller 207 stably receives the 'UP_REG' or 'DN_REG' signal, the controller 207 outputs the 'RST_UPDN' signal to initialize the two flip-flops 206a and 206b, and performs handshaking d (ank-shaking). Will end.

The controller 207 detects the phase relationship between the output signal hclk of the comparator 203 and the output signal rclk of the inverter 204 through the input 'UP_REG' signal and 'DN_REG' signal, and the variable high pass. The time constant of the filter 202 is adjusted to adjust the transition time of the output signal hclk of the comparator 203.

FIG. 9 is a flowchart for determining an output relationship of the frequency signal Freq_out according to the control signal Zctrl in the controller 207.

The frequency signal FREQ_OUT of the controller 207 determines whether the control signal Zctrl of a predetermined continuous number is constant from the control signal Zctrl of the controller 207 (901).

When the control signal Zctrl of the predetermined continuous number is constant in the control signal Zctrl of the controller 207, the frequency signal FREQ_OUT is output in response to the control signal Zctrl (903).

When the control signal Zctrl of the predetermined continuous number is not constant in the control signal Zctrl of the controller 207, any one of the smallest value or the largest value among the predetermined continuous number of control signals Zctrl. Corresponds to the frequency signal FREQ_OUT (step 902).

Whether the smallest value in the control signal Zctrl corresponds to the frequency signal Freq_out or whether the largest value in the control signal Zctrl corresponds to the frequency signal Freq_out is predetermined.

The control signal Zctrl of the controller 207 is a signal obtained by adjusting a time constant value of the variable high pass filter 202 to detect a frequency component. When digitally controlling the variable highpass filter 202, the detected signal has quantization noise because the resolution is discrete rather than continuous.

That is, when the output signal rclk of the inverter 204 and the output signal hclk of the comparator 203 are not exactly in phase, the comparator emits only 'UP' or 'DN' pulses. This pulse raises or lowers the value of the control signal Zctrl of the controller 207 by one step. When the phase is out of phase, the phase detector 205 of the next clock cycle has the previous' UP '/' DN. Emits the opposite signal.

For example, if the output signal refclk of the frequency divider 201 exists between Zctrl [n-1] (n means a predetermined cycle) and Zctrl [n], the k th cycle For a Zctrl [n-1] value, the phase detector 205 will generate an 'UP' pulse, and the controller 207 sets Zctrl [n] to '1' to increase the time constant of the variable highpass filter 202. Will be set to

Then, in the (k + 1) th cycle, since the time constant value determined by Zctrl [n] is faster than the half period of the output signal refclk of the divider 201, the 'DN' is opposed to the (k) th cycle. 'Will print a pulse.

Thus, the value of the control signal Zctrl of the controller 207 will oscillate between any two values and cannot deliver stable frequency information to the system.

Accordingly, in the automatic frequency detection apparatus according to the present invention, all of the 'UP' / 'DN' are '1' or 'UP' / 'DN' are all caused by the control signal Zctrl of a predetermined number of controllers 207 in succession. In the case of '0', the frequency signal FREQ_OUT selects the value of the control signal Zctrl of the controller 207 corresponding to the phase signal and determines the value of the control signal Zctrl of the controller 207. In the case of oscillation between these two values, the lowest or highest value among the values of the control signal Zctrl of a predetermined number of controllers 207 is selected as the frequency signal FREQ_OUT and outputted. It is possible to prevent the frequency signal FREQ_OUT from becoming unstable.

As described above, the present invention automatically detects the frequency of the system clock and provides the information to the system, thereby enabling the system to have optimal performance at the operating frequency.

Claims (11)

A high pass filter having a variable time constant value by a predetermined control signal; A comparator for comparing the output signal of the high pass filter with a predetermined reference signal; A phase detector for detecting a phase difference between an output signal of the comparator and an input signal of the high pass filter; And And a controller for outputting the control signal for varying the time constant value of the high pass filter based on the output signal of the phase detector. According to claim 1, Wherein said high pass filter comprises a variable resistor and a capacitor controlled by said control signal. The method of claim 2, The variable resistor includes a plurality of resistors and switches, characterized in that each switch is controlled by the control signal, automatic frequency detection device. According to claim 1, And the input signal of the high pass filter input to the phase detector is inverted. According to claim 1, And a handshaking circuit is further included between the phase detector and the controller. The method of claim 5, And said handshaking circuit is implemented as a flip-flop. According to claim 1, And an output signal of the high pass filter is initialized by the controller at a predetermined cycle. The method of claim 7, wherein And said predetermined period is a half period of a frequency of an input signal of said high pass filter. According to claim 1, And the input of the high pass filter is input to the high pass filter via a divider. According to claim 1, The controller outputs the control signal for controlling the time constant and the frequency signal having detected frequency information based on the output signal of the phase detector, And a digital filter for determining the frequency signal by determining whether the control signal is continuously a predetermined number of times. The method of claim 10, The digital filter corresponds to the control signal when the control signal is constant. And if the frequency signal is not constant, the frequency signal corresponds to one of the smallest value and the largest value among the control signals.

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