ES2120912B1 - Circuito integrado de aplicacion especifica. - Google Patents
Circuito integrado de aplicacion especifica.Info
- Publication number
- ES2120912B1 ES2120912B1 ES9700166A ES9700166A ES2120912B1 ES 2120912 B1 ES2120912 B1 ES 2120912B1 ES 9700166 A ES9700166 A ES 9700166A ES 9700166 A ES9700166 A ES 9700166A ES 2120912 B1 ES2120912 B1 ES 2120912B1
- Authority
- ES
- Spain
- Prior art keywords
- block
- integrated circuit
- perform
- function
- specific application
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Credit Cards Or The Like (AREA)
- Hardware Redundancy (AREA)
Abstract
CIRCUITO INTEGRADO DE APLICACION ESPECIFICA, QUE COMPRENDE: UN PRIMER BLOQUE (1) QUE CONSTITUYE EL INTERFAZ ENTRE UN MICROPROCESADOR Y LOS RESTANTES BLOQUES; UN SEGUNDO BLOQUE (2), DE GESTION DE INTERRUPCIONES, UN TERCER BLOQUE (3), DE GESTION DE DIRECCIONAMIENTO DE LA MEMORIA, PARA REALIZAR LA FUNCION DE REASIGNACION DE DIRECCIONES DE LA MEMORIA EXTERNA DEL MICROPROCESADOR Y PARA GENERAR SEÑALES DE INTERRUPCION; UN CUARTO BLOQUE (4), LECTOR DE BANDA MAGNETICA, PARA REALIZAR LA FUNCION DE PARALELIZACION DE SEÑALES CORRESPONDIENTES A LAS PISTAS DE DATOS DE UNA TARJETA DE BANDA MAGNETICA; UN QUINTO BLOQUE (5), CON CANALES DE COMUNICACION ASINCRONA APTOS PARA OPERAR EN MODO UART O COMO INTERFAZ DE TARJETA INTELIGENTE, UN SEXTO BLOQUE (6) PARA LA REALIZACION DE FUNCIONES DE RELOJ, CALENDARIO Y DESPERTADOR; UN SEPTIMO BLOQUE (7) PARA REALIZAR LA FUNCION DE SUPERVISION DEL DESARROLLO DEL SOFTWARE; Y UN OCTAVO BLOQUE (8) CON LAS ALIMENTACIONES DEL CIRCUITO INTEGRADO. FIGURA 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9700166A ES2120912B1 (es) | 1997-01-29 | 1997-01-29 | Circuito integrado de aplicacion especifica. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9700166A ES2120912B1 (es) | 1997-01-29 | 1997-01-29 | Circuito integrado de aplicacion especifica. |
Publications (2)
Publication Number | Publication Date |
---|---|
ES2120912A1 ES2120912A1 (es) | 1998-11-01 |
ES2120912B1 true ES2120912B1 (es) | 1999-06-01 |
Family
ID=8298024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES9700166A Expired - Fee Related ES2120912B1 (es) | 1997-01-29 | 1997-01-29 | Circuito integrado de aplicacion especifica. |
Country Status (1)
Country | Link |
---|---|
ES (1) | ES2120912B1 (es) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2180391B1 (es) * | 2000-09-25 | 2003-12-16 | Telesincro S A | Circuito integrado. |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965801A (en) * | 1987-09-28 | 1990-10-23 | Ncr Corporation | Architectural arrangement for a SCSI disk controller integrated circuit |
JPH04163655A (ja) * | 1990-10-26 | 1992-06-09 | Mitsubishi Electric Corp | 入出力装置 |
FR2668622A1 (fr) * | 1990-10-26 | 1992-04-30 | Bull Sa | Circuit de controle d'acces a une memoire. |
EP0497442A3 (en) * | 1991-01-29 | 1993-03-03 | Advanced Micro Devices, Inc. | Multi-peripheral controller |
JP2927634B2 (ja) * | 1993-03-22 | 1999-07-28 | シャープ株式会社 | メモリインタフェイス装置 |
GB9419246D0 (en) * | 1994-09-23 | 1994-11-09 | Cambridge Consultants | Data processing circuits and interfaces |
-
1997
- 1997-01-29 ES ES9700166A patent/ES2120912B1/es not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
ES2120912A1 (es) | 1998-11-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EC2A | Search report published |
Date of ref document: 19981101 Kind code of ref document: A1 Effective date: 19981101 |
|
PC2A | Transfer granted | ||
FD1A | Patent lapsed |
Effective date: 20050131 |