ES2120912A1 - Circuito integrado de aplicacion especifica. - Google Patents

Circuito integrado de aplicacion especifica.

Info

Publication number
ES2120912A1
ES2120912A1 ES09700166A ES9700166A ES2120912A1 ES 2120912 A1 ES2120912 A1 ES 2120912A1 ES 09700166 A ES09700166 A ES 09700166A ES 9700166 A ES9700166 A ES 9700166A ES 2120912 A1 ES2120912 A1 ES 2120912A1
Authority
ES
Spain
Prior art keywords
block
integrated circuit
function
special application
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES09700166A
Other languages
English (en)
Other versions
ES2120912B1 (es
Inventor
Espa Ol Alberto Girons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telesincro S A
Original Assignee
Telesincro S A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telesincro S A filed Critical Telesincro S A
Priority to ES9700166A priority Critical patent/ES2120912B1/es
Publication of ES2120912A1 publication Critical patent/ES2120912A1/es
Application granted granted Critical
Publication of ES2120912B1 publication Critical patent/ES2120912B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Credit Cards Or The Like (AREA)
  • Hardware Redundancy (AREA)

Abstract

CIRCUITO INTEGRADO DE APLICACION ESPECIFICA, QUE COMPRENDE: UN PRIMER BLOQUE (1) QUE CONSTITUYE EL INTERFAZ ENTRE UN MICROPROCESADOR Y LOS RESTANTES BLOQUES; UN SEGUNDO BLOQUE (2), DE GESTION DE INTERRUPCIONES, UN TERCER BLOQUE (3), DE GESTION DE DIRECCIONAMIENTO DE LA MEMORIA, PARA REALIZAR LA FUNCION DE REASIGNACION DE DIRECCIONES DE LA MEMORIA EXTERNA DEL MICROPROCESADOR Y PARA GENERAR SEÑALES DE INTERRUPCION; UN CUARTO BLOQUE (4), LECTOR DE BANDA MAGNETICA, PARA REALIZAR LA FUNCION DE PARALELIZACION DE SEÑALES CORRESPONDIENTES A LAS PISTAS DE DATOS DE UNA TARJETA DE BANDA MAGNETICA; UN QUINTO BLOQUE (5), CON CANALES DE COMUNICACION ASINCRONA APTOS PARA OPERAR EN MODO UART O COMO INTERFAZ DE TARJETA INTELIGENTE, UN SEXTO BLOQUE (6) PARA LA REALIZACION DE FUNCIONES DE RELOJ, CALENDARIO Y DESPERTADOR; UN SEPTIMO BLOQUE (7) PARA REALIZAR LA FUNCION DE SUPERVISION DEL DESARROLLO DEL SOFTWARE; Y UN OCTAVO BLOQUE (8) CON LAS ALIMENTACIONES DEL CIRCUITO INTEGRADO. FIGURA 1.
ES9700166A 1997-01-29 1997-01-29 Circuito integrado de aplicacion especifica. Expired - Fee Related ES2120912B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9700166A ES2120912B1 (es) 1997-01-29 1997-01-29 Circuito integrado de aplicacion especifica.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9700166A ES2120912B1 (es) 1997-01-29 1997-01-29 Circuito integrado de aplicacion especifica.

Publications (2)

Publication Number Publication Date
ES2120912A1 true ES2120912A1 (es) 1998-11-01
ES2120912B1 ES2120912B1 (es) 1999-06-01

Family

ID=8298024

Family Applications (1)

Application Number Title Priority Date Filing Date
ES9700166A Expired - Fee Related ES2120912B1 (es) 1997-01-29 1997-01-29 Circuito integrado de aplicacion especifica.

Country Status (1)

Country Link
ES (1) ES2120912B1 (es)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1191423A3 (en) * 2000-09-25 2004-05-26 Telesincro S.A. Integrated circuit with cryptographic capabilities

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965801A (en) * 1987-09-28 1990-10-23 Ncr Corporation Architectural arrangement for a SCSI disk controller integrated circuit
FR2668622A1 (fr) * 1990-10-26 1992-04-30 Bull Sa Circuit de controle d'acces a une memoire.
EP0497442A2 (en) * 1991-01-29 1992-08-05 Advanced Micro Devices, Inc. Multi-peripheral controller
US5444852A (en) * 1990-10-26 1995-08-22 Mitsubishi Denki Kabushiki Kaisha I/O device interface having buffer mapped in processor memory addressing space and control registers mapped in processor I/O addressing space
US5502834A (en) * 1993-03-22 1996-03-26 Sharp Kabushiki Kaisha Memory interface apparatus for carrying out complex operation processing
WO1996009583A2 (en) * 1994-09-23 1996-03-28 Cambridge Consultants Limited Data processing circuits and interfaces

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965801A (en) * 1987-09-28 1990-10-23 Ncr Corporation Architectural arrangement for a SCSI disk controller integrated circuit
FR2668622A1 (fr) * 1990-10-26 1992-04-30 Bull Sa Circuit de controle d'acces a une memoire.
US5444852A (en) * 1990-10-26 1995-08-22 Mitsubishi Denki Kabushiki Kaisha I/O device interface having buffer mapped in processor memory addressing space and control registers mapped in processor I/O addressing space
EP0497442A2 (en) * 1991-01-29 1992-08-05 Advanced Micro Devices, Inc. Multi-peripheral controller
US5502834A (en) * 1993-03-22 1996-03-26 Sharp Kabushiki Kaisha Memory interface apparatus for carrying out complex operation processing
WO1996009583A2 (en) * 1994-09-23 1996-03-28 Cambridge Consultants Limited Data processing circuits and interfaces

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1191423A3 (en) * 2000-09-25 2004-05-26 Telesincro S.A. Integrated circuit with cryptographic capabilities

Also Published As

Publication number Publication date
ES2120912B1 (es) 1999-06-01

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