ES2087867T3 - Conjunto de puertas programables por mascara para control de bus. - Google Patents
Conjunto de puertas programables por mascara para control de bus.Info
- Publication number
- ES2087867T3 ES2087867T3 ES89309931T ES89309931T ES2087867T3 ES 2087867 T3 ES2087867 T3 ES 2087867T3 ES 89309931 T ES89309931 T ES 89309931T ES 89309931 T ES89309931 T ES 89309931T ES 2087867 T3 ES2087867 T3 ES 2087867T3
- Authority
- ES
- Spain
- Prior art keywords
- communications
- gate array
- bus control
- interface devices
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
- H03K19/01812—Interface arrangements with at least one differential stage
Abstract
UN CONJUNTO DE PUERTAS DE CONTROL DE BUSES DE COMUNICACIONES ADAPTADOS A LOS CLIENTES, PARA FACILITAR LAS COMUNICACIONES ENTRE DISPOSITIVOS SOBRE DOS CANALES DIFERENTES DE COMUNICACIONES DIGITALES. EL CONJUNTO DE PUERTAS TIENE UN CIRCUITO INTEGRADO PROGRAMABLE DE MASCARAS, CON DOS DISPOSITIVOS DE INTERFACE IÑO, QUE ESTAN RESPECTIVAMENTE CONECTADOS A DOS CANALES DIFERENTES DE COMUNICACIONES. EL CONJUNTO DE PUERTAS DISPONE TAMBIEN DE UN DISPOSITIVO TRADUCTOR, CONECTADO A CADA UNO DE LOS DISPOSITIVOS DE INTERFACE IÑO, PARA TRADUCIR LAS SEÑALES ELECTRICAS ENTRE ELLOS. TAMBIEN SE DISPONE DE CONTROL LOGICO, Y CONECTADO A AMBOS DISPOSITIVOS DE INTERFACE IÑO Y AL DISPOSITIVO TRADUCTOR, PARA CONTROLAR EL FUNCIONAMIENTO DE LOS MISMOS, CON LO QUE SE SATISFACEN LOS REQUERIMIENTOS PREVIAMENTE DETERMINADOS DE COMUNICACIONES ENTRE AMBOS CANALES DIFERENTES DE COMUNICACIONES.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/254,751 US4987578A (en) | 1988-10-07 | 1988-10-07 | Mask programmable bus control gate array |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2087867T3 true ES2087867T3 (es) | 1996-08-01 |
Family
ID=22965459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES89309931T Expired - Lifetime ES2087867T3 (es) | 1988-10-07 | 1989-09-29 | Conjunto de puertas programables por mascara para control de bus. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4987578A (es) |
EP (1) | EP0363086B1 (es) |
JP (1) | JPH02144650A (es) |
AT (1) | ATE139356T1 (es) |
DE (1) | DE68926649T2 (es) |
ES (1) | ES2087867T3 (es) |
GR (1) | GR3020218T3 (es) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03109767A (ja) * | 1989-09-25 | 1991-05-09 | Nec Corp | 半導体集積回路装置 |
AU7255491A (en) * | 1990-02-02 | 1991-08-21 | Codex Corporation | An interface adapter |
US5347181A (en) * | 1992-04-29 | 1994-09-13 | Motorola, Inc. | Interface control logic for embedding a microprocessor in a gate array |
GB9209394D0 (en) * | 1992-04-30 | 1992-06-17 | Mini Agriculture & Fisheries | Data storage tags |
US5691218A (en) * | 1993-07-01 | 1997-11-25 | Lsi Logic Corporation | Method of fabricating a programmable polysilicon gate array base cell structure |
US5552333A (en) * | 1994-09-16 | 1996-09-03 | Lsi Logic Corporation | Method for designing low profile variable width input/output cells |
US5758132A (en) * | 1995-03-29 | 1998-05-26 | Telefonaktiebolaget Lm Ericsson | Clock control system and method using circuitry operating at lower clock frequency for selecting and synchronizing the switching of higher frequency clock signals |
US5970255A (en) * | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
US5698873A (en) * | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
US6137340A (en) * | 1998-08-11 | 2000-10-24 | Fairchild Semiconductor Corp | Low voltage, high speed multiplexer |
US7299203B1 (en) * | 2001-04-19 | 2007-11-20 | Xilinx, Inc. | Method for storing and shipping programmable ASSP devices |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211248A (en) * | 1981-06-22 | 1982-12-25 | Hitachi Ltd | Semiconductor integrated circuit device |
US4430582A (en) * | 1981-11-16 | 1984-02-07 | National Semiconductor Corporation | Fast CMOS buffer for TTL input levels |
US4734592A (en) * | 1983-10-31 | 1988-03-29 | Texas Instruments Incorporated | Interface circuit for data processing system |
US4614882A (en) * | 1983-11-22 | 1986-09-30 | Digital Equipment Corporation | Bus transceiver including compensation circuit for variations in electrical characteristics of components |
JPS61274513A (ja) * | 1985-04-19 | 1986-12-04 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | 論理レベル変換器 |
US4645954A (en) * | 1985-10-21 | 1987-02-24 | International Business Machines Corp. | ECL to FET interface circuit for field effect transistor arrays |
US4719372A (en) * | 1986-02-03 | 1988-01-12 | International Business Machines Corporation | Multiplying interface circuit for level shifting between FET and TTL levels |
FR2598871B1 (fr) * | 1986-05-14 | 1988-09-30 | Bendix Electronics Sa | Circuit d'interface bidirectionnel presentant un acces unipolaire et un acces bipolaire pour des signaux logiques |
-
1988
- 1988-10-07 US US07/254,751 patent/US4987578A/en not_active Expired - Lifetime
-
1989
- 1989-09-29 EP EP89309931A patent/EP0363086B1/en not_active Expired - Lifetime
- 1989-09-29 DE DE68926649T patent/DE68926649T2/de not_active Expired - Fee Related
- 1989-09-29 ES ES89309931T patent/ES2087867T3/es not_active Expired - Lifetime
- 1989-09-29 AT AT89309931T patent/ATE139356T1/de not_active IP Right Cessation
- 1989-10-06 JP JP1262845A patent/JPH02144650A/ja active Pending
-
1996
- 1996-06-13 GR GR960401340T patent/GR3020218T3/el unknown
Also Published As
Publication number | Publication date |
---|---|
EP0363086A3 (en) | 1991-07-31 |
EP0363086B1 (en) | 1996-06-12 |
DE68926649T2 (de) | 1997-01-02 |
ATE139356T1 (de) | 1996-06-15 |
EP0363086A2 (en) | 1990-04-11 |
US4987578A (en) | 1991-01-22 |
JPH02144650A (ja) | 1990-06-04 |
DE68926649D1 (de) | 1996-07-18 |
GR3020218T3 (en) | 1996-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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