ES2085883T3 - Circuito para la adaptacion de las velocidades de bits de dos señales. - Google Patents

Circuito para la adaptacion de las velocidades de bits de dos señales.

Info

Publication number
ES2085883T3
ES2085883T3 ES90201626T ES90201626T ES2085883T3 ES 2085883 T3 ES2085883 T3 ES 2085883T3 ES 90201626 T ES90201626 T ES 90201626T ES 90201626 T ES90201626 T ES 90201626T ES 2085883 T3 ES2085883 T3 ES 2085883T3
Authority
ES
Spain
Prior art keywords
circuit
adaptation
signal bit
bit speeds
speeds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90201626T
Other languages
English (en)
Inventor
Ralph Dipl-Ing Urbansky
Michael Dipl-Ing Niegel
Miguel Dr-Ing Robledo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of ES2085883T3 publication Critical patent/ES2085883T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

EL CIRCUITO DESCRITO SE UTILIZA EN LOS MULTIPLEXORES PLESIOCRONOS PARA LLEVAR A LA MISMA VELOCIDAD BINARIA LAS SEÑALES PLESIOCRONAS, QUE SE DEBEN AGRUPAR EN UNA SEÑAL DIGITAL DE ORDEN SUPERIOR. EL CIRCUITO, BASADO PREDOMINANTEMENTE EN LA TECNOLOGIA CMOS, ES APLICABLE A SISTEMAS DE 140 MBIT/S.
ES90201626T 1989-06-22 1990-06-21 Circuito para la adaptacion de las velocidades de bits de dos señales. Expired - Lifetime ES2085883T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3920391A DE3920391A1 (de) 1989-06-22 1989-06-22 Schaltungsanordnung zur anpassung der bitraten zweier signale

Publications (1)

Publication Number Publication Date
ES2085883T3 true ES2085883T3 (es) 1996-06-16

Family

ID=6383289

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90201626T Expired - Lifetime ES2085883T3 (es) 1989-06-22 1990-06-21 Circuito para la adaptacion de las velocidades de bits de dos señales.

Country Status (4)

Country Link
EP (1) EP0404268B1 (es)
JP (1) JPH03129934A (es)
DE (2) DE3920391A1 (es)
ES (1) ES2085883T3 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4027967A1 (de) * 1990-09-04 1992-03-05 Philips Patentverwaltung Stopfentscheidungsschaltung fuer eine anordnung zur bitratenanpassung
JPH04286233A (ja) * 1991-03-14 1992-10-12 Nec Corp スタッフ同期回路
DE4205959A1 (de) * 1992-02-27 1993-09-02 Philips Patentverwaltung Schaltungsanordnung zum ausgleich von frequenz- und/oder phasenschwankungen zwischen einem ankommenden und einem abgehenden signal
US5285206A (en) * 1992-08-25 1994-02-08 Alcatel Network Systems, Inc. Phase detector for elastic store
DE4425087A1 (de) * 1994-07-15 1996-01-18 Philips Patentverwaltung Übertragungssystem
EP0702465A1 (fr) * 1994-09-13 1996-03-20 T.R.T. Telecommunications Radioelectriques Et Telephoniques Système de transmission et équipement de multiplexage-démultiplexage impliquant un flux d'éléments binaires pouvant être justifié
DE19707365C2 (de) * 1997-02-25 1999-01-07 Lucent Tech Network Sys Gmbh Digitaler Oszillator
DE19719547C1 (de) * 1997-05-09 1998-11-12 Lucent Tech Network Sys Gmbh Digitaler Oszillator

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2269246B1 (es) * 1974-04-25 1976-12-17 Cit Alcatel
US4397017A (en) * 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
DE3843372C2 (de) * 1988-12-23 1997-03-27 Bosch Gmbh Robert Verfahren und Schaltungsanordnung zur Taktanpassung in der digitalen Nachrichtentechnik

Also Published As

Publication number Publication date
JPH03129934A (ja) 1991-06-03
EP0404268B1 (de) 1996-02-07
EP0404268A2 (de) 1990-12-27
EP0404268A3 (de) 1991-10-09
DE59010110D1 (de) 1996-03-21
DE3920391A1 (de) 1991-01-10

Similar Documents

Publication Publication Date Title
DE69130392T2 (de) Hochgeschwindigkeitspufferverwaltung
EP0328063A3 (en) Absolute value calculating circuit having a single adder
DE68912277D1 (de) Ausgangspufferschaltung.
ES2103331T3 (es) Unidad de memoria con generador de direcciones.
ES2085883T3 (es) Circuito para la adaptacion de las velocidades de bits de dos señales.
ATE213849T1 (de) Bereichsdetektierschaltung
DE3851487D1 (de) Schneller CMOS-Ausgangspuffer mit niedriger Störspannung.
DE68911584D1 (de) Digitaler Signalregenerator.
ES2118976T3 (es) Codificador audio de paquetes en tiempo real que funcionan en modo de capas.
AU564002B2 (en) Digital data converting
CA2210211A1 (en) Method of and apparatus for generating a pseudorandom noise sequence
GR3007799T3 (es)
ES2132106T3 (es) Registro de desplazamiento de entrada paralelo de n bitios a salida paralelo de bitios variables.
FR2443721B1 (fr) Systeme d'ordinateur numerique a grande vitesse de faible encombrement
EP0297581A3 (en) Pseudo-noise sequence generator
ATE117484T1 (de) Zuverlässige datenrückgewinnung in einem kodierer/dekodierer.
ES491936A0 (es) Conexion para la transmision de una serie binaria para transferir datos
DE69326529D1 (de) Erweiterbarer, digitaler Multiplexer hoher Schaltgeschwindigkeit
EP1142126A4 (en) CAPACITIVE PARALLEL ANALOG-TO-DIGITAL CONVERTER
IT8920537A0 (it) Convertitore analogico/digitale ad elevata velocita'.
KR870006562A (ko) 디스크 재생 장치
JPS5428529A (en) Information output system
AR246144A1 (es) Cuadro basico de pulsos para una jerarquia multiplex de senales digitales para una red sincronica.
ITMI920108A1 (it) Metodo per la realizzazione di una rete di connessione per segnali appartenenti alla gerarchia sincrona sdh (synchronous digital hierarchy), e circuiti integrati per l'implementazione del metodo
ES544048A0 (es) Aparato para convertir una primera senal modulada en delta con una primera frecuencia de bits en una segunda senal modulada en delta con una segunda frecuencia de bits.

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 404268

Country of ref document: ES