ES2103331T3 - Unidad de memoria con generador de direcciones. - Google Patents

Unidad de memoria con generador de direcciones.

Info

Publication number
ES2103331T3
ES2103331T3 ES92113292T ES92113292T ES2103331T3 ES 2103331 T3 ES2103331 T3 ES 2103331T3 ES 92113292 T ES92113292 T ES 92113292T ES 92113292 T ES92113292 T ES 92113292T ES 2103331 T3 ES2103331 T3 ES 2103331T3
Authority
ES
Spain
Prior art keywords
address
memory unit
address generator
generator
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92113292T
Other languages
English (en)
Inventor
Werner Koch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Alcatel SEL AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SEL AG filed Critical Alcatel SEL AG
Application granted granted Critical
Publication of ES2103331T3 publication Critical patent/ES2103331T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Computer And Data Communications (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)

Abstract

SE DESCRIBE UNA UNIDAD DE ALMACENADO (SE) CON VARIAS "AREAS DE DIRECCIONES" VARIABLES EN MAGNITUD Y CANTIDAD. PARA UN AREA DE DIRECCION SE ALMACENA SIEMPRE SOLO UN VALOR DE DIRECCION, ASI COMO LAS DIRECCIONES INICIAL Y FINAL. UN GENERADOR DE DIRECCIONES (AG) CUENTA LAS DIRECCIONES DESDE LA DIRECCION INICIAL HASTA LA DIRECCION FINAL. LAS DIRECCIONES INICIAL Y FINAL SE CONDUCEN A UN REGISTRO DE DIRECCIONES (AR) POR MEDIO DE UN ORDENADOR CENTRAL (ZR), EL CUAL ESTA UNIDO CON UN GENERADOR DE DIRECCIONES (AG). POR MEDIO DE UN NUMERO IDENTIFICADOR SE SOLICITAN LAS DIRECCIONES INICIAL Y FINAL EN EL REGISTRO DE DIRECCIONES (AR) Y UN VALOR DE DIRECCION ACTUAL EN EL GENERADOR DE DIRECCIONES (AG). EL GENERADOR DE DIRECCIONES (AG) CUENTA EL AREA DE DIRECCION, HASTA QUE ES ALCANZADA LA DIRECCION FINAL. LA UNIDAD DE ALMACENADO (SE) ENCUENTRA SU APLICACION, CON PREFERENCIA, EN UN SISTEMA DE TRANSMISION CONEXION CRUZADA DE UN SDH.
ES92113292T 1991-08-21 1992-08-05 Unidad de memoria con generador de direcciones. Expired - Lifetime ES2103331T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4127579A DE4127579A1 (de) 1991-08-21 1991-08-21 Speichereinheit mit einem adressgenerator

Publications (1)

Publication Number Publication Date
ES2103331T3 true ES2103331T3 (es) 1997-09-16

Family

ID=6438714

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92113292T Expired - Lifetime ES2103331T3 (es) 1991-08-21 1992-08-05 Unidad de memoria con generador de direcciones.

Country Status (7)

Country Link
US (1) US5737570A (es)
EP (1) EP0529358B1 (es)
AT (1) ATE152280T1 (es)
AU (1) AU650994B2 (es)
DE (2) DE4127579A1 (es)
DK (1) DK0529358T3 (es)
ES (1) ES2103331T3 (es)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522575C2 (de) * 1994-06-27 1999-06-10 Lw Composite Gmbh & Co Aufprallvorrichtung für Fahrzeuge
GB2319934B (en) * 1996-11-27 2001-06-06 Sony Uk Ltd Digital signal processing
CA2293066A1 (en) * 1999-12-20 2001-06-20 Nortel Networks Corporation Method and apparatus for cross-connecting data streams with efficient memory utilization and transparent protocol conversion
US20030005269A1 (en) * 2001-06-01 2003-01-02 Conner Joshua M. Multi-precision barrel shifting
US7007172B2 (en) * 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6952711B2 (en) * 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US7020788B2 (en) * 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6937084B2 (en) * 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US20030005268A1 (en) * 2001-06-01 2003-01-02 Catherwood Michael I. Find first bit value instruction
US6985986B2 (en) * 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6934728B2 (en) * 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US7003543B2 (en) * 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US20020184566A1 (en) * 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6976158B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US20030028696A1 (en) * 2001-06-01 2003-02-06 Michael Catherwood Low overhead interrupt
US20030023836A1 (en) * 2001-06-01 2003-01-30 Michael Catherwood Shadow register array control instructions
US6975679B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US7467178B2 (en) * 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
GB0118678D0 (en) * 2001-08-01 2001-09-19 Qinetiq Ltd Random access decoder
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US7886205B2 (en) * 2008-06-24 2011-02-08 Unisys Corporation Verification of a data processing system using overlapping address ranges
US20100205349A1 (en) * 2009-02-11 2010-08-12 Stec, Inc. Segmented-memory flash backed dram module

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2056135B (en) * 1977-12-22 1982-11-24 Honeywell Inf Systems Data processing system including a cache store
JPS5717049A (en) * 1980-07-04 1982-01-28 Hitachi Ltd Direct memory access controlling circuit and data processing system
GB2095441A (en) * 1981-03-25 1982-09-29 Philips Electronic Associated A method of storing data and a store therefor
US4482951A (en) * 1981-11-12 1984-11-13 Hughes Aircraft Company Direct memory access method for use with a multiplexed data bus
JPS60235269A (ja) * 1984-05-08 1985-11-21 Toshiba Corp デ−タ転送制御装置
JPS62260444A (ja) * 1986-05-06 1987-11-12 Mitsubishi Electric Corp 双方向エラステイツクストア回路
DE3942883A1 (de) * 1989-12-23 1991-06-27 Philips Patentverwaltung Schaltungsanordnung zur bitratenanpassung
US5003509A (en) * 1990-03-27 1991-03-26 National Semiconductor Corp. Multi-port, bipolar-CMOS memory cell

Also Published As

Publication number Publication date
DE4127579A1 (de) 1993-02-25
EP0529358A1 (de) 1993-03-03
DE59208377D1 (de) 1997-05-28
DK0529358T3 (da) 1997-08-04
EP0529358B1 (de) 1997-04-23
ATE152280T1 (de) 1997-05-15
AU2114192A (en) 1993-03-04
AU650994B2 (en) 1994-07-07
US5737570A (en) 1998-04-07

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