ES2083987T3 - Circuito de decision de llenado. - Google Patents

Circuito de decision de llenado.

Info

Publication number
ES2083987T3
ES2083987T3 ES90116389T ES90116389T ES2083987T3 ES 2083987 T3 ES2083987 T3 ES 2083987T3 ES 90116389 T ES90116389 T ES 90116389T ES 90116389 T ES90116389 T ES 90116389T ES 2083987 T3 ES2083987 T3 ES 2083987T3
Authority
ES
Spain
Prior art keywords
bit rate
decision circuit
stuffing
decision
stuffing decision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90116389T
Other languages
English (en)
Inventor
Ralph Dipl-Ing Urbansky
Miguel Dr Ing Robledo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of ES2083987T3 publication Critical patent/ES2083987T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Engineering & Computer Science (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Television Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Basic Packing Technique (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

SE DESCRIBE UNA CONEXION DE DECISION DE RELLENO QUE SIRVE PARA LA ADAPTACION DE LAS CANTIDADES DE BITS DE DOS SEÑALES. PARA UTILIZAR LA CONEXION ES NECESARIO QUE LA SEÑAL CON MAS CANTIDAD DE BITS ESTE ESTRUCTURADA POR CUADROS, DE MODO QUE SE REALICE UNA DECISION POR CUADRO. PARA PODER ELIMINAR EL LLAMADO JITTER DE TIEMPO DE ESPERA QUE APARECE EN EL LADO DE RECEPCION, AL RECUPERARSE LA SEÑAL CON MENOS CANTIDAD DE BITS, SE PROPONEN MEDIOS PARA ATRASAR EL MOMENTO DE LA DECISION DE RELLENO DE MANERA ALEATORIA O SEUDOALEATORIA POR TIEMPOS MUCHO MAS CORTOS QUE UN CUADRO. GRACIAS A ESA MODULACION DEL MOMENTO DE LA DECISION, EL JITTER, QUE POR SI TIENE FRECUENCIAS BAJAS SE TRANSFORMA A FRECUENCIAS MAS ALTAS Y PUEDE ELIMINARSE DEL LADO DE RECEPCION SIN MAS QUE CON UN BUCLE DE CONTROL DE FASES.
ES90116389T 1989-08-09 1990-08-09 Circuito de decision de llenado. Expired - Lifetime ES2083987T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3926251A DE3926251A1 (de) 1989-08-09 1989-08-09 Stopfentscheidungsschaltung

Publications (1)

Publication Number Publication Date
ES2083987T3 true ES2083987T3 (es) 1996-05-01

Family

ID=6386763

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90116389T Expired - Lifetime ES2083987T3 (es) 1989-08-09 1990-08-09 Circuito de decision de llenado.

Country Status (6)

Country Link
EP (1) EP0412575B1 (es)
AT (1) ATE132677T1 (es)
DE (2) DE3926251A1 (es)
DK (1) DK0412575T3 (es)
ES (1) ES2083987T3 (es)
GR (1) GR3019524T3 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4108429A1 (de) * 1991-03-15 1992-09-17 Philips Patentverwaltung Uebertragungssystem fuer die digitale synchrone hierarchie
DE4110933A1 (de) * 1991-04-04 1992-10-08 Philips Patentverwaltung Uebertragungssystem fuer die synchrone digitale hierachie
ITMI20051286A1 (it) * 2005-07-08 2007-01-09 Alcatel Italia Dispositivo e metodo per mappare-demappare in segnale tributario in-da trame di trasporto

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0035795B1 (en) * 1980-03-10 1985-12-04 Nec Corporation Stuff synchronization device with reduced sampling jitter
JPS57212842A (en) * 1981-06-25 1982-12-27 Nec Corp Pulse stuff synchronizing device
JPS61224740A (ja) * 1985-03-29 1986-10-06 Fujitsu Ltd スタツフ同期方式

Also Published As

Publication number Publication date
DE3926251A1 (de) 1991-02-14
ATE132677T1 (de) 1996-01-15
EP0412575B1 (de) 1996-01-03
GR3019524T3 (en) 1996-07-31
DE59010029D1 (de) 1996-02-15
EP0412575A3 (en) 1992-03-25
EP0412575A2 (de) 1991-02-13
DK0412575T3 (da) 1996-05-13

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