ES2078171B1 - Procedimiento de fabricacion de modulos de potencia con elementos semiconductores. - Google Patents

Procedimiento de fabricacion de modulos de potencia con elementos semiconductores.

Info

Publication number
ES2078171B1
ES2078171B1 ES09302702A ES9302702A ES2078171B1 ES 2078171 B1 ES2078171 B1 ES 2078171B1 ES 09302702 A ES09302702 A ES 09302702A ES 9302702 A ES9302702 A ES 9302702A ES 2078171 B1 ES2078171 B1 ES 2078171B1
Authority
ES
Spain
Prior art keywords
phase
bases
elements
power modules
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
ES09302702A
Other languages
English (en)
Other versions
ES2078171A2 (es
ES2078171R (es
Inventor
Nadal Francisco Masana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Smartpack Tecnologia S A
Original Assignee
Smartpack Tecnologia S A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Smartpack Tecnologia S A filed Critical Smartpack Tecnologia S A
Priority to ES09302702A priority Critical patent/ES2078171B1/es
Publication of ES2078171A2 publication Critical patent/ES2078171A2/es
Publication of ES2078171R publication Critical patent/ES2078171R/es
Application granted granted Critical
Publication of ES2078171B1 publication Critical patent/ES2078171B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Landscapes

  • Emergency Protection Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROCEDIMIENTO DE FABRICACION DE MODULOS DE POTENCIA CON ELEMENTOS SEMICONDUCTORES. DEL TIPO DE LOS QUE FACULTAN LA INTEGRACION DE VARIOS COMPONENTES INDIVIDUALES (14) EN UN UNICO MODULO; Y CUYO OBJETO ES REDUCIR TANTO EL NUMERO DE FASES DEL PROCESO DE FABRICACION COMO LA DIVERSIDAD DE MATERIALES A UTILIZAR, PERMITIR UNA MAYOR Y MAS FACIL AUTOMATIZACION DE FABRICACION, ABARATANDO SU COSTE. CUENTA CON: UNA PRIMERA FASE DE TROQUELADO DE UNA O DOS LAMINAS, ESTABLECIENDOSE LAMINAS BASE (11) Y TERMINALES (16), DE MANERA TAL QUE ALGUNAS BASES (11) QUE FINALMENTE DEBE DE QUEDAR AISLADAS, INICIALMENTE SE MANTIENEN UNIDAS POR TRAMOS (13) DANDO AL CONJUNTO RIGIDEZ; UNA SEGUNDA FASE DE SOLDADO DE LOS DISTINTOS ELEMENTOS (14) EN LAS CORRESPONDIENTES BASES (11) Y TERMINALES (16); UNA TERCERA FASE DE INTERCONEXIONADO DE LAS BASES (11), ELEMENTOS (4) Y LOS TERMINALES (16) QUE CONSTITUYEN EL MEDIO DE CONEXION CON EL EXTERIOR; UNA CUARTA FASE DE ENCAPSULADO (20) DEL CONJUNTO PROPORCIONANDO EL AISLAMIENTO ENTRE LOS DISTINTOS ELEMENTOS (14) Y CON EL EXTERIOR; UNA QUINTA FASE DE SEPARACION DE LAS BASES (11) QUE HAN DE CONSTITUIR EL MODULO, AISLANDO LAS QUE SE MANTUVIERON UNIDAS EN LA PRIMERA FASE MEDIANTE LOS TRAMOS (13) PARA DAR RIGIDEZ; FACULTANDOSE LA OBTENCION DE UNO O VARIOS MODULOS DE POTENCIA A LA VEZ.
ES09302702A 1993-12-28 1993-12-28 Procedimiento de fabricacion de modulos de potencia con elementos semiconductores. Expired - Fee Related ES2078171B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES09302702A ES2078171B1 (es) 1993-12-28 1993-12-28 Procedimiento de fabricacion de modulos de potencia con elementos semiconductores.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES09302702A ES2078171B1 (es) 1993-12-28 1993-12-28 Procedimiento de fabricacion de modulos de potencia con elementos semiconductores.

Publications (3)

Publication Number Publication Date
ES2078171A2 ES2078171A2 (es) 1995-12-01
ES2078171R ES2078171R (es) 1997-05-16
ES2078171B1 true ES2078171B1 (es) 1998-01-16

Family

ID=8284038

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09302702A Expired - Fee Related ES2078171B1 (es) 1993-12-28 1993-12-28 Procedimiento de fabricacion de modulos de potencia con elementos semiconductores.

Country Status (1)

Country Link
ES (1) ES2078171B1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111357099B (zh) 2017-09-15 2024-05-03 费纳模组有限公司 电子器件的封装方法和接合技术

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2479564A1 (fr) * 1980-03-26 1981-10-02 Thomson Csf Boitier d'encapsulation pour module de puissance en circuit hybride
JPS6386462A (ja) * 1986-09-29 1988-04-16 Sharp Corp ソリツド・ステ−ト・リレ−の製造方法
JPH0671063B2 (ja) * 1989-09-11 1994-09-07 株式会社東芝 大電力半導体装置

Also Published As

Publication number Publication date
ES2078171A2 (es) 1995-12-01
ES2078171R (es) 1997-05-16

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EC2A Search report published

Date of ref document: 19951201

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FD1A Patent lapsed

Effective date: 20071229