ES2069846T3 - Procedimiento de tratamiento de una señal video. - Google Patents

Procedimiento de tratamiento de una señal video.

Info

Publication number
ES2069846T3
ES2069846T3 ES91401814T ES91401814T ES2069846T3 ES 2069846 T3 ES2069846 T3 ES 2069846T3 ES 91401814 T ES91401814 T ES 91401814T ES 91401814 T ES91401814 T ES 91401814T ES 2069846 T3 ES2069846 T3 ES 2069846T3
Authority
ES
Spain
Prior art keywords
blocks
data
blocks containing
video signal
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91401814T
Other languages
English (en)
Inventor
Jean-Claude Guillon
Laurent Perdrieau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EUROP RECH ELECTR LAB
Laboratoire Europeen de Recherches Electroniques Avancees SNC
Original Assignee
EUROP RECH ELECTR LAB
Laboratoire Europeen de Recherches Electroniques Avancees SNC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EUROP RECH ELECTR LAB, Laboratoire Europeen de Recherches Electroniques Avancees SNC filed Critical EUROP RECH ELECTR LAB
Application granted granted Critical
Publication of ES2069846T3 publication Critical patent/ES2069846T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/74—Circuits for processing colour signals for obtaining special effects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/04—Colour television systems using pulse code modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories

Abstract

LA PRESENTE INVENCION SE REFIERE A UN PROCESO DE TRATAMIENTO DE UNA SEÑAL DE VIDEO CODIFICADA EN FORMA DE BLOQUES DE K PALABRAS, ESTANDO ESCRITO DICHA SEÑAL EN O LEIDA A PARTIR DE DOS MEMORIAS DE TRAMA (FM1, FM2) QUE COMPRENDEN CADA UNA UN PUERTO DE ENTRADA, UN PUERTO DE SALIDA DE VELOCIDAD RAPIDA Y UN PUERTO DE SALIDA DE VELOCIDAD LENTA. SEGUN ESTE PROCESO, LA SEÑAL DE VIDEO NUMERICA EN LA ENTRADA SE FORMA POR CONJUNTOS DE M'' BLOQUES CON N'' BLOQUES QUE CONTIENEN DATOS DE LUMINOSIDAD (Y1, Y2,...) Y M''-N'' BLOQUES QUE CONTIENEN DATOS DE CROMINANCIA (C1, C2,...), ESTANDO INSCRITOS LOS BLOQUES QUE CONTIENEN LOS DATOS DE CROMINANCIA (C1) EN LA PRIMERA MEMORIA (FM1) Y LOS BLOQUES QUE CONTIENEN LOS DATOS DE CROMINANCIA (Y1) INSCRITOS EN LA SEGUNDA MEMORIA (FM2), ESTANDO INVERTIDAS EN CADA TRAMA LAS MEMORIAS. A CONTINUACION LOS BLOQUES QUE CONTIENEN LOS DATOS DE LUMINOSIDAD Y LOS BLOQUES QUE CONTIENEN LOS DATOS DE CROMINANCIA SON LEIDOS SIMULTANEAMENTE EN EL PUERTO DE SALIDA DE VELOCIDAD RAPIDA DECADA MEMORIA, ESTANDO INVERTIDAS EN CADA TRAMO LAS MEMORIAS, Y LOS DATOS SON EVENTUALMENTE TRATADOS DE MANERA A OBTENER EN LA SALIDA DE LOS DATOS DE VIDEO QUE PRESENTAN UNA RELACION DE COMPRESION DE M/N CON M > N. APLICACION EN LA TELEVISION.
ES91401814T 1990-07-13 1991-07-02 Procedimiento de tratamiento de una señal video. Expired - Lifetime ES2069846T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9008951A FR2664779B1 (fr) 1990-07-13 1990-07-13 Procede de traitement d'un signal video.

Publications (1)

Publication Number Publication Date
ES2069846T3 true ES2069846T3 (es) 1995-05-16

Family

ID=9398691

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91401814T Expired - Lifetime ES2069846T3 (es) 1990-07-13 1991-07-02 Procedimiento de tratamiento de una señal video.

Country Status (7)

Country Link
US (1) US5488432A (es)
EP (1) EP0466554B1 (es)
JP (1) JPH04255196A (es)
KR (1) KR920003741A (es)
DE (1) DE69106794T2 (es)
ES (1) ES2069846T3 (es)
FR (1) FR2664779B1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829007A (en) 1993-06-24 1998-10-27 Discovision Associates Technique for implementing a swing buffer in a memory array
US5861894A (en) 1993-06-24 1999-01-19 Discovision Associates Buffer manager
CA2145365C (en) 1994-03-24 1999-04-27 Anthony M. Jones Method for accessing banks of dram
CA2145361C (en) 1994-03-24 1999-09-07 Martin William Sotheran Buffer manager
JP3508119B2 (ja) * 1995-06-20 2004-03-22 ソニー株式会社 画面表示領域判別装置
US6005546A (en) 1996-03-21 1999-12-21 S3 Incorporated Hardware assist for YUV data format conversion to software MPEG decoder
US5907372A (en) * 1996-06-28 1999-05-25 Hitachi, Ltd. Decoding/displaying device for decoding/displaying coded picture data generated by high efficiency coding for interlace scanning picture format
JP3449142B2 (ja) 1996-12-06 2003-09-22 松下電器産業株式会社 画像縮小装置およびその制御方法
GB9704027D0 (en) * 1997-02-26 1997-04-16 Discovision Ass Memory manager for mpeg decoder
US6118823A (en) * 1997-04-01 2000-09-12 International Business Machines Corporation Control scheme for shared-use dual-port predicted error array
US6724758B1 (en) * 1999-12-20 2004-04-20 Cisco Technology, Inc. Stage specific dilation in multi-stage interconnection networks

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2644706C3 (de) * 1976-10-04 1985-12-05 Robert Bosch Gmbh, 7000 Stuttgart System zur Übertragung bzw. Speicherung eines Farbfernsehsignals
JPS5848591A (ja) * 1981-09-18 1983-03-22 Matsushita Electric Ind Co Ltd 画像メモリ−制御装置
DE3787324T2 (de) * 1986-06-20 1994-03-31 Sony Corp Videospeicher.
EP0309875A3 (de) * 1987-09-30 1991-02-06 Deutsche Thomson-Brandt GmbH Demultiplexer
EP0334932A1 (de) * 1987-09-30 1989-10-04 Deutsche Thomson-Brandt GmbH Schaltungsanordnung zur bearbeitung von videokomponenten
JPH01292984A (ja) * 1988-05-20 1989-11-27 Sony Corp 映像信号の方式変換装置
DE68912095D1 (de) * 1988-10-31 1994-02-17 Nec Corp Bildgrössenreduzierungsschaltung zur Reduzierung eines Bildes normaler Grösse in eine kleinere Fläche.

Also Published As

Publication number Publication date
FR2664779A1 (fr) 1992-01-17
DE69106794D1 (de) 1995-03-02
US5488432A (en) 1996-01-30
FR2664779B1 (fr) 1993-06-11
DE69106794T2 (de) 1995-08-24
KR920003741A (ko) 1992-02-29
JPH04255196A (ja) 1992-09-10
EP0466554B1 (fr) 1995-01-18
EP0466554A1 (fr) 1992-01-15

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