ES2042382R - - Google Patents

Info

Publication number
ES2042382R
ES2042382R ES9102409A ES9102409A ES2042382R ES 2042382 R ES2042382 R ES 2042382R ES 9102409 A ES9102409 A ES 9102409A ES 9102409 A ES9102409 A ES 9102409A ES 2042382 R ES2042382 R ES 2042382R
Authority
ES
Spain
Prior art keywords
misalignment
transistors
measurement
levels
technologies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES9102409A
Other languages
English (en)
Spanish (es)
Other versions
ES2042382B1 (es
ES2042382A2 (es
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to ES09102409A priority Critical patent/ES2042382B1/es
Publication of ES2042382A2 publication Critical patent/ES2042382A2/es
Publication of ES2042382R publication Critical patent/ES2042382R/es
Application granted granted Critical
Publication of ES2042382B1 publication Critical patent/ES2042382B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
ES09102409A 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular Expired - Fee Related ES2042382B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES09102409A ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES09102409A ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Publications (3)

Publication Number Publication Date
ES2042382A2 ES2042382A2 (es) 1993-12-01
ES2042382R true ES2042382R (enrdf_load_html_response) 1995-08-16
ES2042382B1 ES2042382B1 (es) 1996-04-01

Family

ID=8274001

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09102409A Expired - Fee Related ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Country Status (1)

Country Link
ES (1) ES2042382B1 (enrdf_load_html_response)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386459A (en) * 1980-07-11 1983-06-07 Bell Telephone Laboratories, Incorporated Electrical measurement of level-to-level misalignment in integrated circuits
US4399205A (en) * 1981-11-30 1983-08-16 International Business Machines Corporation Method and apparatus for determining photomask alignment
US4647850A (en) * 1984-10-05 1987-03-03 Burroughs Corporation Integrated circuit for measuring mask misalignment
JP2666859B2 (ja) * 1988-11-25 1997-10-22 日本電気株式会社 目合せ用バーニヤパターンを備えた半導体装置

Also Published As

Publication number Publication date
ES2042382B1 (es) 1996-04-01
ES2042382A2 (es) 1993-12-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20020425