ES2019497A6 - Descodificador digital de manipulacion por desplazamiento de fase diferencial. - Google Patents

Descodificador digital de manipulacion por desplazamiento de fase diferencial.

Info

Publication number
ES2019497A6
ES2019497A6 ES8903904A ES8903904A ES2019497A6 ES 2019497 A6 ES2019497 A6 ES 2019497A6 ES 8903904 A ES8903904 A ES 8903904A ES 8903904 A ES8903904 A ES 8903904A ES 2019497 A6 ES2019497 A6 ES 2019497A6
Authority
ES
Spain
Prior art keywords
signal
input signal
differential phase
shift keyed
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES8903904A
Other languages
English (en)
Inventor
Mark L Peischl
Ralan N Vinluan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Electronic Systems Corp
Original Assignee
Plessey Electronic Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Electronic Systems Corp filed Critical Plessey Electronic Systems Corp
Publication of ES2019497A6 publication Critical patent/ES2019497A6/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2331—Demodulator circuits; Receiver circuits using non-coherent demodulation wherein the received signal is demodulated using one or more delayed versions of itself

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
  • Pulse Circuits (AREA)

Abstract

DESCODIFICADOR DIGITAL DE MANIPULACION POR DESPLAZAMIENTO DE FASE DIFERENCIAL. UNA LINEA DE RETARDO CON DERIVACIONES O TOMAS RETARDA LA SEÑAL DE ENTRADA EN UNA MAGNITUD VARIABLE, SUSTANCIALMENTE IGUAL A UN PERIODO DE UN BITIO DE LOS DATOS MODULADOS, Y PROPORCIONA LA SEÑAL RETARDADA A UN MULTIPLICADOR PARA GENERAR UNA SEÑAL PRODUCTO. EN RESPUESTA A CAMBIOS DE FRECUENCIA DE LA SEÑAL DE ENTRADA, UN SISTEMA DE CONTROL SELECCIONA TOMAS DIFERENTES DE LA LINEA DE RETARDO A FIN DE PROPORCIONAR LA SEÑAL RETARDADA PARA MULTIPLICACION POR LA SEÑAL DE ENTRADA MODULADA. LA SEÑAL DE CONTROL INCLUYE UN BUCLE DE REALIMENTACION EN EL QUE UNA DIFERENCIA DE FASE ENTRE LA SEÑAL EN LA TOMA SELECCIONADA Y LA SEÑAL DE ENTRADA, ES UTILIZADA PARA CAMBIAR UN COMPUTO DE UN CONTADOR ASCENDENTE/DESCENDENTE. UN MULTIPLEXADOR SELECTOR DE TOMAS PROPORCIONA UNA SALIDA DESDE TOMAS ESPECIFICADAS EN RESPUESTA A VALORES PARTICULARES DEL COMPUTO.
ES8903904A 1988-11-17 1989-11-16 Descodificador digital de manipulacion por desplazamiento de fase diferencial. Expired - Lifetime ES2019497A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/272,393 US4965810A (en) 1988-11-17 1988-11-17 Digital differential phase-shift keyed decoder

Publications (1)

Publication Number Publication Date
ES2019497A6 true ES2019497A6 (es) 1991-06-16

Family

ID=23039611

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8903904A Expired - Lifetime ES2019497A6 (es) 1988-11-17 1989-11-16 Descodificador digital de manipulacion por desplazamiento de fase diferencial.

Country Status (8)

Country Link
US (1) US4965810A (es)
EP (1) EP0444114A1 (es)
JP (1) JPH03505959A (es)
AU (1) AU4643989A (es)
CA (1) CA2001341A1 (es)
ES (1) ES2019497A6 (es)
IL (1) IL92147A0 (es)
WO (1) WO1990006031A1 (es)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0779363B2 (ja) * 1990-06-29 1995-08-23 三菱電機株式会社 遅延検波回路
US5142287A (en) * 1990-07-16 1992-08-25 Allied-Signal Inc. Technique for demodulating and decoding mls dpsk transmissions using a digital signal processor
US5067139A (en) * 1990-12-17 1991-11-19 Motorola, Inc. Coherent detector for QPSK modulation in a TDMA system
IL98730A (en) * 1991-07-04 1994-02-27 Technion Res & Dev Foundation Method and device for removing modulation especially KSPD of signals in the method
JP2850942B2 (ja) * 1994-07-13 1999-01-27 日本電気株式会社 復調器
JP3166494B2 (ja) * 1994-07-27 2001-05-14 松下電器産業株式会社 遅延検波方法および装置
US6930524B2 (en) * 2001-10-09 2005-08-16 Micron Technology, Inc. Dual-phase delay-locked loop circuit and method
US6759911B2 (en) 2001-11-19 2004-07-06 Mcron Technology, Inc. Delay-locked loop circuit and method using a ring oscillator and counter-based delay
US7162000B2 (en) * 2002-01-16 2007-01-09 Motorola, Inc. Delay locked loop synthesizer with multiple outputs and digital modulation
US6621316B1 (en) 2002-06-20 2003-09-16 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line
US6727740B2 (en) 2002-08-29 2004-04-27 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
DE10314808B4 (de) * 2003-04-01 2014-09-25 Intel Mobile Communications GmbH Abtastzeitbestimmung beim Empfang höherwertig frequenz- oder phasenmodulierter Empfangssignale durch Korrelationsverfahren
US6937076B2 (en) * 2003-06-11 2005-08-30 Micron Technology, Inc. Clock synchronizing apparatus and method using frequency dependent variable delay
US7130226B2 (en) * 2005-02-09 2006-10-31 Micron Technology, Inc. Clock generating circuit with multiple modes of operation
WO2007030860A1 (en) 2005-09-12 2007-03-22 Magellan Technology Pty Ltd A method and apparatus adapted to demodulate a data signal
JP2007235346A (ja) * 2006-02-28 2007-09-13 Icom Inc 角度復調装置、位相補正装置、角度復調方法、位相補正方法及びプログラム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906380A (en) * 1974-04-16 1975-09-16 Rixon Phase demodulator with phase shifted reference carrier
US4064361A (en) * 1975-12-31 1977-12-20 Bell Telephone Laboratories, Incorporated Correlative timing recovery in digital data transmission systems
US4229824A (en) * 1978-07-21 1980-10-21 Cubic Corporation Method and apparatus for synchronizing electrical signals
US4379266A (en) * 1980-04-03 1983-04-05 Ford Aerospace & Communications Corporation PSK Demodulator with automatic compensation of delay induced phase shifts
JPS58161555A (ja) * 1982-03-19 1983-09-26 Fujitsu Ltd 遅延検波回路
JPS6182552A (ja) * 1984-09-29 1986-04-26 Toshiba Corp 受信周波数安定化装置
JP2592795B2 (ja) * 1985-05-24 1997-03-19 キヤノン株式会社 情報データ復調装置
US4769816A (en) * 1985-11-08 1988-09-06 Raytheon Company Qpsk demodulator
CA1267935A (en) * 1986-07-21 1990-04-17 Sumitomo Electric Industries, Ltd. Psk modem system with improved demodulation reliability

Also Published As

Publication number Publication date
JPH03505959A (ja) 1991-12-19
WO1990006031A1 (en) 1990-05-31
EP0444114A1 (en) 1991-09-04
US4965810A (en) 1990-10-23
AU4643989A (en) 1990-06-12
IL92147A0 (en) 1990-07-12
CA2001341A1 (en) 1990-05-17

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19981001