EP4690277A1 - Segmented transistor active region for enhanced thermal conductivity - Google Patents

Segmented transistor active region for enhanced thermal conductivity

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Publication number
EP4690277A1
EP4690277A1 EP24720352.4A EP24720352A EP4690277A1 EP 4690277 A1 EP4690277 A1 EP 4690277A1 EP 24720352 A EP24720352 A EP 24720352A EP 4690277 A1 EP4690277 A1 EP 4690277A1
Authority
EP
European Patent Office
Prior art keywords
intermediate layers
channels
epitaxially growing
cap layer
nanowire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP24720352.4A
Other languages
German (de)
French (fr)
Inventor
Caroline REILLY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of EP4690277A1 publication Critical patent/EP4690277A1/en
Pending legal-status Critical Current

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    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H10D30/435—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels having multiple laterally adjacent 1D material channels
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/226—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for HF amplifiers

Definitions

  • the present disclosure relates to semiconductor devices and to a segmented transistor active region for enhanced thermal conductivity.
  • a radio frequency (RF) transistor is a semiconductor device used to amplify and switch electronic signals.
  • An RF transformer can be seated between two or more circuits and can use changes of electric signals and the principle of induction in a conductor to produce a varying magnetic field (flux) that couples energy through to another conductor.
  • a semiconductor device includes a miscut substrate, intermediate layers epitaxially grown on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, segmented active regions including nano wire channels, each of which is epitaxially grown on a corresponding one of the surface steps and a cap layer epitaxially grown on the nanowire channels and exposed portions of the uppermost surface.
  • cross-sectional shapes of the segmented active regions are one or more of triangular, square, rectangular and trapezoidal and the intermediate layers and the nanowire channels have various crystallographic orientations including at least one or more of N-polar, Ga-polar, m-plane and semipolar.
  • the intermediate layers, the cap layer and the nanowire channels each include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
  • source and drain regions are disposed in electrical communication with opposite ends of each of the nanowire channels and a gate structure is disposed between the source and drain regions and about each of the nano wire channels.
  • a method of building a semiconductor device includes providing a miscut substrate, epitaxially growing intermediate layers on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
  • materials of the epitaxially growing of the intermediate layers, the cap layer and the nano wire channels include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof and precursor materials include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
  • the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer is continuous. [0014] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
  • the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
  • the method further includes disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
  • a method of building a semiconductor device includes providing a planarized substrate, epitaxially growing intermediate layers on the planarized substrate, forming surface steps in an uppermost surface of the intermediate layers, epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
  • the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes metalorganic chemical vapor deposition (CVD).
  • CVD metalorganic chemical vapor deposition
  • materials of the epitaxially growing of the intermediate layers, the cap layer and the nano wire channels include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof and precursor materials include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
  • the epitaxially growing of the nano wire channels and the cap layer is continuous.
  • the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
  • the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
  • the method further includes disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
  • FIG. 1A is an axial view of a semiconductor device in accordance with embodiments
  • FIG. IB is an enlarged view of a surface of a miscut substrate of the semiconductor device of FIG. 1A, which is encircled by the dashed line, in accordance with embodiments;
  • FIG. 2A is a side view of the semiconductor device of FIG. 1 A in accordance with embodiments
  • FIG. 2B is an enlarged view of a surface of a miscut substrate of the semiconductor device of FIG. 2A, which is encircled by the dashed line, in accordance with embodiments;
  • FIG. 3 is a top-down view of the semiconductordevice of FIG. 1A without a cap layer in accordance with embodiments;
  • FIG. 4 is a schematic cross-sectional view of a triangular nanowire channel in accordance with embodiments
  • FIG. 5 is a schematic cross-sectional view of a square nanowire channel in accordance with embodiments
  • FIG. 6 is a schematic cross-sectional view of a rectangular nanowire channel in accordance with embodiments.
  • FIG. 7 is a schematic cross-sectional view of a trapezoidal nanowire channel in accordance with embodiments.
  • FIG. 8 is an axial view of a semiconductor device with multiple layers of segmented active regions and nano wire channels in accordance with embodiments;
  • FIG. 9 is a flow diagram illustrating a method of building a semiconductor device with a miscut substrate in accordance with embodiments.
  • FIG. 10 is a flow diagram illustrating a method of building a semiconductor device with a planarized substrate and a surface step forming operation in accordance with embodiments.
  • GaN gallium nitride
  • HEMT high electron mobility transistor
  • a semiconductor device such as an RF transistor device
  • a segmented active region in which interfaces between buffer and cap layers are removed to allow for more effective heat transfer through the semiconductor device.
  • This structure can be applied to a variety of material combinations and crystal orientations. Active region segmentation can be achieved through self-assembled nanowire growth on vicinal substrates, where the surface steps naturally provide segmentation. This creates a truncated two-dimensional electron gas (2DEG) which may be considered a 1DEG with channel conduction parallel to the source-drain.
  • 2DEG truncated two-dimensional electron gas
  • a semiconductor device (hereinafter referred to as an exemplary “RF transistor device”) 101 is provided and includes a miscut substrate 110, which has an uppermost surface 111 with miscut sections 112 that are angled relative to the horizontal plane P (i.e., by about 2°-4°), intermediate layers 120, segmented active regions 130 and a cap layer 140.
  • the intermediate layers 120 are epitaxially grown on the uppermost surface 111 of the miscut substrate 110 such that the formations of the miscut sections 112 cause the intermediate layers 120 to grow in such a manner that an uppermost surface 121 of the intermediate layers 120 includes surface steps 122.
  • the surface steps 122 generally mimic the formation of the miscut sections 112. In this way, the surface steps 122 can be regarded as a vicinal substrate whose surface at the surface steps deviates from a major crystallographic axis.
  • the segmented active regions 130 can be provided as one of fully strained, partially relaxed and fully relaxed and can include nanowire channels 131. Each of the nano wire channels 131 is epitaxially grown or self-assembled on a corresponding one of the surface steps 122, which results in each of the nanowire channels 131 having a particular cross-sectional shape (see FIGS. 4, 5, 6 and 7).
  • the cap layer 140 is epitaxially grown on the nanowire channels 131 and on exposed portions of the uppermost surface 121.
  • materials of the intermediate layers 120, the segmented active regions 130, the nanowire channels 131 and the cap layer 140 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
  • the RF transistor device 101 can further include source and drain regions 150 and 151, which are disposed in electrical communication with opposite ends of each of the segmented active regions 130 and each of the nano wire channels 131, and a gate structure 152.
  • the gate structure 152 is disposed between the source and drain regions 150 and 151 and about each of the segmented active regions 130 and each of the nanowire channels 131.
  • the miscut substrate 110 can be reformulated as a planarized substrate. In these or other cases, the surface steps 122 of the uppermost surface 121 can be etched or machined into the uppermost surface 121. This will result in a same overall configuration of the segmented active regions 130 and the nanowire channels 131 as that described above.
  • the RF transistor device 101 is characterized in that it has an absence of high thermal boundary resistance between the uppermost surface 121 of the intermediate layers 120 and the cap layer 140. As such, heat from the nanowire channels 131 is met with little or substantially reduced resistance after transferring to the surrounding materials and a resulting temperature of the RF transistor device 101 can be reduced.
  • This heat transfer characteristic will be present in cases in which the intermediate layers 120 and the cap layer 140 are formed of similar materials, such as aluminum nitride, and the nano wire channels 131 are formed of gallium nitride and/or or when the intermediate layers 120 and the cap layer 140 are formed of differing materials. In the cases in which the intermediate layers 120 and the cap layer 140 are formed of differing materials, there remains fewer interfaces as compared to a situation in which the active region is not segmented.
  • the intermediate layers 120 and the nanowire channels 131 can have various crystallographic orientations owing to the formation of the miscut sections 112 of the miscut substrate 110 or where the intermediate layers 120 and the nanowire channels 131 are formed on a semipolar substrate that shows large surface steps. Th various crystallographic orientations can include, but are not limited to, one or more of N-polar, Ga-polar, m-plane and semipolar.
  • the cross-sectional shapes of the segmented active regions 130 and the nanowire channels 131 can be one or more of triangular 401, square 501, rectangular 601 and trapezoidal 701 or other regular or irregular shapes.
  • the segmented active regions 130 and the nano wire channels 131 can be provided in multiple layers 801, 802, ..., 80N. Numbers of the multiple layers can be increased or decreased to satisfy various requirements of the RF transistor device 101.
  • a method 900 of building an RF transistor device such as the RF transistor device 101 described above, is provided.
  • the method 900 includes providing a miscut substrate (block 901), epitaxially growing intermediate layers on the miscut substrate such that an uppermost surface of the intermediate layers comprises surface steps (block 902), epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions (block 903) and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface (block 904).
  • the method 900 can further include disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels (block 905) and disposing a gate structure between the source and drain regions and about each of the nano wire channels (block 906).
  • the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 902, 903 and 904 can be conducted via metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy and can be executed in a continuous manner.
  • Such continuous epitaxial growth can be enabled by switching between precursor materials without removal of wafer material from the growth chamber and proceeding with epitaxial growth without stopping or at least without stopping for any significant amount of time.
  • the continuous epitaxial growth contributes significantly to the absence of impurities at the interface associated with removal of the wafer from the growth chamber, which is often done when having to pattern the material. These impurities reduce the performance of the device.
  • materials used in the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 902, 903 and 904 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
  • Precursor materials can include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
  • the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 902, 903 and 904 can include one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
  • the epitaxially growing of the nanowire channels of block 903 can be executed such that the segmented active regions and the nano wire channels are provided in multiple layers.
  • a method 1000 of building an RF transistor device such as the RF transistor device 101 described above, is provided.
  • the method 900 includes providing a planarized substrate (block 1001), epitaxially growing intermediate layers on the planarized substrate (block 1002) and forming surface steps in an uppermost surface of the intermediate layers (block 1003) by one of etching and machining.
  • the method 1000 further includes epitaxially growing nano wire channels, with each nano wire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions (block 1004) and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface (block 1005).
  • the method 1000 can further include disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels (block 1006) and disposing a gate structure between the source and drain regions and about each of the nanowire channels (block 1007).
  • the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 1002, 1004 and 1005 can be conducted via metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy and can be executed in a continuous manner. Such continuous epitaxial growth can be enabled by switching between precursor materials without removal of wafer material from the growth chamber and proceeding with epitaxial growth without stopping or at least without stopping for any significant amount of time.
  • materials used in the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 1002, 1004 and 1005 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
  • Precursor materials can include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
  • the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 1002, 1004 and 1005 can include one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
  • the epitaxially growing of the nanowire channels of block 1004 can be executed such that the segmented active regions and the nanowire channels are provided in multiple layers.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device is provided and includes a miscut substrate, intermediate layers epitaxially grown on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, segmented active regions including nanowire channels, each of which is epitaxially grown on a corresponding one of the surface steps and a cap layer epitaxially grown on the nanowire channels and exposed portions of the uppermost surface.

Description

SEGMENTED TRANSISTOR ACTIVE REGION FOR ENHANCED THERMAL
CONDUCTIVITY
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Application No. 18/191,954, filed on March 29, 2023, which is incorporated herein by reference in its entirety.
BACKGROUND
[0001] The present disclosure relates to semiconductor devices and to a segmented transistor active region for enhanced thermal conductivity.
[0002] A radio frequency (RF) transistor is a semiconductor device used to amplify and switch electronic signals. An RF transformer can be seated between two or more circuits and can use changes of electric signals and the principle of induction in a conductor to produce a varying magnetic field (flux) that couples energy through to another conductor.
[0003] In operation, RF transistors tend to heat up, which reduces a device lifetime. Therefore, a need remains for RF transistors that do not exhibit self-heating.
SUMMARY
[0004] According to an aspect of the disclosure, a semiconductor device is provided and includes a miscut substrate, intermediate layers epitaxially grown on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, segmented active regions including nano wire channels, each of which is epitaxially grown on a corresponding one of the surface steps and a cap layer epitaxially grown on the nanowire channels and exposed portions of the uppermost surface.
[0005] In accordance with additional or alternative embodiments, there is an absence of high thermal boundary resistance between the nanowire channels, the intermediate layers and the cap layer.
[0006] In accordance with additional or alternative embodiments, cross-sectional shapes of the segmented active regions are one or more of triangular, square, rectangular and trapezoidal and the intermediate layers and the nanowire channels have various crystallographic orientations including at least one or more of N-polar, Ga-polar, m-plane and semipolar.
[0007] In accordance with additional or alternative embodiments, the intermediate layers, the cap layer and the nanowire channels each include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
[0008] In accordance with additional or alternative embodiments, the segmented active regions are provided in multiple layers.
[0009] In accordance with additional or alternative embodiments, source and drain regions are disposed in electrical communication with opposite ends of each of the nanowire channels and a gate structure is disposed between the source and drain regions and about each of the nano wire channels.
[0010] According to an aspect of the disclosure, a method of building a semiconductor device is provided. The method includes providing a miscut substrate, epitaxially growing intermediate layers on the miscut substrate such that an uppermost surface of the intermediate layers includes surface steps, epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
[0011] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes metalorganic chemical vapor deposition (CVD).
[0012] In accordance with additional or alternative embodiments, materials of the epitaxially growing of the intermediate layers, the cap layer and the nano wire channels include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof and precursor materials include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
[0013] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer is continuous. [0014] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
[0015] In accordance with additional or alternative embodiments, the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
[0016] In accordance with additional or alternative embodiments, the method further includes disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
[0017] According to an aspect of the disclosure, a method of building a semiconductor device is provided. The method includes providing a planarized substrate, epitaxially growing intermediate layers on the planarized substrate, forming surface steps in an uppermost surface of the intermediate layers, epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
[0018] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes metalorganic chemical vapor deposition (CVD).
[0019] In accordance with additional or alternative embodiments, materials of the epitaxially growing of the intermediate layers, the cap layer and the nano wire channels include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof and precursor materials include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
[0020] In accordance with additional or alternative embodiments, at least the epitaxially growing of the nano wire channels and the cap layer is continuous. [0021] In accordance with additional or alternative embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer includes one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth.
[0022] In accordance with additional or alternative embodiments, the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
[0023] In accordance with additional or alternative embodiments, the method further includes disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
[0024] Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed technical concept. For a better understanding of the disclosure with the advantages and the features, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0025] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts:
[0026] FIG. 1A is an axial view of a semiconductor device in accordance with embodiments;
[0027] FIG. IB is an enlarged view of a surface of a miscut substrate of the semiconductor device of FIG. 1A, which is encircled by the dashed line, in accordance with embodiments;
[0028] FIG. 2A is a side view of the semiconductor device of FIG. 1 A in accordance with embodiments;
[0029] FIG. 2B is an enlarged view of a surface of a miscut substrate of the semiconductor device of FIG. 2A, which is encircled by the dashed line, in accordance with embodiments; [0030] FIG. 3 is a top-down view of the semiconductordevice of FIG. 1A without a cap layer in accordance with embodiments;
[0031] FIG. 4 is a schematic cross-sectional view of a triangular nanowire channel in accordance with embodiments;
[0032] FIG. 5 is a schematic cross-sectional view of a square nanowire channel in accordance with embodiments
[0033] FIG. 6 is a schematic cross-sectional view of a rectangular nanowire channel in accordance with embodiments;
[0034] FIG. 7 is a schematic cross-sectional view of a trapezoidal nanowire channel in accordance with embodiments;
[0035] FIG. 8 is an axial view of a semiconductor device with multiple layers of segmented active regions and nano wire channels in accordance with embodiments;
[0036] FIG. 9 is a flow diagram illustrating a method of building a semiconductor device with a miscut substrate in accordance with embodiments; and
[0037] FIG. 10 is a flow diagram illustrating a method of building a semiconductor device with a planarized substrate and a surface step forming operation in accordance with embodiments.
DETAILED DESCRIPTION
[0038] Semiconductor devices, such as transistors for RF applications often require higher power densities under higher frequency operation. During such higher power density operation, device lifetimes tend to drop due to device self-heating phenomena. To maintain high device lifetimes, active region temperatures need to be reduced. In gallium nitride (GaN) high electron mobility transistors (HEMTs), for example, the device includes epitaxial layers/sheets whose interfaces have high thermal boundary resistances which contribute to elevated temperatures of active regions. As such, in HEMTs, reduction of active region temperatures remains a challenge.
[0039] Thus, as will be described below, a semiconductor device, such as an RF transistor device, is provided with a segmented active region in which interfaces between buffer and cap layers are removed to allow for more effective heat transfer through the semiconductor device. This structure can be applied to a variety of material combinations and crystal orientations. Active region segmentation can be achieved through self-assembled nanowire growth on vicinal substrates, where the surface steps naturally provide segmentation. This creates a truncated two-dimensional electron gas (2DEG) which may be considered a 1DEG with channel conduction parallel to the source-drain.
[0040] With reference to FIGS. 1A and IB, FIGS. 2A and 2B and FIG. 3, a semiconductor device (hereinafter referred to as an exemplary “RF transistor device”) 101 is provided and includes a miscut substrate 110, which has an uppermost surface 111 with miscut sections 112 that are angled relative to the horizontal plane P (i.e., by about 2°-4°), intermediate layers 120, segmented active regions 130 and a cap layer 140. The intermediate layers 120 are epitaxially grown on the uppermost surface 111 of the miscut substrate 110 such that the formations of the miscut sections 112 cause the intermediate layers 120 to grow in such a manner that an uppermost surface 121 of the intermediate layers 120 includes surface steps 122. The surface steps 122 generally mimic the formation of the miscut sections 112. In this way, the surface steps 122 can be regarded as a vicinal substrate whose surface at the surface steps deviates from a major crystallographic axis. The segmented active regions 130 can be provided as one of fully strained, partially relaxed and fully relaxed and can include nanowire channels 131. Each of the nano wire channels 131 is epitaxially grown or self-assembled on a corresponding one of the surface steps 122, which results in each of the nanowire channels 131 having a particular cross-sectional shape (see FIGS. 4, 5, 6 and 7). The cap layer 140 is epitaxially grown on the nanowire channels 131 and on exposed portions of the uppermost surface 121.
[0041] In accordance with embodiments, materials of the intermediate layers 120, the segmented active regions 130, the nanowire channels 131 and the cap layer 140 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
[0042] As shown in FIG. 3, the RF transistor device 101 can further include source and drain regions 150 and 151, which are disposed in electrical communication with opposite ends of each of the segmented active regions 130 and each of the nano wire channels 131, and a gate structure 152. The gate structure 152 is disposed between the source and drain regions 150 and 151 and about each of the segmented active regions 130 and each of the nanowire channels 131. [0043] In accordance with embodiments, the miscut substrate 110 can be reformulated as a planarized substrate. In these or other cases, the surface steps 122 of the uppermost surface 121 can be etched or machined into the uppermost surface 121. This will result in a same overall configuration of the segmented active regions 130 and the nanowire channels 131 as that described above.
[0044] With the construction described above, the RF transistor device 101 is characterized in that it has an absence of high thermal boundary resistance between the uppermost surface 121 of the intermediate layers 120 and the cap layer 140. As such, heat from the nanowire channels 131 is met with little or substantially reduced resistance after transferring to the surrounding materials and a resulting temperature of the RF transistor device 101 can be reduced. This heat transfer characteristic will be present in cases in which the intermediate layers 120 and the cap layer 140 are formed of similar materials, such as aluminum nitride, and the nano wire channels 131 are formed of gallium nitride and/or or when the intermediate layers 120 and the cap layer 140 are formed of differing materials. In the cases in which the intermediate layers 120 and the cap layer 140 are formed of differing materials, there remains fewer interfaces as compared to a situation in which the active region is not segmented.
[0045] With additional reference to FIGS. 4-7, the intermediate layers 120 and the nanowire channels 131 can have various crystallographic orientations owing to the formation of the miscut sections 112 of the miscut substrate 110 or where the intermediate layers 120 and the nanowire channels 131 are formed on a semipolar substrate that shows large surface steps. Th various crystallographic orientations can include, but are not limited to, one or more of N-polar, Ga-polar, m-plane and semipolar. In any case, due to the nanowire channels 131 being epitaxially grown or self-assembled on the surface steps 122 of the uppermost surface 121, the cross-sectional shapes of the segmented active regions 130 and the nanowire channels 131 can be one or more of triangular 401, square 501, rectangular 601 and trapezoidal 701 or other regular or irregular shapes.
[0046] With reference to FIG. 8 and in accordance with further embodiments, the segmented active regions 130 and the nano wire channels 131 can be provided in multiple layers 801, 802, ..., 80N. Numbers of the multiple layers can be increased or decreased to satisfy various requirements of the RF transistor device 101. [0047] With reference to FIG. 9, a method 900 of building an RF transistor device, such as the RF transistor device 101 described above, is provided. The method 900 includes providing a miscut substrate (block 901), epitaxially growing intermediate layers on the miscut substrate such that an uppermost surface of the intermediate layers comprises surface steps (block 902), epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions (block 903) and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface (block 904).
[0048] The method 900 can further include disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels (block 905) and disposing a gate structure between the source and drain regions and about each of the nano wire channels (block 906).
[0049] In accordance with embodiments, the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 902, 903 and 904 can be conducted via metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy and can be executed in a continuous manner. Such continuous epitaxial growth can be enabled by switching between precursor materials without removal of wafer material from the growth chamber and proceeding with epitaxial growth without stopping or at least without stopping for any significant amount of time. The continuous epitaxial growth contributes significantly to the absence of impurities at the interface associated with removal of the wafer from the growth chamber, which is often done when having to pattern the material. These impurities reduce the performance of the device.
[0050] In accordance with further embodiments, materials used in the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 902, 903 and 904 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof. Precursor materials can include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
[0051] The epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 902, 903 and 904 results in a self-assembled formation of a segmented channel region that would otherwise need to be formed via a process of etching or regrowth. Those conventional processes would tend to introduce damage and/or impurities near sensitive portions of the device and thus degrade performance.
[0052] In accordance with embodiments, the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 902, 903 and 904 can include one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth. In addition, the epitaxially growing of the nanowire channels of block 903 can be executed such that the segmented active regions and the nano wire channels are provided in multiple layers.
[0053] With reference to FIG. 10, a method 1000 of building an RF transistor device, such as the RF transistor device 101 described above, is provided. The method 900 includes providing a planarized substrate (block 1001), epitaxially growing intermediate layers on the planarized substrate (block 1002) and forming surface steps in an uppermost surface of the intermediate layers (block 1003) by one of etching and machining. The method 1000 further includes epitaxially growing nano wire channels, with each nano wire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions (block 1004) and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface (block 1005).
[0054] The method 1000 can further include disposing source and drain regions in electrical communication with opposite ends of each of the nanowire channels (block 1006) and disposing a gate structure between the source and drain regions and about each of the nanowire channels (block 1007). In accordance with embodiments, the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 1002, 1004 and 1005 can be conducted via metalorganic chemical vapor deposition or metalorganic vapor phase epitaxy and can be executed in a continuous manner. Such continuous epitaxial growth can be enabled by switching between precursor materials without removal of wafer material from the growth chamber and proceeding with epitaxial growth without stopping or at least without stopping for any significant amount of time. The continuous epitaxial growth contributes significantly to the absence of impurities at the interface associated with removal of the wafer from the growth chamber, which is often done when having to pattern the material. These impurities reduce the performance of the device. [0055] In accordance with further embodiments, materials used in the epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 1002, 1004 and 1005 can include at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof. Precursor materials can include at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
[0056] The epitaxially growing of the intermediate layers, the nano wire channels and the cap layer of blocks 1002, 1004 and 1005 results in a self-assembled formation of a segmented channel region that would otherwise need to be formed via a process of etching or regrowth. Those conventional processes would tend to introduce damage and/or impurities near sensitive portions of the device and thus degrade performance..
[0057] In accordance with embodiments, the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer of blocks 1002, 1004 and 1005 can include one or more of N-polar growth, Ga-polar growth, m-plane growth and semipolar growth. In addition, the epitaxially growing of the nanowire channels of block 1004 can be executed such that the segmented active regions and the nanowire channels are provided in multiple layers.
[0058] Technical effects and benefits of the present disclosure are the provision of an RF transistor device in which heat can be transferred between the buffer and cap layers without an interfacial thermal boundary resistance. Also, multiple parallel conducting channels are created in-plane, with increased thermal conductivity in the vertical direction. By removing interfaces, heat can be dissipated relatively rapidly, and device operating temperatures will tend to decrease thus increasing device lifetimes. This in turn allows for higher power densities while maintaining lifetime metrics in RF applications.
[0059] The corresponding structures, materials, acts, and equivalents of all means or step-plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the technical concepts in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
[0060] While the preferred embodiments to the disclosure have been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the disclosure first described.

Claims

CLAIMS What is claimed is:
1. A semiconductor device, comprising: a miscut substrate; intermediate layers epitaxially grown on the miscut substrate such that an uppermost surface of the intermediate layers comprises surface steps; segmented active regions comprising nanowire channels, each of which is epitaxially grown on a corresponding one of the surface steps; and a cap layer epitaxially grown on the nanowire channels and exposed portions of the uppermost surface.
2. The semiconductor device according to claim 1, wherein there is an absence of high thermal boundary resistance between the nanowire channels, the intermediate layers and the cap layer.
3. The semiconductor device according to claim 1, wherein: cross-sectional shapes of the segmented active regions are one or more of triangular, square, rectangular and trapezoidal, and the intermediate layers and the nanowire channels have various crystallographic orientations comprising at least one or more of N-polar, Ga-polar, m-plane and semipolar.
4. The semiconductor device according to claim 1, wherein the intermediate layers, the cap layer and the nanowire channels each comprise at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof.
5. The semiconductor device according to claim 1, wherein the segmented active regions are provided in multiple layers.
6. The semiconductor according to claim 1, further comprising: source and drain regions disposed in electrical communication with opposite ends of each of the nano wire channels; and a gate structure disposed between the source and drain regions and about each of the nano wire channels.
7. A method of building a semiconductor device, the method comprising: providing a miscut substrate; epitaxially growing intermediate layers on the miscut substrate such that an uppermost surface of the intermediate layers comprises surface steps; epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions; and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
8. The method according to claim 7, wherein the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer comprises metalorganic chemical vapor deposition (CVD).
9. The method according to claim 7, wherein: materials of the epitaxially growing of the intermediate layers, the cap layer and the nanowire channels comprise at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof, and precursor materials comprise at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
10. The method according to claim 7, wherein the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer is continuous.
11. The method according to claim 7, wherein the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer comprises one or more of bipolar growth, Ga-polar growth, m-plane growth and semipolar growth.
12. The method according to claim 7, wherein the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
13. The method according to claim 7, further comprising: disposing source and drain regions in electrical communication with opposite ends of each of the nano wire channels; and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
14. A method of building a semiconductor device, the method comprising: providing a planarized substrate; epitaxially growing intermediate layers on the planarized substrate; forming surface steps in an uppermost surface of the intermediate layers; epitaxially growing nanowire channels, with each nanowire channel being epitaxially grown on a corresponding one of the surface steps to form segmented active regions; and epitaxially growing a cap layer on the nanowire channels and exposed portions of the uppermost surface.
15. The method according to claim 14, wherein the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer comprises metalorganic chemical vapor deposition (CVD).
16. The method according to claim 14, wherein: materials of the epitaxially growing of the intermediate layers, the cap layer and the nanowire channels comprise at least one or more of aluminum nitride, gallium nitride, indium nitride, aluminum gallium nitride and alloys thereof and indium gallium nitride and alloys thereof, and precursor materials comprise at least one or more of trimethylaluminium, trimethylgallium, triethylgallium, trimethylindium, triethylindium, ammonia, hydrazine, and dimethylhydrazine .
17. The method according to claim 14, wherein at least the epitaxially growing of the nano wire channels and the cap layer is continuous.
18. The method according to claim 14, wherein the epitaxially growing of the intermediate layers, the nanowire channels and the cap layer comprises one or more of bipolar growth, Ga-polar growth, m-plane growth and semipolar growth.
19. The method according to claim 14, wherein the epitaxially growing of the nanowire channels is executed such that the segmented active regions are provided in multiple layers.
20. The method according to claim 14, further comprising: disposing source and drain regions in electrical communication with opposite ends of each of the nano wire channels; and disposing a gate structure between the source and drain regions and about each of the nano wire channels.
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