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Definitions

• the invention relates to the production of so-called vertical microelectronic components, based on an III-N material.
• the invention finds for example for application the field of vertical power components such as power transistors, or power diodes.
• nitride based on an III-N material for example a layer of gallium nitride (GaN), present on two opposite faces of the electrodes .
• GaN gallium nitride
• the power component is a MOS (metal-oxide-semiconductor) transistor.
• a layer 550 of an III-N material forms a stack of layers having different dopings. It may for example be a stack of layers 554, 553, 552, 551 having the following n+/p-/n-/n+ dopings and successively arranged from a first face 550A (also designated front face) and up to to one second side 550B (also referred to as the back side) of the III-N material.
• Electrodes 10, 30 are located on the front side 550A and an electrode 20 is located on the back side 550B of the III-N layer 550.
• the electrodes 10, 30 correspond respectively to the source and to the gate of the transistor, the electrode 20 corresponding to the drain. Since the electrodes are located on two opposite faces 550, 550 of the material 550, the current flows vertically throughout the volume of the material and the blocking resistance of the component is correlated to the thickness of this material.
• III-N material such as GaN makes it possible to increase the power density and the voltage withstand of the components (typically 900V to 5kV) compared to a lateral GaN component or a vertical silicon component.
• a thickness of 8 ⁇ m of GaN doped at 2x10 16 cm' 3 is sufficient to withstand a voltage of 1200V when a thickness of 100 ⁇ m of silicon doped at 1.3x10 14 cm' 3 is required for a vertical component of the same structure.
• GaN is a wide gap material perfectly suited for power components. This material thus brings considerable advantages for vertical components such as pin diode, Schottky diode, and for transistors of the type:
• a GaN-based vertical MOSFET transistor architecture is for example described in the following publications: Ch. Gupta et al. IEEE EDL (2016) 37 p1601, Ray Li et al. IEEE EDL (2016) 37 p1466, Tohru Oka et al. APEX (2015) 8 p054101.
• a GaN-based vertical MOSFET transistor architecture is for example described in the following publications: Min Sun et al. IEEE EDL (2017) 48, p509.
• a GaN-based vertical MOSFET transistor architecture is for example described in the following publications: Daisuke Shibata et al. MEI (2016).
• the layer 550 in III-N material To produce a vertical component in III-N materials which is effective, it is necessary for the layer 550 in III-N material to have intrinsic quality characteristics (resistivity, impurity, number of defects) throughout its thickness.
• silicon (Si) layer To form a silicon (Si) layer, many well-known and inexpensive technologies are available. For example, growth by floating fused zone (usually designated by the acronym FZ) which is purer and which is therefore more suitable for high voltages can be favored than growth by Czochralski (Cz) pulling.
• FZ floating fused zone
• Cz Czochralski
• III-N material for example in gallium nitride (GaN)
• GaN gallium nitride
• GaN-based structures on an Si or SiC (silicon carbide) substrate is feasible but induces much too high dislocation densities for the application to the vertical power transistor.
• GaN pseudosubstrates usually referred to as template or freestanding. These GaN pseudo-substrates are available in four-inch format. These GaN substrates are still very expensive and only available in very small formats, typically two inches.
• Another objective of the present invention consists in proposing a solution for producing this type of component with a cost price which remains limited and in formats compatible with the constraints of industrial productivity.
• a method for producing a so-called vertical microelectronic component comprising at least one layer based on an III-N material comprising the following successive steps:
• - providing a stack comprising a plurality of pads extending from a base substrate, the pads being distributed over the base substrate so as to form several sets of pads, at least some of the pads of the set comprising at least:
• a creep section formed from a material having a glass transition temperature Tt vitreous ra nsition, the crystalline section surmounting the creep section,
• the method comprises at least one step of doping the III-N material of the vignettes so that at least some of the vignettes comprise at least:
• n+, n- and p doping types a second layer based on the III-N material and which has a second doping taken from the n+, n- and p doping types.
• the types of the first and second dopings being different.
• the first and second layers are stacked in the thumbnail, in a so-called vertical direction, between a first face and a second face of the thumbnail.
• the method further comprises at least the production of a first electrode and the production of a second electrode located on the thumbnail and configured so that a current passing from one electrode to the other passes through at least the second layer in its entire thickness e552, the thickness e552 being taken along said vertical direction.
• the proposed method provides for the production of vignettes of III-N material (GaN for example) from sets of pads etched in a stack and comprising a crystalline layer intended for the epitaxy of the III-N material and a layer of creep.
• III-N material GaN for example
• the crystallites formed at the top of the pads of the same set of pads come together to form a vignette, each of the vignettes being intended to form the layer of III-N material of a vertical component.
• the use of these networks of plots makes it possible to form by epitaxy vignettes of III-N material without or with few dislocations.
• the use of sets of pads makes it possible to take advantage of the creep properties of certain materials of the pads at the epitaxy temperature in order to align the crystallites of III-N material which grow by pendeo-epitaxy from adjacent plots until forming the thumbnails, this without forming any coalescence defects.
• the portion of the pad which is formed by the creep section reaches (or exceeds) its glass transition temperature or a temperature very close to the latter. Under the force of a mechanical stress, this portion of the stud can thus deform.
• the mechanical stresses generated by this contact are transferred to the studs and therefore to the creep sections.
• the latter deform, thereby absorbing some or all of the mechanical stresses. It is thus possible to considerably reduce, or even avoid, the appearance and propagation of dislocations at the level of the coalescence joints between the crystallites which form a vignette of III-N material.
• the disorientation between crystallites results in the creation of a grain boundary to coalescence.
• This grain boundary is highly energetic since it results from the superposition of the stress fields of the defects that compose it. If the crystallites grow on pads which can deform as the process described allows, the adjacent crystallites then orient themselves in-plane or out-of-plane to minimize the total energy of the system without the formation of grain boundaries. . On the contrary, if the crystallites grow on pads which cannot deform, there is formation of grain boundaries and therefore the appearance of dislocations.
• the process described offers a solution clearly opposed to all the solutions of the state of the art which provide for delimiting vignettes by etching from an initial common layer obtained by epitaxy.
• the proposed process makes it possible to completely dispense with an etching step to delimit the vignettes.
• the invention is based on a new mode of growth of epitaxial structures and on the direct production by a "bottom-up" process (i.e., from bottom to top) associated with vertical GaN power components.
• the method commonly used consists in carrying out the epitaxy of the structure n- / p / n+ on a full plate substrate of GaN. This epitaxy is then etched to draw the periodic structure of sources on the surface. It is therefore a “top-down” process (ie, from top to bottom). The drain is taken from the rear face of the GaN substrate. The grids are located in the engraved parts. The depletion in the p-GaN takes place at the level of the surfaces which have been etched.
• the claimed process proposes a solution which is radically different from the known solutions, since this claimed process makes it possible to completely dispense with this penalizing etching step for the load transport properties of vertical structures.
• the thickness of the stack of layers of III-N material can easily be greater than 8 ⁇ m, or even 10 ⁇ m, or even 12 ⁇ m without showing any dislocations.
• the dislocation density in these GaN vignettes is less than 1 to 2.1 E 8 /cm 2 .
• the surface of the thumbnails is determined by the network of plots.
• the precision of the methods implemented to produce the array of pads will partly determine at least the smallest possible dimension for the vertical components and therefore the density of these components in a circuit.
• nanoimprint nanometric printing
• e-beam electron beam lithography
• this method makes it possible to directly produce vertical components, each having a size corresponding to the initial size of the thumbnail.
• the proposed process thus makes it possible to obtain vignettes with a reduced rate of dislocations, high thicknesses and small surfaces. This method is therefore particularly advantageous for producing power components with improved performance.
• microelectronic devices or components means any type of device made with microelectronic means. These devices include in particular, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.). It can be a device intended to provide an electronic, optical, mechanical function, etc. It can also be an intermediate product intended solely for the production of another microelectronic device.
• MEMS micromechanical or electromechanical devices
• MOEMS optical or optoelectronic devices
• the proposed method makes it possible to produce the following vertical transistors: MOSFET, FinFET, CAVET, HEMT (acronym for “High Electron Mobility Transistor”, meaning high electron mobility transistor).
• Figure 1 schematically illustrates an example of a vertical component, here a MOSFET transistor, based on an III-N material.
• Figures 2A to 2F illustrate some of the steps of a non-limiting example of a method according to the present invention. At the end of these steps, we obtain vignettes based on an III-N material.
• Figures 3A-3J illustrate steps that can be implemented in the framework of the method according to the present invention to obtain a non-limiting example of a vertical component.
• the steps of Figures 3A to 3J can be implemented after the step of Figure 2F.
• Figure 4 illustrates an example of a thumbnail intended to form vertical components.
• Figures 5A to 5D illustrate examples of vertical components that can be formed from the thumbnail of Figure 4 and by implementing the method according to the invention.
• Figure 6 illustrates another example of a vignette intended to form vertical components.
• Figure 7 illustrates an example of a vertical component that can be formed from the thumbnail of Figure 6 and by implementing the method according to the invention.
• Figure 8 illustrates another example of a vignette intended to form vertical components.
• Figure 9 illustrates an example of a vertical component that can be formed from the thumbnail of Figure 8 and by implementing the method according to the invention.
• FIGS. 10A to 10G illustrate steps that can be implemented within the framework of the method according to the present invention to obtain an example of a vertical component.
• the steps of FIGS. 10A to 10G can be implemented from thumbnails such as that illustrated in FIG. 6 for example.
• FIGS. 11A to 11D illustrate steps that can be implemented within the framework of the method according to the present invention to obtain an example of a vertical component.
• FIGS. 12A to 12E illustrate steps that can be implemented within the framework of the method according to the present invention to obtain an example of a vertical component.
• the steps of FIGS. 12A to 12E can be implemented from thumbnails such as that illustrated in FIG. 6 for example.
• FIGS. 13A to 13G illustrate steps that can be implemented within the framework of the method according to the present invention to obtain an example of a vertical component.
• the steps of FIGS. 13A to 13G can be implemented from thumbnails such as that illustrated in FIG. 6 for example.
• the first layer has a thickness e551 of between 1 and 5 ⁇ m (10-6 meters), preferably between 1 and 3 ⁇ m, preferably of the order of 2 ⁇ m.
• the first layer extends from one side of the sticker to the other.
• the first layer covers the entire surface of the sticker.
• the surface of the sticker is taken in projection on a parallel plane (xy plane) in which the upper face of the substrate mainly extends.
• the first layer has a doping level greater than or equal to 5.10 17 atoms per cubic centimeter (at/cm 3 ).
• the first layer has a doping level preferably of the order of 5 ⁇ 10 18 at/cm 3 .
• the first layer has an n+ type doping. This ensures good quality electrical conduction with the second electrode.
• the second layer extends from one side of the sticker to the other.
• the second layer covers the entire surface of the sticker.
• the surface of the sticker is taken in projection on a parallel plane (xy plane) in which the upper face of the substrate mainly extends.
• the second layer has a thickness e 552 of at least 8 ⁇ m (10'6 meters) and preferably of at least 10 ⁇ m.
• the second layer has a doping level greater than or equal to 1 ⁇ 10 15 at/cm 3 .
• the second layer has a doping level preferably of the order of 1 ⁇ 10 16 at/cm 3 .
• the second layer has an n- type doping.
• the step of doping the III-N material of the vignettes is carried out during the step of forming, on each set, a vignette by epitaxial growth.
• the electrodes are configured so that a current passing from one electrode to the other also passes through the first layer throughout its entire thickness.
• the first and second layers are located between the first electrode and the second electrode.
• one of the first and second electrodes is located on the first face of the label and the other of the first and second electrodes is located on the second face of the label. This allows the current passing from one electrode to the other to pass through the entire thickness of the first and second layers, which considerably improves the performance of the device.
• one of the first and second electrodes is located on the first face of the sticker and the other of the first and second electrodes extends, in the vertical direction, from the first face and up to to the first layer through the second layer.
• the vignettes comprise only the following layers: said first layer and said second layer, the component preferably forming a Schottky type diode.
• the vignettes comprise the following layers: said first layer, said second layer, and a third layer surmounting the second layer and preferably having p-type doping, positioned so that the second layer is located between the first and third layers, the component preferably forming a diode of the p-i-n type or a transistor.
• the third layer has a thickness of at least 100 nm ( 10.9 meters) and preferably less than 1 ⁇ m. Preferably the thickness is between 300 and 700 nm.
• the third layer has a level of chemical doping greater than or equal to 5 ⁇ 10 17 at/cm 3 .
• the third layer has a doping level preferably of the order of 1.10 18 at/cm 3 .
• the third layer has p-type doping.
• the vignettes comprise only the following layers: said first layer, said second layer, and said third layer, the component preferably forming a p-i-n type diode.
• the vignettes comprise the following layers: said first layer, said second layer, said third layer as well as at least a fourth layer surmounting the third layer and preferably having a n+ type doping, the component preferably forming a transistor.
• the first electrode forms a source for the transistors
• the second electrode forms a drain for the transistors
• the method also comprises a step of producing a gate for the transistor.
• the fourth layer 554 has a thickness of at least 50 nm.
• the thickness of the fourth layer is between 50 and 200 nm and preferably around 100 nm.
• the fourth layer has a doping level greater than or equal to 5 ⁇ 10 17 at/cm 3 .
• the fourth layer has a doping level preferably of the order of 5 ⁇ 10 18 at/cm 3 .
• the second layer has an n+ type doping. This ensures good quality electrical conduction with the first electrode.
• the fourth layer forms an ohmic contact with the first layer.
• a first lateral portion grows by epitaxy on the flanks of the second layer.
• a second lateral portion grows by epitaxy on the sides of the second layer and on the first lateral portion.
• the growth and the doping level of the third layer and of the fourth layer are controlled so that the first and second side portions form an electrically insulating barrier.
• This electrically insulating barrier is obtained by depletion, i.e. they no longer contain or only very few free carriers. They then form depleted layers.
• the method comprises at least one step of removing the studs.
• the at least one step of removing the pads is carried out before the production of the first electrode and before the production of the second electrode.
• the at least one step of removing the pads is carried out after the production of the first electrode and before the production of the second electrode.
• the pads are kept after the production of the first electrode and after the production of the second electrode.
• the method comprises, after the production of a thumbnail on each set of studs, the second face being turned with regard to the studs:
• the second electrode preferably being a conductive substrate attached to the second face
• the method comprises, before the fixing of a manipulation substrate, the production of an encapsulation layer encapsulating the vignettes and covering the first face.
• the method comprises, after removal of the pads, the production of an encapsulation layer encapsulating the vignettes and covering the first face, the first electrode being formed through the encapsulation layer.
• making at least part of the first side of the thumbnails accessible includes completely baring the first side of the thumbnails
• the first electrode is formed so as not to cover a central zonel of the first face, for example intended to receive an electrode forming a transistor gate, and to extend over a peripheral zone surrounding the central zonel.
• making at least part of the first face of the thumbnails accessible comprises removing part of the encapsulation layer so as to create in the encapsulation layer an opening making only part of the first face of the thumbnails accessible , the first electrode being formed through said opening.
• the method comprises, after the production of a thumbnail on each set of studs, the second face B being turned with regard to the studs:
• the method comprises, after the production of a thumbnail on each set of studs, the second face B being turned with regard to the studs: - Make at least one hole for each thumbnail, the hole extending from the first face and at least to the first layer,
• the epitaxial growth is carried out at an epitaxial temperature, such that .
• the lll-N material is a nitride of at least one of gallium (Ga), indium (In) and aluminum (Al),
• the III-N material is based on GaN, preferably the III-N material is GaN.
• each of these layers of III-N material has a lower face and an upper face, substantially parallel to an upper face of the substrate.
• Each layer forms a thumbnail. All the lower faces of the layers are substantially included in the same plane. It is the same for the upper faces.
• the creep layer is made of a viscous material. It exhibits a visco-plastic transition.
• this material is taken from:
• the creep layer is preferably made of SiO2,
• BPSG borophosphosilicate glass
• the epitaxial growth being carried out at a temperature Tépjtaxie, such as. Tepjtaxis — k1 X Glass transition, with k1 S 0.8
• the epitaxial growth is carried out at an epitaxial temperature, such as . Tepitaxy — k1 X Glass transition, with k1 S 0.8.
• k1 0.92.
• k1 0.95.
• k2 0.9. This makes it possible to avoid a diffusion of the species of the material whose melting temperature is the lowest.
• T fU sion min is equal to the melting temperature of silicon since the melting temperature of silicon is equal to 1440° and the melting temperature of SiO2 is equal to 1970°C.
• k2 0.8.
• the thumbnails present, in projection in a main extension plane parallel to the main faces of the thumbnails, i.e., parallel to an upper face of the substrate, i.e., parallel to the xy plane of the xyz marker illustrated in FIG. 2A and 3A, maximum dimensions of micrometric dimension.
• these maximum dimensions are less than a few hundred micrometers.
• these maximum dimensions are less than 500 ⁇ m and preferably less than 100 ⁇ m.
• the method can have at least any one of the following characteristics and steps which can be combined or taken separately:
• the distance D (D1 or D2) separating two adjacent pads of the same set, for example the vertices of these two pads, is less than the distance W1 separating two adjacent pads belonging to two different sets.
• k4 1.5
• k4 2.
• W1 can be equal to 1.5 microns.
• W2 being the distance separating two adjacent thumbnails (see W2 in figure 3D), W2 must be non-zero so that the two adjacent thumbnails do not touch each other.
• W2 > 0.
• W1 > k5 x W2, with:
• - W1 is the distance separating two adjacent plots belonging to two distinct sets; - W2 is the distance separating two adjacent thumbnails, W2 being > 0.
• each pad has a section whose maximum dimension dpiot is between 10 and 500 nm ( 10'9 meters), the maximum dimension d piot being measured in a plane parallel to a plane (xy) in which extends mainly an upper surface of the substrate, preferably 20 nm ⁇ dpiot s 200 nm and preferably 50 nm ⁇ dpiot s 100 nm.
• d piot d R or d s .
• each stud has a continuous outline distinct from the outline of the stud which is adjacent to it.
• each stud has a constant section over its entire height H piot .
• the top of the stud has a section that is identical or substantially identical to its base.
• each thumbnail has a section whose maximum dimension of the thumbnail is between 0.5 and 20 ⁇ m ( 10'6 meters), the maximum dimension of the thumbnail being measured in a plane parallel to a plane (xy) in which s' mainly extends an upper face of the substrate, preferably 0.8 ⁇ m ⁇ 3 ⁇ m poop and preferably 1 ⁇ m ⁇ 2 ⁇ m poop.
• the maximum dinette dimension thus corresponds to the maximum dimension of a projection of the thumbnail in a plane parallel to the xy plane in which the upper face of the substrate mainly extends.
• the pads of the same set are distributed on the substrate in a non-periodic manner.
• the vignettes are distributed over the substrate periodically.
• the studs comprise at least one buffer layer surmounting the crystalline section, and made of a material different from that of the nitride thumbnails.
• the nitride decals are made of gallium nitride (GaN) and the buffer layer is aluminum nitride (AIN). This makes it possible to avoid the appearance of the phenomenon of melt back etching (etching by reflow), generated by the very strong reactivity between gallium and silicon.
• the buffer layer is formed by deposition by epitaxy above the crystalline section, before the step of forming the pads by etching.
• the stack comprises, before the step of epitaxial growth of the nitride vignettes, at least said buffer layer.
• the pads comprise, before the step of epitaxial growth of the nitride thumbnails, at least one priming layer, surmounting said buffer layer and made of gallium nitride (GaN).
• the stack comprises, before said step of forming the pads by etching, at least one seed layer, surmounting the crystalline section, the seed layer being made of the same material as that of the nitride vignettes.
• the seed layer is also GaN.
• this priming layer facilitates the resumption of epitaxial growth for the formation of crystallites. This characteristic is all the more advantageous when the top surface of the studs is small.
• each stud has an upper face and the growth by epitaxy of the crystallites takes place at least in part and preferably only from said upper face.
• the buffer layer is placed directly in contact with the upper face of the crystalline section or in contact with the upper face of the section formed by the seed layer.
• the crystallites are grown by epitaxy directly in contact with the crystalline layer. If the top of the pad is formed by the priming layer, then the crystallites are grown by epitaxy directly in contact with the priming layer. If the top of the pad is formed by the buffer layer, then the crystallites are grown by epitaxy directly in contact with the buffer layer. Preferably, the seed layer is placed directly in contact with the upper face of the crystalline section.
• At least one of the buffer layer and the layer seed retains a constant thickness during the epitaxial growth step.
• supplying said stack comprises supplying an elaborate silicon-on-insulator (SOI) type substrate comprising a base substrate surmounted successively by an oxide layer forming said creep layer and a semiconductor layer forming said crystalline layer .
• SOI silicon-on-insulator
• the creep section has a height e 2 2o such that e 2 2o O.lxdpiot, dpiot being the diameter of the stud or more generally the edge-to-edge distance of the stud taken, at the level of the creep section and in a direction parallel to a plane (xy) in which mainly extends an upper face of the substrate, preferably e 220 s 1xdp
• the studs have a height H piot , and in which two adjacent studs are separated by a distance D, such that: H piot / D ⁇ 2 and preferably Hpiot / D ⁇ 1. This distance D can be taken at the tops of the adjacent plots.
• the crystalline section is based on silicon and preferably the crystalline section is made of silicon.
• the crystalline section can also be based on materials other than Si and which allow the epitaxy of nitride materials.
• the crystalline section can be based on SiC or Al 2 0 3 . These materials can also be used in the form of SiCOI (SiC on Insulator, ie SiC on insulator) or SOS (silicon on sapphire).
• the crystalline layer having served to form the crystalline section is a monocrystalline layer.
• the creep layer is in direct contact with the substrate.
• the creep layer is in direct contact with the crystalline section.
• the layer of nitride forming each thumbnail that is produced by coalescence of crystallites is in direct contact with the crystalline section.
• at least one intermediate layer is provided between the crystalline section and the layer of nitride which is produced by coalescence of crystallites and which forms a thumbnail. This intermediate layer typically forms the buffer layer.
• the creep layer and the crystalline layer are different.
• the creep layer has a glass transition temperature. It is therefore made of a glass transition material and exhibits the behavior of glass transition materials.
• the creep layer is not crystalline. It is made of a material viscous or glassy, for example an oxide.
• the creep layer and the crystalline layer are not made of the same material.
• the creep layer has a thickness e 2 20 of less than 500 nm (10' 9 meters). It is preferably between 50 nm and 500 nm and preferably between 100 nm and 150 nm.
• the crystalline layer has a thickness comprised between 2 nm (10' 9 meters) and 10 ⁇ m (10' 6 meters) and preferably between 5 nm and 500 nm and preferably between 10 nm and 50 nm.
• crystals are grown by epitaxy on all the pads.
• the ratio V/III of the fluxes in the epitaxy deposition reactor (the fluxes being for example measured in sccm) of said material comprising nitride (N) and at least one of gallium (Ga) , indium (In) and aluminum (Al) is around 2000.
• the nitride of the vignettes is a gallium nitride (GaN).
• the nitride of the stickers is based on gallium nitride (GaN) and further comprises aluminum (Al) and/or indium (In).
• the material forming the nitride (N) of the labels is any one of: gallium nitride (GaN), indium nitride (InN), aluminum nitride (AIN), aluminum gallium nitride (AIGaN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AIGalnN), aluminum indium nitride (AllnN), aluminum indium gallium nitride (AlInGaN ).
• the step of forming the pads comprises the etching of the crystalline layer and the etching of only a portion of the creep layer so as to retain a portion of the creep layer between the pads.
• k3 3. According to an example 100 > k3 > 3. Preferably, 50 > k3 > 3. Preferably, 5 > k3 > 3.
• This feature allows the creep sections to deform to particularly effectively absorb the mechanical stresses that arise when two adjacent crystallites begin to coalesce.
• this characteristic contributes effectively to reducing the density of defects within the nitride vignettes that are obtained in the end.
• P pio t/d p iot 4 and preferably P pio t/d pio t 5-
• P pio t/d pio t 5.
• the terms “over”, “overcomes”, “covers” or “underlying” or their equivalents do not mean “in contact with”.
• the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with one another, but it does mean that the first layer at least partially covers the second layer. by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element, including air.
• stages of formation of the different layers and regions are understood in the broad sense: they can be carried out in several sub-stages which are not necessarily strictly successive.
• step refers to the performance of part of the process, and may designate a set of sub-steps.
• stage does not necessarily mean that the actions carried out during a stage are simultaneous or immediately successive. Certain actions of a first step can in particular be followed by actions linked to a different step, and other actions of the first step can be repeated later. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.
• insulator or “dielectric” qualify a material whose electrical conductivity is low enough in the given application to serve as an insulator.
• a dielectric material preferably has a dielectric constant of less than 7.
• the spacers are typically formed from a dielectric material.
• a substrate, a layer, a device, "based" on a material M is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example elements alloy, impurities or doping elements.
• a "nitride-based layer” can be a layer made only of this nitride or be made of a nitride added with other species or dopants.
• a nitride layer or structure made at least in part of a nitride (N) obtained from at least one of gallium (Ga), indium (In) and aluminum ( Al), can be a layer or a structure based on GaN, InN, AIN, InGaN, AIGaN, AUnN.
• the thickness of a layer or of the substrate is measured in a direction perpendicular to the surface along which this layer or this substrate has its maximum extension.
• the thickness of the horizontal layers is taken along the vertical, that is to say along the z axis of the reference frame illustrated in FIGS. 2A, 3A and 4 for example.
• dopings are non-limiting examples.
• the invention covers all embodiments in which the dopings are reversed.
• an exemplary embodiment mentions for a first zone a p-type doping and for a second zone an n-type doping the present description then describes, implicitly at least, the opposite example in which the first zone has a doping n-type and the second zone a p-type doping.
• an n+ doping means that it is an n-type doping (doping by negative charges) and whose doping species content is greater than or equal to 1 atom of the doping species for less than 1000 atoms of the semiconductor and preferably for less than 10 to 100 atoms of the material forming the semiconductor layer.
• a doping denoted p+ means that it is a type p doping (doping by positive charges) and whose content of doping species is greater than or equal to 1 atom of the doping species for less than 1000 atoms of the semiconductor and preferably for less than 10 to 100 atoms of the material forming the semiconductor layer.
• n encompasses all doping by carriers of negative charges whatever the content of the doping.
• n doping includes n+ doping contents and n doping contents lower than n+ type doping.
• p encompasses all dopings by carriers of positive charges whatever the content of the doping.
• a p doping includes the p+ doping contents and the p doping contents lower than the p+ type doping.
• An electrode is configured to make ohmic contact with the layer with which it is in contact.
• An electrode can for example be one among a source, a drain, a gate of a transistor.
• the first electrode forms an anode.
• the second electrode forms the cathode.
• FIGS. 2A to 2F An example of a method for forming vignettes in III-N material will now be described with reference to FIGS. 2A to 2F.
• a stack comprising at least one base substrate 100, surmounted successively by a creep layer 200 and a crystalline layer 300.
• creep layer 200 is placed between base substrate 100 and crystalline layer 300.
• the base substrate 100 is silicon-based, amorphous or crystalline. It ensures the mechanical strength of the stack.
• the crystalline layer 300 has a lower face facing the creep layer 200 and an upper face whose function is to serve as a base layer for growing vignettes 550, 550 of nitride.
• the layer that it is desired to obtain in the end is a layer of gallium nitride GaN.
• the crystalline layer 300 is based on monocrystalline silicon.
• the crystalline layer 300 can be based on SiC or Al 2 0 3 .
• creep layer 200 is made of a viscous material.
• the creep layer 200 has a glass transition temperature. It presents the behavior of glass transition materials. Like all materials having a glass transition temperature, the creep layer 200, under the effect of a rise in temperature, deforms without breaking and without returning to its initial position after a drop in temperature. On the contrary, the crystalline layer 300 naturally does not exhibit a glass transition. The crystalline layer deforms, then dislocates and can break. Therefore, the creep layer 200 and the crystalline layer 300 are different. The creep layer 200 is not crystalline.
• the creep layer 200 is made of an amorphous material such as an oxide, preferably a SixOy silicon oxide, such as SiO2. The role of this layer will be explained later in the description.
• this stack comprising the base substrate 100, the flow layer 200 and the crystalline layer 300 constitutes a substrate of the semiconductor on insulator type, preferably of silicon on insulator (SOI).
• the creep layer 200 is formed by the buried oxide layer (BOX) of the SOI substrate.
• a buffer layer 400 is deposited on the upper face of the crystalline layer 300 by epitaxy.
• this buffer layer 400 is typically made of aluminum nitride (AIN).
• AIN aluminum nitride
• the AlN layer thickness is between 10 and 100 nanometers (10.9 meters).
• a seed layer 500 As illustrated in FIG. 2B, it is also possible to deposit by epitaxy, on the upper face of the buffer layer 400, a seed layer 500.
• This seed layer 500 has the function of facilitating the resumption of growth of the crystallites 510 during following steps. In this case, it is from an upper face of the priming layer 500 that at least partly the growth by epitaxy of the crystallites 510A1-510B4 takes place, the crystallites being illustrated in FIG. 2D.
• This priming layer 500 is preferably made of the same material as that of the thumbnails 550, 550 that one wishes to obtain in the end. Typically, when the material of the thumbnails 550, 550 is gallium nitride GaN, the seed layer 500 is also GaN.
• This priming layer 500 typically has a thickness of between 50 and 200 nanometers.
• layers 400 and 500 are only optional. Thus, according to embodiments not illustrated in FIG. 2A-2F, it is possible to provide only the buffer layer 400 or only the priming layer 500, or even none of these two layers 400 and 500.
• pads 1000A1-1000B4 are then formed from the stack. These pads are obtained by etching the stack into the creep layer 200, at least part of the etching extending within the creep layer 200. Thus, and as clearly illustrated 2C for example, the pads are separated from each other. In particular, their vertices are not joined. Their vertices do not touch each other. It is the same for their crystalline sections.
• etching it is possible to use the many etching techniques known to those skilled in the art. It will be possible in particular to use conventional lithography techniques, such as photolithography techniques comprising the formation of a mask, for example in resin, then the transfer of the patterns of the mask into the stack. Electron beam (e-beam) lithography techniques or nanometric printing techniques can also be used.
• photolithography techniques comprising the formation of a mask, for example in resin
• Electron beam (e-beam) lithography techniques or nanometric printing techniques can also be used.
• thumbnail 550 can be formed on a greater number of studs.
• the number of pads as well as their period will be adapted according to the size desired for the microelectronic device, such as a transistor of power, a pin diode or a Schottky diode for example, which you want to make from this thumbnail.
• these studs 1000A1-1000B4 are small in size and can be qualified as nano-studs or nano-pillars.
• the maximum dimension of the section of the pads taken in a plane parallel to the plane xy of the orthogonal reference frame xyz or to the plane of the upper face of the base substrate 100, is between a few tens and a few hundreds of nanometers. This maximum dimension of the section of the studs is referenced d piot in FIG. 2C. If the studs are of circular section, this maximum dimension d stud corresponds to the diameter of the studs. If the studs are of hexagonal section, this maximum dimension d stud corresponds to the diagonal or to the diameter of the circle passing through the angles of the hexagon.
• d piot is between 10 and 1000 nanometers and preferably between 20 and 150 nm and preferably between 50 and 100 nm, for example of the order of 50 nm or 100 nm.
• each stud has a constant section over its entire height H piot .
• the top of the stud has a section that is identical or substantially identical to its base.
• the pads 1000A1-1000B4 are not all distributed evenly on the surface of the base substrate 100.
• the pads 1000A1-1000B4 form sets 1000A, 1000B of pads, each set comprising a plurality of pads.
• the pads 1000A1-1000A4 forming the same set 1000A define a network of pads remote from the network of pads 1000B1-1000B4 forming another set 1000B.
• the adjacent pads 1000A1-1000A4 of the same set 1000A are separated by a distance D.
• the adjacent pads 1000A4-1000B1 belonging to two separate sets 1000A, 1000B are separated by a distance W1.
• the distances D and W1 are taken in planes parallel to the xy plane and are illustrated in FIG. 2C.
• the distances D and W1 are taken for example at the level of the vertices of the adjacent pads.
• the studs 1000A1-1000A4 of the same set 1000A are intended to support a single thumbnail 550 which will be distant from another thumbnail 550B supported by another set 1000B of studs 1000B1-1000B4.
• the distance D may vary.
• the pads 1000A1-1000A4 of a same thumbnail 550 can be distributed in a non-periodic manner. Their distribution can thus be adapted to promote the growth of the sticker or to promote the controlled detachment of part of the sticker relative to the base substrate 100.
• the arrangement of the studs 1000A1- 1000A4 of a sticker 550 is not periodic, one can have a D which varies for these pads 1000A1-1000A4 by plus or minus 20% or by plus or minus 10%, for example plus or minus 10 nm around an average value.
• D can take the following values for the same thumbnail: 100 nm, 90 nm, 85 nm, 107 nm.
• the vignettes 550, 550 formed on sets of pads 1000A, 1000B distributed in a non-periodic manner can for their part be arranged periodically on the base substrate 100.
• the sections of the studs 1000A1-1000B4, formed in the creep layer 200 have a height e 2 2o and, within the same assembly, two adjacent studs 1000A1, 1000A2 are separated by a distance D, such as:
• the studs have a height H piot and two adjacent studs are separated by a distance D, such that:
• H piot / D ⁇ 2 preferably H piot / D ⁇ 1.5.
• Hpiot and e220 are measured along the z direction.
• D is measured parallel to the xy plane.
• H piot , e 22 o and D are shown in Figure 2C.
• the pads are etched through the entire seed layer 500, the entire buffer layer 400 (when the latter are present), the entire crystalline layer 300.
• This embodiment has the advantage of preventing the nitride of the vignettes 550, 550 from developing on the creep sections 220 during epitaxy. This epitaxy selectivity is encountered in particular when the nitride vignettes 550, 550 that grown by epitaxy are in GaN and that the creep sections are in SiO 2 .
• the creep layer 200 is etched over its entire thickness, then, during epitaxy, the nitride of the vignettes 550, 550 develops from the upper face of the base substrate 100 , usually made of silicon. This situation is obviously not desirable.
• the fact of keeping a non-etched portion 210 of the creep layer 200 makes it possible to facilitate the creep of the section 220, in particular when the crystallites are disoriented in a twist, that is to say in main extension plans of the thumbnails 550, 550 that one wishes to obtain.
• These main thumbnail extension planes 550, 550 are parallel to the xy plane of the xyz reference.
• the thickness e220 etched, and therefore forming the height of the creep section 220 is equal to at least half the thickness of the creep layer 200. This makes it possible to have a very good reorientation of the crystallites during the formation of grain boundaries.
• Figure 2D illustrates the formation of crystallites 510A1-510B4 by epitaxial growth from seed layer 500 (or from the top side of crystal layer 300 when layers 400 and 500 are absent).
• the studs 1000A1-1000B4 each support a crystallite 510A1-510B4 carried by a stack of sections 400A1-400B4, 300A1-300B4, 220A1-220B4.
• the sections extend along the main extension direction of the block, that is to say vertically (z) in Figures 2A to 2F.
• the growth by epitaxy of the crystallites 510A1-510B4 is carried out in part at least or only from the upper face of the stud 1000A1-1000B4, also designated top 1010 of the stud.
• this upper face is formed either by the crystalline section 300A1-300B4, or by the section formed by the priming layer 400A1-400B4, or by the section formed by the buffer layer. In particular, this makes it possible to quickly obtain 510A1-510B4 crystallites of significant thickness.
• the upper faces of the buffer layer 400 and of the priming layer 500 that is to say the faces facing the layer of thumbnails 550, 550 that one wishes to grow, have Gallium (Ga) type polarities, and not nitrogen (N), which considerably facilitates obtaining 550, 550 vignettes of high quality epitaxial nitride.
• Ga Gallium
• N nitrogen
• crystallites 510A1-510B4 continue and extends laterally, in particular along planes parallel to the xy plane.
• the crystallites 510A1-510B4 of the same set 1000A of pads 1000A1-1000A4 develop until they coalesce and form a block or vignettes 550, 550 as illustrated in FIG. 2E.
• each thumbnail 550, 550 extends between several pads 1000A1-1000A4.
• Each vignette 550, 550 forms a continuous layer of III-N material.
• This growth of crystallites 510A1-510B4 does not extend downward. Moreover, this growth is selective in that it does not take place on the creep layer 200 typically made of an oxide. In this sense, the growth of crystallites 510A1-510B4 takes place according to the principle of pendeo-epitaxy. It will be noted that it is particularly advantageous to etch the pads 1000A1-1000B4 after formation by epitaxy of the buffer layer 400 and of the priming layer 500 (when these layers are present). Indeed, if one of these layers 400, 500 were deposited after etching, it would form at least in part between the pads 1000A1-1000B4 on the upper face of the creep layer 200.
• the epitaxial nitride is GaN, that the creep layer 200 is SiO 2 , then, at the temperature of the deposition by epitaxy, the epitaxial growth of the vignettes 550, 550 of nitride would not take place selectively but would on the contrary also take place between the 1000A1-1000B4 pads, which of course is not desirable.
• the temperature T éP itaxie at which the epitaxy is carried out is greater than or of the order of the glass transition temperature Tt glass transition of the creep layer 200.
• the creep sections 220A1-220A4 are brought to a temperature which allows them to deform.
• the studs 1000A1-1000A2 are not joined, in particular they are not joined at their vertices, which allows them to deform independently of each other, so that the crystallites 510A1-510A2 can be oriented to minimize the energy of the system.
• a plurality of thumbnails 550, 550 are obtained, each thumbnail 550 being supported by the studs 1000A1-1000A4 of a same set 1000A of studs.
• Two adjacent vignettes 550, 550 are separated by a distance W2, W2 being the smallest distance taken between these two vignettes. W2 is measured in the xy plane.
• W2 depends on W1, the duration and the speed of epitaxial growth. W2 is nonzero. W2 ⁇ W1.
• poop the maximum dimension of a thumbnail measured parallel to the xy plane.
• poop corresponds to the maximum dimension of a projection of the thumbnail in a plane parallel to the xy plane.
• poop depends on the speed and the duration of the epitaxial growth as well as on the number, the dimension and the pitch p piot of the pads of the same set.
• the poop will for example be of the order of a few tens of ⁇ m.
• FIG. 2E illustrates a non-limiting embodiment in which layers having different types of doping are produced within the layer of III-N material of each thumbnail 550, 550.
• layers having different types of doping are produced within the layer of III-N material of each thumbnail 550, 550.
• those skilled in the art can implement the known solutions of the state of the art.
• the doping of each of these layers can be carried out during the growth by epitaxy of the crystallites.
• the sticker 550 has, from its rear face 550B facing the base substrate 100 and up to its front face 550A, the following layers:
• III-N material having for example an n+ type doping
• III-N material in III-N material, having for example an n- type doping
• III-N material having for example a P-type doping
• III-N material having for example an n+ type doping.
• doping is not limiting.
• the characteristics, steps and technical effects described above are perfectly applicable to layers of III-N material having only some of these layers 551-554, or having another combination of layers, or even having additional layers.
• the layer 551 is the layer formed by coalescence of the crystallites which grow by epitaxy on the pads 1000.
• the layer formed by coalescence of the crystallites which grow by epitaxy on the pads 1000 is an initial layer, referenced 550i in FIG. 4, different from layer 551.
• This last embodiment has the advantage of more precisely controlling the dopings of layer 551. All the embodiments described above and below below are perfectly replaceable by embodiments with or without an initial layer 550i between the pads and the first layer 551. Examples of features to reduce dislocations at coalescence joints
• T éP itaxie makes it possible for the creep section 220 to creep.
• epitaxy — k2x Tf U sion min, Tf U sion min being the lowest melting temperature among the melting temperatures of the sections forming the pad. These are mainly the crystalline section and the creep section. According to an exemplary embodiment, k2 0.9. This makes it possible to avoid a diffusion of the species of the material whose melting temperature is the lowest.
• T fU sion min is equal to the melting temperature of silicon since the melting temperature of silicon is equal to 1440°C and the melting temperature of SiO 2 is equal to 1970°C.
• the step of forming the studs 1000A1-1000A4 is carried out so that dcnstaiüte / d piot s k3, d piot being the maximum dimension of the section of the stud 1000A1-1000A4 taken in a direction parallel to the plane in which extends the upper surface base substrate 100.
• d piot corresponds to the maximum dimension of a projection of the stud in the xy plane.
• dcristaiite corresponds to the size of the crystallite measured along the same direction as d piot at the time of the coalescence of crystallites 510A1-510B4.
• k3 > 3 preferably 100 > k3 > 3.
• This characteristic allows the creep sections to deform in order to absorb in a particularly effective manner the mechanical stresses which arise when two adjacent crystallites begin to coalesce.
• this characteristic contributes effectively to reducing the density of defects within the 550, 550 nitride thumbnails that are obtained in the end.
• FIGS. 3A to 3J A first embodiment of a vertical component from epitaxial thumbnails will now be described in detail with reference to FIGS. 3A to 3J.
• a first step consists in providing a stack comprising the base substrate 100 supporting several thumbnails 550.
• Each of these thumbnails 550 comprises a layer of III-N material formed of several sub-layers, each sub-layer having dopings of different types.
• the method according to the invention is not limited to a certain number of doped layers, to certain types of doping or even to a certain combination of dopings.
• an encapsulation layer 600 is produced which covers the thumbnails 550.
• This encapsulation layer 600 covers both the rear face 550B and the front face 550A of the thumbnails 550.
• This encapsulation layer 600 has for the function of stabilizing the 550 thumbnails before the next technological steps. In addition, it protects the 550A front panel.
• This encapsulation layer 600 is for example a dielectric layer, deposited by centrifugation. Typically, it is a layer of SOG (acronym for the English word Spin On Glass, meaning centrifuged glass), essentially comprising SiO 2 and possibly other species.
• SOG synonym for the English word Spin On Glass, meaning centrifuged glass
• a sacrificial substrate 700 is then attached to the encapsulation layer 600.
• This encapsulation layer 600 thus also has the function of forming a surface facilitating attachment, for example by bonding, with the sacrificial substrate 700 .
• the assembly comprising the two substrates 100, 700 as well as the thumbnails 550 held in the encapsulation layer 600.
• the following steps aim to make the thumbnail 550 made of III-N material accessible, as illustrated in FIG. 3E. More precisely, it is sought to make accessible the layer 551 which defines the rear face 550B of the thumbnail 550 of the vertical component.
• this first layer 551 is n+ doped. This ensures a good electrical connection with the electrode that will be in contact with it.
• the base substrate 100 is removed, as illustrated in FIG. 3D1. Then, all of the layers surmounting the rear face 550B of the thumbnail 550 can be removed. mechanical-chemical (CMP), an etching step.
• CMP mechanical-chemical
• mechanical delamination can be carried out at the level of the studs 1000.
• the application of a mechanical stress makes it possible in particular to break the studs 1000 at the level of the creep sections 220. then proceeds to remove the various layers which surmount the rear face 550B of the sticker 550.
• one or more of the steps mentioned above of grinding, CMP or etching can be used.
• the thumbnail 550 is thus made accessible. Provision can be made to remove a portion of the thickness of this sticker or, on the contrary, to stop on the initial lower face 550B.
• the thumbnail 550 has an initial layer 550i which results from the coalescence of the crystallites 510 on the pads 1000, and which is not the doped layer 551, then this initial layer 550i is also removed.
• each thumbnail 550 has the following layers from the rear face 550B: an n ⁇ doped layer 551, a p doped layer 552, an n+ doped layer 553.
• an electrode 20 is made to form an ohmic contact with the layer 550 of III-N material. This step is illustrated in Figure 3F.
• an electrically conductive base can be attached to the accessible face of the thumbnails 550.
• This is typically an electrically conductive plate or substrate. It can also be a conductive layer, a conductive coating on a base or a support of any kind.
• the sacrificial substrate 700 is then removed.
• a mask 900 is then produced covering partially thumbnails 550 leaving accessible a first zone 550A1 of the front face 550A of the thumbnails and by masking a second zone 550A2 of the front face 550A of the thumbnails.
• the mask 900 has one or more portions 920 which cover the second zone 550A2 and one or more openings 930 which leave the thumbnail 550 accessible.
• the first area 550A1 extends from the center of the front face 550A of the thumbnails 550 and the second area 550A2 surrounds the first area 550A1.
• the mask 900 extends to the periphery of the front face 550A and also covers the sides 550C of the thumbnails 550.
• the mask 900 also has portions 910 which extend between two adjacent thumbnails 550.
• Mask 900 is preferably made of a dielectric material. It may be SiO 2 .
• This mask 900 can be formed by partial etching of the encapsulation layer 600.
• this mask 900 can be formed by deposition then lithography, these two steps being carried out after removal of the encapsulation layer 600.
• an electrically conductive material is deposited in the openings 930 of the mask 900. This conductive material forms an electrode 10 for the vertical component.
• the vertical component then has a first electrode 10 and a second electrode 20. A current flowing from one of these electrodes to the other thus crosses the thickness of the layer of III-N material of the thumbnail 550.
• the vertical component is a transistor.
• Electrode 10 acts as a source
• electrode 20 acts as a drain.
• An additional and optional step is also carried out to form an additional electrode 30 acting as a gate.
• an electrically conductive layer is deposited, typically forming the gate metal.
• This electrode 30 is deposited between the vignettes 550 and covers part of the portions 920 of the mask 900.
• the electrode 30 comprises:
• the grid is deposited on the vertical components, without being etched.
• the proposed method makes it possible to preserve the characteristics of the grid because it is not engraved. This significantly improves the performance of power components.
• this makes it possible to improve the threshold voltage, the mobility in the channel and to reduce trapping in the oxide, which has an impact on the threshold voltage and its reliability.
• the grid may have a small thickness.
• each stud 1000 has a hexagonal shape.
• the proposed method makes it possible to overcome the drawbacks associated with the delimitation etching of the various vertical components.
• the thumbnails made of III-N material each correspond in their shape and their dimension to one of the electrodes of the vertical component, for example to the source of a vertical transistor.
• the material of the vignettes is completely relaxed and contains very few dislocations.
• the dislocation rate is typically less than 1 E 8/cm 2 .
• it is less than 1 E 7/cm 2 , preferably it is of the order of 1 E 6/cm 2 .
• the proposed method thus makes it possible to obtain a vertical component, here a transistor, based on an III-N material having a large thickness, a high purity and a low density of dislocations.
• a considerable advantage of the proposed process is the reduction in cost price and the increase in diameter of the plates compared to solutions based on freestanding or bulk GaN plates (self-supporting or massive), which only exist in diameter less than or equal to 100mm.
• the best-known solution for manufacturing freestanding GaN plates is layer epitaxy by HVPE (Hybrid Vapor Phase Epitaxy) on a substrate such as sapphire. The growth is done in order to reduce the density of surface dislocations, and to have a final layer which is a few hundred pm thick. With these known solutions, the sapphire substrate can therefore be removed, leaving a layer of GaN which could be used as a plate. This solution is long and expensive. In addition, it is difficult to implement on large diameter plates.
• Figures 5A to 5D illustrate other component structures that can be obtained by implementing the method according to the invention.
• the vignette 550 of FIG. 4 can be obtained by implementing the method described above with reference to FIGS. 2A to 2F.
• This thumbnail 550 comprises the layers 550i, 551, 552, 553, 554 described above. As mentioned above, it is possible to get a thumbnail without the initial 550i layer.
• FIG 5A illustrates a vertical transistor similar to that shown in Figure 3J. Indeed, this vertical transistor includes:
• a source 10 and a drain 20 arranged respectively on the faces 550A and 550B of the layer of III-N material, the face 550A being formed by the fourth layer 554 and the face 550B being formed by the first layer 551,
• a grid 30 arranged on the sides 550C of the vignette and thus surrounding the layer of III-N material over at least part of its height.
• gate 30 is directly in contact with layers 553 and 554. It is not in contact with layer 552.
• FIG. 5B illustrates another example of a vertical transistor in which the gate 30 is etched through at least some of the doped layers of the III-N material.
• gate 30 crosses layers 554 and 553.
• Source 10 extends over front face 550A and surrounds gate 30. Naturally, source 10 is placed at a distance from gate 30 to avoid any short circuit.
• FIGS. 5C and 5D illustrate vertical components close to those illustrated in FIGS. 5A and 5B respectively, except that lateral portions of layers 553 and 554 cover part of the sides 552F of layer 552. Layer portions 553 and 554 that cover the 552F sidewalls are referenced 553A and 554A.
• the e553A and e554A thicknesses of the III-N material are well targeted, with the right doping, it can be ensured that the junction is completely depleted.
• the layers 553A, 554A which grow on the sides 552F then have no free carriers, and will present a high resistivity. They will then form a barrier preventing electrons from reaching the surface of the sides of the sticker 550.
• This deserted p-n junction then acts as passivation layers for the sides of the sticker 550. This avoids having to add specific layers of passivation.
• the process for producing the component is then simplified and its cost price reduced.
• the growth of the layers 553, 554 is carried out so that the side portions 553A and 554A cover the entire height of the flanks 552F of the second layer 552.
• the flanks 552F of the second layer 552 are entirely protected and are no longer accessible.
• a single component and a single cell are produced per thumbnail.
• several components or several cells can be produced on the same thumbnail.
• the same thumbnail is in contact with several grids.
• Several components are then produced by vignettes. Indeed, in particular for MOS technologies, there is an interest in making several cells or components on the same thumbnail.
• a component can also be composed of several cells, each with a grid. This embodiment is particularly interesting if the edges of vignettes or mesas have too many impurities to have a very low doping. In this case, it will then be interesting to make large thumbnails with several cells for each thumbnail.
• the III-N material is based on GaN.
• the III-N material is GaN.
• the first layer 551 can have a thickness e551 of between 1 and 5 ⁇ m (10-6 meters), preferably between 1 and 3 ⁇ m, preferably of the order of 2 ⁇ m.
• This first layer 551 has an n+ type doping. This makes it possible to ensure good quality electrical conduction with the second electrode 20.
• this first layer 551 has a doping level greater than or equal to 5.1017 atoms per cubic centimeter (at/cm3) and preferably of the order of 5.1018 at/cm3.
• the first layer has a doping level preferably of the order of 5.1018 at/cm3.
• the first layer 551 extends from one side 550C to the other of the sticker 550. It extends over the entire surface of the sticker 550. The surface of the sticker is taken into projection on a parallel plane (xy plane) in which the upper face of the substrate 100 mainly extends.
• the second layer 552 can have a thickness e552 of at least 8 ⁇ m (10-6 meters) and preferably of at least 10 ⁇ m. Thus, this relatively thick layer 552 is perfectly suitable for power components.
• the second layer 552 has a doping level greater than or equal to 1.1015 at/cm3 and preferably of the order of 1.1016 at/cm3.
• the second layer 552 has an n- type doping. As illustrated in FIG. 3E to 13D, the second layer 552 extends from one flank 550C to the other of the thumbnail 550, except in the embodiments where it is covered, at the flanks, by a third 553 or a fourth layer 554. The second layer 552 extends over the entire surface of the sticker 550.
• the third layer 553 can have a thickness e553 of at least 100 nm (10-9 meters) and preferably of less than 1 ⁇ m. Preferably, the thickness e553 is between 300 and 700 nm. According to one example, the thickness e553 is equal to 500 nm.
• the third layer has a doping level greater than or equal to 5.1017 at/cm3 and preferably of the order of 1.1018 at/cm3. It exhibits p-type doping. As illustrated in FIG. 3E to 9, the third layer 553 extends from a flank 550C to the other of the sticker 550 except in the embodiments where it is covered, at the level of the sides, by a fourth layer 554. The third layer 553 extends over the entire surface of the sticker 550.
• the fourth layer 554 can have a thickness e554 of at least 50 nm (10-9 meters). Preferably, the thickness e554 is between 50 and 300 nm. Preferably, the thickness e554 is of the order of 100 nm.
• the fourth layer 554 has a doping level greater than or equal to 5.1017 at/cm3 and preferably of the order of 1.1018 at/cm3. It exhibits an n+ type doping. This makes it possible to ensure good quality electrical conduction with the first electrode 10. As illustrated in FIGS. 3E to 5D, the fourth layer 553 extends from one side 550C to the other of the label 550. It extends over the entire surface of the sticker 550.
• Figure 7 illustrates another structure of components that can be obtained by implementing the method according to the invention. This structure is preferably made from a thumbnail 550 like the one illustrated in Figure 6.
• the thumbnail 550 of FIG. 6 can be obtained by implementing the method described above with reference to FIGS. 2A to 2F.
• This thumbnail 550 comprises the layers 550i, 551, 552 described above. As mentioned above, it is possible to get a thumbnail without the initial 550i layer.
• FIG. 7 illustrates a diode, for example of the Schottky type. This vertical component includes:
• an electrode for example an anode, acting for example as a source 10 arranged on the face 550A of the layer of III-N material formed by the second layer 552,
• An electrode for example a cathode, acting for example as a drain 20 arranged on the face 550B defined by the first layer 551 of III-N material.
• the layers 551, 552 have the characteristics, in terms of thickness and/or level of doping, mentioned above with regard to the embodiment illustrated in FIGS. 5A to 5D.
• Figure 9 illustrates another component structure that can be obtained by implementing the method according to the invention. This structure is preferably made from a thumbnail 550 like the one illustrated in Figure 8.
• the thumbnail 550 of FIG. 8 can be obtained by implementing the method described above with reference to FIGS. 2A to 2F.
• This thumbnail 550 comprises the layers 550i, 551, 552, 553 described above. As mentioned above, it is possible to obtain a thumbnail devoid of the initial layer 550i.
• FIG. 9 illustrates a diode, for example of the p-i-n type.
• This vertical component includes:
• an anode for example a source 10, arranged on the face 550A of the layer of III-N material formed by the third layer 553,
• a cathode for example a drain 20, arranged on the face 550B defined by the first layer 551 of III-N material.
• the layers 551, 552, 553 have the characteristics, in terms of thickness and/or level of doping, mentioned with regard to the embodiment illustrated in FIGS. 5A to 5D.
• FIGS. 10A to 10G another embodiment of a vertical component will be described in detail.
• a first step consists in providing a stack comprising thumbnails 550 each supported by a set of studs integral with the base substrate 100.
• each thumbnail corresponds to thumbnail 550 illustrated in figure 6.
• the following example is perfectly suitable for the use of different thumbnails, in particular those illustrated in figure 4, 5C or 8.
• First steps include the encapsulation of the vignettes in an encapsulation layer 600 and the fixing of a sacrificial substrate 700. These steps, the result of which is illustrated in FIG. 10B, correspond to those described above with reference to FIGS. 3A and 3B.
• the studs are then removed and the rear face 550B of the III-N material layer is exposed, as illustrated in FIG. 10D.
• the steps described above with reference to FIGS. 3D1 to 3E can be carried out.
• the second electrode 20 is then formed. For this, it is for example possible to attach a conductive base 20 to the rear face 550B. This step corresponds to that described above with reference to FIG. 3F.
• the first electrode 10 is then formed. For this, it is possible for example to open the encapsulation layer 600 to make the front face 550A of the layer of III-N material accessible. This step corresponds to that described above with reference to FIG. 3G. It will be noted that it is possible to make the first electrode 10 before the second electrode 20. Example of embodiment illustrated in FIGS. 11A to 11D
• FIGS. 11 A to 11 D another embodiment of a vertical component will be described in detail.
• a first step consists in providing a stack comprising thumbnails 550 each supported by a set of studs integral with the base substrate 100.
• each thumbnail presents the layers 551 and 552.
• the initial layer 550i produced by coalescence of the crystallites at the top of the pads is directly the first functional layer 551.
• the following example is perfectly suitable to the use of different thumbnails, in particular any of the thumbnails illustrated in figure 4, 5C, 6 or 8.
• a first step includes the encapsulation of thumbnails 550 in an encapsulation layer 600.
• the first electrode 10 is then formed. For this, it is possible for example to open the encapsulation layer 600 to make the front face 550A of the layer of III-N material accessible. The result of this step is illustrated in FIG. 11B.
• an opening 110 is made through the base substrate 100 and so as to make the first layer 551 of each sticker 550 accessible.
• This opening 110 can be made by etching through a mask. During this etching, provision can be made to remove the studs which are located to the right of the opening 110. This step is illustrated in FIG. 11C.
• the opening 110 is filled with an electrically conductive material, thus defining the second electrode 20.
• this electrode 20 can be qualified as TSV (through silicon via - via traversing silicon).
• opening 110 is completely filled.
• the deposit of electrically conductive material preferably forms a layer having a continuous lower face serving as a base for the stack.
• the opening 110 as well as the second electrode 20 can be made before the formation of the first electrode 10.
• the encapsulation layer 600 is only optional. This embodiment can be implemented with a via leading to the first layer 551 without necessarily providing an encapsulation layer 600.
• This embodiment has the advantage of considerably reducing the number of steps. In particular, it is not necessary to carry out steps intended to remove the studs. This embodiment is also advantageous for ensuring thermal conductivity between the vignette and the substrate.
• one of the first 10 and the second 20 electrodes is located on the first face 550A of the vignette 550 and the other of the first 10 and the second 20 electrodes is located on the second face 550B of the vignette 550. This allows the current passing from one electrode to the other to pass through the entire thickness of the first and second layers, which considerably improves the performance of the device.
• FIGS. 12A to 12E another embodiment of a vertical component will be described in detail.
• a first step consists in providing a stack comprising thumbnails 550 each supported by a set of studs integral with the base substrate 100.
• each thumbnail has layers 550i, 551, and 552.
• the following example is ideal for using different thumbnails, including any of the thumbnails shown in Figure 4, 5C, 6, or 8 or 11A.
• a first step includes the encapsulation of the thumbnails 550 in an encapsulation layer 600. This step is illustrated in FIG. 12B.
• the first electrode 10 is then formed. For this, it is possible for example to open the encapsulation layer 600 to make the front face 550A of the layer of III-N material accessible.
• the first electrode 10 Before or after, or preferably simultaneously with the formation of the first electrode 10, it is possible to produce an electrode serving as gate 30 if the vertical component is a transistor. As illustrated in the figures, it is preferably provided that the first electrode 10 surrounds the grid 30. Thus, the first electrode can for example form on the front face 550A, a ring surrounding the grid 30. For the production of at least one gate 30, it is possible to provide a prior etching within the second layer 552 so that the gate 30 penetrates at least partly into this second layer 552. The result of this step is illustrated in FIG. 12C.
• the second electrode 20 is produced.
• a first step consists in making a hole also designated via 111, from the front face 550A of the thumbnail 550.
• This via 111 extends into the layer in lll-N material to a depth p111.
• p111 is configured so as to make the first layer 551 accessible.
• p111 is greater than the distance separating the front face 550A from the first layer 551. In this example, this distance corresponds to the thickness e 552 of the second layer 552
• This step is illustrated in Figure 12D.
• An electrically conductive material is then deposited inside the via 111 to make the second electrode 20 forming an electrical contact with the first layer 551.
• the walls of the via 111 will have been electrically insulated beforehand to avoid any electrical conduction between the second electrode 20 and the layers of III-N materials surmounting the first layer 551.
• only the second layer 552 surmounts the first layer 551.
• the electrical insulation layer(s) of the via 111 are referenced 25 in FIG. 12E.
• the vertical component is a transistor, the first electrode 10 and the second electrode 20 then effectively forming the drain and the source.
• This vertical component structure, with a through electrode, as well as the production method, are perfectly applicable to vertical components other than transistors.
• the same steps can be carried out, the steps for producing the gate then being naturally eliminated.
• This embodiment has the advantage of considerably reducing the number of steps. In particular, it is not necessary to carry out steps intended to remove the studs. Furthermore, it allows contact with the first 10 and second 20 electrodes from the same face of the component.
• FIGS. 13A to 13G another embodiment of a vertical component will be described in detail.
• the step illustrated in FIG. 13A corresponds to that described above with reference to FIG. 10A.
• a sacrificial substrate 700 is then attached to the front face 550A of the sticker 550.
• This step, illustrated in FIG. 13B, is therefore close to that illustrated in FIG. 10B, with the difference that this sacrificial substrate 700 is attached directly to the stickers. 550 and there is no encapsulation layer 600.
• Base substrate 100 is removed. This removal can be done mechanically. During this removal, most of the studs are broken, in particular at their creep portion 220. This step is illustrated in FIG. 13C.
• the first layer 551 of III-N material is made accessible. For this, the remaining portions of the studs are removed. The possible initial 550i layer is also removed.
• the electrode 20 is then placed in contact with the first layer 551.
• the vignettes 550 are preferably fixed to an electrically conductive substrate, as illustrated in FIG. 13F.
• Figures 13G illustrate the result of the following steps. These steps include forming the first electrode 10 on the front face 550A of the decals 550 and forming a passivation layer 610 to electrically insulate the decal 550.
• this embodiment has the advantage of reducing the number of steps by avoiding the formation of the encapsulation layer 600.
• the present invention proposes a particularly effective solution for obtaining vertical microelectronic components based on an III-N material exhibiting high purity, low dislocation density and high thickness, typically a thickness greater than 8 ⁇ m.
• the invention is particularly advantageous for the production of diode and transistor power components in GaN, for the discrete component market on ranges from a few 100V to a few kV in a range of intensity typically comprised in the range of 1 Ampere (A) a few hundred Amps. Other applications are of course possible.
• the examples above describe certain examples of layers of III-N material formed of several sub-layers having different dopings.
• the method according to the invention is not limited to a certain number of doped layers, to certain types of doping or even to certain combinations of doped layers.
• the first electrode 10 can be made before or after the second electrode 20.

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• 2020
  • 2020-12-22 FR FR2013964A patent/FR3118281B1/fr active Active
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