Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/00006—Changing the frequency
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/033—Monostable circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/01—Shaping pulses
  • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
  • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/01—Shaping pulses
  • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
  • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
  • H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
  • H04L9/0852—Quantum cryptography

Definitions

• the invention relates to generating pulses for controlling optical modulators, and, in particular, though not exclusively, to a pulse generator for high-frequency generation of pulses having a narrow pulse width, an optical quantum apparatus, such as photonic qubit generator or a quantum key distribution system, using such pulse generator and a computer program product for executing such methods.
• Quantum information system are data processing systems that use a quantum system, e.g. a qubit, as an information carrier rather than classical bits ‘0’ and T as used by conventional data processing system.
• Qubits can be represented as superposition of two orthogonal quantum states
• ip) a
• An example of a quantum information system is a so-called quantum key distribution (QKD) system which allows two or more users at different locations to securely generate cryptographic keys based on the laws of quantum mechanics.
• QKD quantum key distribution
• MDI-QKD point-to-point MDI-QKD is ideally suited for extension into startype networks.
• MDI-QKD can be seamlessly upgraded - not disruptively replaced - into quantum repeater-based long-distance quantum communication as more mature hardware becomes available.
• An example of an MDI-QKD system is described in the article by R.
• Valivarthi et al A cost-effective measurement-device-independent quantum key distribution system for quantum networks, Quantum Science and Technology, 2 (2017), which proposes a MDI-QKD system based on distributed feedback lasers and field- programmable gate array for time-bin qubit preparation and time-tagging.
• Time-bin qubits may be formed by a coherent superposition of two independent temporal modes of a single-photon excitation.
• Time-bin encoding is especially suitable for single-mode optical fibre propagation and compatible with already existing fibre networks.
• the formation of time bin qubits in QKD systems is an essential element in the development of practical QDK implementations.
• QKD protocols such as the abovereferred MDI-QKD protocol, the coherent one-way (COW) QKD protocol and other QKD protocols such as described in the article by Vagniluca et al, Efficient time-bin encoding for practical high-dimensional quantum key distribution, physical review applied 14, 014051 (2020), use a train of phase coherent temporal modes by intensity modulation of the output of a continuous-wave (CW) laser and subsequent attenuation. Measures should be taken to ensure independence between the two temporal modes.
• CW continuous-wave
• QKD systems and protocols including QKD systems and protocols that are based time-bin qubits, are subject to standardisation efforts to define requirements to improve the inter-operability of the different components and interfaces in such system without compromising security.
• pulses forming a time-bin encoded qubit should be indistinguishable. That is a light modulator should be controlled such that only the intensity of the laser light is modulated without modifying other degrees of freedom of the light (polarization, relative phase or carrier frequency) as correlations between the different degrees of freedom could be exploited. The same holds for deviations between targeted values and actual values of the controlled intensity.
• time-bin light pulses should be undisguisable has consequences for the electronics that controls the modulator in the sense that it should be able to produce high frequency pulses for controlling an intensity modulator that are undisguisable.
• State-of-the art FPGA-based pulse generators that are typically used for controlling optical modulators cannot guarantee such high pulse fidelity.
• aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit,” “module” or “system.” Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.
• the methods, systems, modules, functions and/or algorithms described with reference to the embodiments in this application may be realized in hardware, software, or a combination of hardware and software.
• the methods, systems, modules, functions and/or algorithms may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the embodiments (or parts thereof) described in this application is suited.
• a typical implementation may comprise one or more digital circuits such as application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), and/or one or more processors (e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture) and associated supporting circuitry (e.g., storage, DRAM, FLASH, bus interface circuits, etc.).
• ASICs application specific integrated circuits
• FPGAs field programmable gate arrays
• processors e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture
• associated supporting circuitry e.g., storage, DRAM, FLASH, bus interface circuits, etc.
• Each discrete ASIC, FPGA, processor, or other circuit may be referred to as “chip,” and multiple such circuits may be referred to as a “chipset.”
• the programmable logic devices may be provided with fast RAM, in particular block RAM (BRAM).
• BRAM block RAM
• Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to perform processes as described in this disclosure.
• a non-transitory machine-readable (e.g., computer readable) medium e.g., FLASH drive, optical disk, magnetic storage disk, or the like
• each block in a flowchart or a block diagrams may represent a module, segment, or portion of code, which be implemented as software, hardware or a combination of software and hardware.
• the main insight of the embodiments in this disclosure revolves around the generation of one or more high-quality pulses for driving an electro-optic modulator or the like.
• the one or more pulses may be generated based on a high frequency clock signal.
• the electronics is designed to produce pulses that have a high pulse fidelity.
• the methods, systems and devices for producing such high-quality pulses may be used to drive optical components devices, including but not limiting to switches, phase and intensity modulators, intensifiers, as well as resistive loads.
• the pulses may be used as a modulation signal for signal generation in optical communication, quantum signal processing and as a stimulus and clock signal to analyze and test electrical devices.
• the invention relates to a method of generating pulses for controlling an optical device.
• the method may comprise one or more of the following steps: receiving a clock signal and one or more digital pulse selection signals, wherein the timing quality of the clock signal is higher than the timing quality of the digital pulse selection signals; generating one or more control pulses based on the one or more digital pulse selection signals and the clock signal, the generating including: constructing, depending on the logical value of a first digital pulse selection signal, a first base pulse, the first base pulse including a rising edge that has the timing quality of the clock signal; constructing a second base pulse based on the first base pulse, the second base pulse having a falling edge that has the timing quality of the clock signal; and, constructing a first analog control pulse based on the first base pulse and the second base pulse, wherein the timing quality of the rising edge and the falling edge of the first analog control pulse have the timing quality of the clock signal.
• the invention may also relate to a method of generating pulses for controlling an optical device comprising: receiving a clock signal and one or more digital pulse selection signals generated based on the clock signal; and, generating one or more control pulses, preferably one or more analog control pulses, based on the one or more digital pulse selection signals and the clock signal, the generating of the one or more control pulses including: constructing a first base pulse, the constructing of the first based pulse including providing a first digital pulse selection signal and the clock signal to the input of a transparent latch, wherein the output of the latch is connected via a delay circuit to a reset port R of the transparent latch; constructing a second base pulse based on the first base pulse, the constructing of the second base pulse including inverting the first base pulse and applying a delay to the first base pulse and/or second base pulse so that the rising edge of the first base pulse is positioned before the falling edge of second base pulse; and, constructing a first control pulse based on the first base pulse and the second base pulse.
• the generating of the one or more control pulses may further include: constructing a third base pulse, the constructing of the third based pulse including providing a second digital pulse selection signal and the clock signal to the input of a second transparent latch, wherein the output of second transparent latch is connected via a delay circuit to a reset port R of the second transparent latch; constructing a fourth base pulse based on the third base pulse, the constructing including inverting the third base pulse and applying a delay to the third base pulse and/or fourth base pulse so that the rising edge of the third base pulse is positioned before the falling edge of fourth base pulse; and, constructing a second control pulse based on the third base pulse and the fourth base pulse.
• the quality of the pulse may be based on the timing jitter of the clock signal.
• the timing jitter of the clock signal is substantially lower than the timing jitter of the digital pulse selection signal.
• the timing jitter of the clock may be substantially smaller, i.e. at least one or two order of magnitudes smaller, than a minimum pulse width of a pulse generated by the method.
• the minimum pulse width of the pulse generating system may be smaller than 400 ps, preferably smaller than 200 ps so that a clock may be selected that has a timing jitter smaller than 40 ps, preferably smaller than 20 ps, more preferably smaller than 5 ps peak-to-peak.
• the invention relates to a method of generating one or more high- quality control pulses per clock cycle at high frequencies and a pulse generating system that is configured to generate such pulses.
• the pulse generating system may be capable of generating a pulse signal that has (at least) two predefined temporal modes (no pulse, one early pulse, one late pulse or both an early and late pulse) per clock cycle.
• the pulse generating system has the ability to define the time difference and pulse width of each of the two temporal modes in a clock cycle.
• the pulse generating system may be configured to receive digital input data for each clock cycle from a digital pulse selector device.
• This input data may be used to determine whether to generate no pulses or one or more pulses and - if so - which of the temporal modes to generate. Furthermore, invention provides a simple, low-cost design of a high-quality, high frequency pulse generating system without compromising the signal characteristics. Further, the design can be implemented based on a small physical footprint and lower power consumption.
• the constructing of the first base pulse may include: in response to the logical value of the first digital pulse selection signal, copying the rising edge of the clock signal and constructing the first base pulse based on the copy of the rising edge.
• the first base pulse may be generated by a first logic block that includes a transparent latch or a circuit equivalent to transparent latch, for example a D- flipflop circuit or a circuit equivalent to a D-flipflop circuit, and a delay circuit.
• the constructing of the second base pulse may include copying the first base pulse and inverting the first base pulse.
• constructing the first control pulse may include: forming a first delayed base pulse by applying a first delay to the first base pulse; and/or, forming a second delayed by applying a second delay to the second base pulse wherein the first delay and/or second delay are selected such that the high-quality timing rising edge of the first base pulse is positioned before the high-quality timing falling edge of second base pulse; and, constructing the first control pulse based on the first delayed base pulse and the second delayed base pulse.
• the generating of the one or more control pulses may further include: constructing, depending on the logical value of a second digital pulse selection signal, a second base pulse, the first base pulse including a rising edge that has the timing quality of the clock signal; constructing a second base pulse based on the first base pulse, the second base pulse having a falling edge that has the timing quality of the clock signal; and, constructing a first control pulse based on the first base pulse and the second base pulse, wherein the timing quality of the rising edge and the falling edge have the timing quality of the clock signal.
• the one or more digital pulse selection signals, the first base pulse, the second base pulse and the first control pulse may be generated within one clock cycle of the clock signal.
• the one or more digital pulse selection signals may be generated by a digital pulse selector device such as a PFGA-based digital pulse selector device.
• the first control pulse may be generated by a pulse sequence generating device.
• the clock signal may generated by a clock that is external to the digital pulse selector device and the pulse sequence generating device.
• the method may further comprise sending the one or more control pulses to an optical device, preferably an intensity modulator, to control the optical device based on the one or more control pulses.
• an optical device preferably an intensity modulator
• the frequency of the clock may be selected between 100 and 500 MHz, preferably between 200 and 400 MHz.
• the width of the control pulse may be selected 100 and 600 ps, preferably between 150 and 500 ps, more preferably between 200 and 400 ps,.
• the timing jitter of the clock may be at least one order of magnitude, preferably two orders of magnitudes, smaller than the minimum pulse width of the control pulse.
• the invention may relate to a pulse sequence generator comprising: one or more logic blocks configured to receive at its input one or more digital pulse selection signals, preferably from an FPGA-based digital pulse selector based on a clock signal, and to generate one or more control pulses at its output, wherein the pulse sequence generator comprises at least a first pulse generator configured to: construct a first base pulse, the constructing of the first based pulse including providing a first digital pulse selection signal and the clock signal to the input of a transparent latch, wherein the output of the latch is connected via a delay circuit to a reset port R of the transparent latch; construct a second base pulse based on the first base pulse, the constructing including inverting the first base pulse and applying a delay to the first base pulse and/or second base pulse so that the rising edge of the first base pulse is positioned before the falling edge of second base pulse; and, construct a first control pulse based on the first base pulse and the second base pulse.
• the pulse sequence generator may comprise a second pulse generator configured to: construct a third base pulse, the constructing of the third based pulse including providing a second digital pulse selection signal and the clock signal to the input of a second transparent latch, wherein the output of second transparent latch is connected via a delay circuit to a reset port R of the second transparent latch; construct a fourth base pulse based on the third base pulse, the constructing including inverting the third base pulse and applying a delay to the third base pulse and/or fourth base pulse so that the rising edge of the third base pulse is positioned before the falling edge of fourth base pulse; and, construct a second control pulse based on the third base pulse and the fourth base pulse.
• a second pulse generator configured to: construct a third base pulse, the constructing of the third based pulse including providing a second digital pulse selection signal and the clock signal to the input of a second transparent latch, wherein the output of second transparent latch is connected via a delay circuit to a reset port R of the second transparent latch; construct a fourth base pulse based on the third base pulse,
• the invention may relate to a pulse generating system which may comprise a digital pulse selector, preferably an FPGA-based digital pulse selector, configured to receive a clock signal from a clock, and to generate one or more digital pulse selection signals, wherein the timing quality of the clock signal is higher than the timing quality of the pulse selection signal, preferably the timing jitter of the clock signal being lower than the timing jitter of the pulse selection signal.
• a digital pulse selector preferably an FPGA-based digital pulse selector
• the pulse generating system may further comprise a pulse sequence generator comprising one or more logic blocks configured for generating one or more control pulses based on the one or more pulse selection signals and the clock signal, wherein the pulse sequence generator may be configured to: constructing, depending on the logical value of a first digital pulse selection signal, a first base pulse, the first base pulse including a rising edge that has the timing quality of the clock signal; constructing a second base pulse based on the first base pulse, the second base pulse having a falling edge that has the timing quality of the clock signal; and, constructing a first control pulse based on the first base pulse and the second base pulse, wherein the timing quality of the rising edge and the falling edge have the timing quality of the clock signal.
• a pulse sequence generator comprising one or more logic blocks configured for generating one or more control pulses based on the one or more pulse selection signals and the clock signal, wherein the pulse sequence generator may be configured to: constructing, depending on the logical value of a first digital pulse selection signal, a first base pulse, the first base
• the constructing the first base pulse may include: in response to the logical value of the first digital pulse selection signal, copying the rising edge of the clock signal and constructing the first base pulse based on the copy of the rising edge.
• the first base pulse may be generated by a first logic block that includes a transparent latch or a circuit equivalent to transparent latch, for example a D- flipflop circuit or a circuit equivalent to a D-flipflop circuit, and a delay circuit.
• a transparent latch or a circuit equivalent to transparent latch for example a D- flipflop circuit or a circuit equivalent to a D-flipflop circuit, and a delay circuit.
• constructing the second base pulse may include copying the first base pulse and inverting the first base pulse.
• constructing the first control pulse may include: forming a first delayed base pulse by applying a first delay to the first base pulse; and/or forming a second delayed base pulse by applying a second delay to the second base pulse wherein the first delay and/or second delay are selected such that the high-quality timing rising edge of the first base pulse is positioned before the high-quality timing falling edge of second base pulse; and, constructing the first control pulse based on the first delayed base pulse and the second delayed base pulse.
• the generating of the one or more control pulses may further include: constructing, depending on the logical value of a second digital pulse selection signal, a first base pulse, the first base pulse including a rising edge that has the timing quality of the clock signal; constructing a second base pulse based on the first base pulse, the second base pulse having a falling edge that has the timing quality of the clock signal; and, constructing a first control pulse based on the first base pulse and the second base pulse, wherein the timing quality of the rising edge and the falling edge have the timing quality of the clock signal.
• the one or more digital pulse selection signals, the first base pulse, the second base pulse and the first control pulse a generated within one clock cycle of the clock signal.
• the one or more digital pulse selection signals may be generated by a digital pulse selector device.
• the first control pulse may be generated by a pulse sequence generating device.
• the clock signal may be generated by a clock that is external to the pulse selector device and the pulse sequence generating device.
• the system may be further configured to send the one or more control pulses to an optical device, preferably an intensity modulator, to control the optical device based on the one or more control pulses.
• the invention may relate to an optical encoder, preferably an optical encoder for quantum key distribution system or a quantum communication system, wherein the optical encoder comprises as a pulse generating system according to any of embodiments described in this application.
• the invention may also relate to a computer program product comprising software code portions configured for, when run in the memory of a computer, executing the method steps according to any of process steps described above.
• a computer program product comprising software code portions configured for, when run in the memory of a computer, executing the method steps according to any of process steps described above.
• Fig. 1 illustrates an optical encoder for controlling an optical modulator.
• Fig, 2 illustrates a pulse generating system according to an embodiment of the invention
• Fig. 3 depicts an implementation of a pulse generating system according to an embodiment of the invention
• Fig. 4 depicts part of a process for generating a pulse using a pulse generator according to an embodiment of the invention
• Fig. 5 depicts part of a process for generating a pulse using a pulse generator according to an embodiment of the invention
• Fig. 6 depicts part of a process for generating a pulse using a pulse generator according to an embodiment of the invention
• Fig. 7 depicts a flow diagram of a process of generating pulses for controlling an optical device according to an embodiment of the invention.
• Fig. 8 depicts an example of a QKD system comprising an optical encoder according to an embodiment of the invention.
• Fig. 1 illustrates an optical encoder configured to control an optical device, for example an intensity modulator.
• the optical encoder may comprise pulse generator 102 connected to a digital pulse selector 104.
• the digital pulse selector may be configured to generate a digital pulse selection signal for triggering the pulse generator to generate a particular sequence of pulses.
• Both the digital pulse selector and the pulse generator may be configured to receive a clock signal from a clock 100, which is configured to produce a high-frequency clock signal with a high timing quality.
• the term timing quality may refer to the timing jitter of the clock signal which is a well-known noise source in electronics and telecommunications. Timing jitter may be quantified based on well-known measurement units such as an RMS value or a peak-to-peak value.
• the timing jitter may be substantially smaller, i.e. at least one or two order of magnitudes smaller than the minimum pulse width of the pulse generator.
• the minimum pulse width of the pulse generator may be smaller 250 ps, preferably smaller than 200 ps, more preferably smaller than 100 ps.
• the clock signal may be used to synchronize the digital pulse selector with the pulse generator so that each clock cycle a pulse sequence may be generated. Based on the pulse selection signal and the clock signal, the pulse generator may generate a sequence of control pulses for controlling for example, one or more optical modulators, such as an optical intensity modular (OIM) 108 and/or an optical phase modulator 110, to generate a photonic qubit.
• OIM optical intensity modular
• a laser 106 configured to generate a weak coherent laser pulse may be attenuated to single photon level by a system of modulators.
• the photonic qubit generator of Fig. 1 allows the generation of a photonic qubit comprising two independent temporal photonic modes as illustrated by two short photonic pulses 114i,2 that are “carved out” from a relatively long weak coherent laser pulse 112.
• Such qubit is sometimes referred to as a time-bin encoded qubit, which may include an “late” temporal photonic mode ⁇ l) and an “early” temporal photonic mode
• such qubit may include different states e.g. both an early and a late temporal mode, only an early or a late mode or no modes.
• the pulse generator may be connected to a laser 106, e.g. a continuous wave (CW) laser, for generating a weak coherent laser pulse, which may be modulated using the intensity modulator 108 and phase modulator 110.
• the pulse selector may generate a pulse selection signal representing a particular time bin, which is subsequently used by the pulse generator to generate control pulses for controlling the modulators to produce the time bin qubit.
• the pulse generator may trigger the laser to generate a weak coherent laser pulse 112 of a predetermined wavelength, which is subsequently modulated by the optical intensity modulator based on the generated control pulses.
• the phase modulator may act on one of the two photonic modes to tune the phase between the two modes.
• the time interval between the two temporal modes needs to be smaller than the coherence time of the weak coherent laser pulse. Additionally, it should be large enough to ensure that the modes are independent, i.e. do not overlap each other in time. Such conditions require the pulse generator to generate, per clock cycle, zero, one or two short pulses, having a width of 250 ps or smaller at a clock frequency of 100 MHz or higher. Additionally, a major constrained for the design of the pulse generator is that the optical modes of a time-bin encoded qubit should be indistinguishable.
• the indistinguishability of optical modes may be defined based on the pulse fidelity of the generated optical pulses, which may be determined by calculating the maximal value of the cross-correlation between the pulse signals.
• the pulse fidelity of the optical pulse is largely determined by the analogue pulses the optical modulator receives from the pulse generator.
• the pulse generator according to the invention is configured to generate electronic pulses for driving an optical intensity modulator at high frequencies, wherein the pulses are as narrow as possible and have a high pulse fidelity, e.g. no memory effects are present in the shape of the generated pulses.
• a pulse should look identical regardless of whether or not there was a pulse preceding it.
• Fig. 2 illustrates a pulse generating system according to an embodiment of the invention.
• the figure illustrates a pulse generating system 200 that is configured to generate a high-frequency, high-fidelity analog pulse signal, e.g. an analog pulse train signal (pulse sequences) for driving an optical device.
• the pulses in the pulse signal may be constructed such that they are indistinguishable or at least substantially indistinguishable (both within one clock cycle as between different clock, cycles).
• the pulse generating system is particularly suitable for generate a pulse sequence for controlling an optical modulator to form the optical states (ths temporal modes) of a time-bin qubits.
• Such qubits may be used in known QKD protocols, such as the BB84 protocol or one of its variants.
• the pulse generating system may include a pulse selector 202 configured to generate pulse selection information for a pulse sequence generator 2Q4. Both the pulse selector and the pulse sequence generator may be connected to a clock 2Q5 so that the pulse selection and pulse generation can be synchronized.
• the clock may be configured to produce an (external) high-quality clock signal having a low timing jitter.
• the clock may be implemented as a crystal oscillator including a crystal and oscillation circuit are combined in the same package.
• a quartz piezo-electric oscillator may output a clock signal as a square wave with 50% duty cycle.
• Fig. 28 depicts examples of pulse signals that may be generated by the pulse generator in one clock cycle based on the pulse selection information.
• the pulse selection information may be used to trigger the pulse sequence generator to make a sequence of, in this example, either two pulses, one pulse and one “no” pulse or two “no” pulses at a predetermined paint af a dock cycie. These different pulse signals may be used to generate different photonic excitations, e.g. time-bin qubits.
• the pulse selector may be configured to generate amodule selection signal 207 ⁇ ,2 , e.g. binary pulse selection signals, for input to themodule sequence generator. In an embodiment, for each pulse in the pulse signal, the pulse selector may generate a pulse selection signal, e.g. a logic high or logic low signal, which is fed to the input of the pulse sequence generator.
• each pulse selection signal may be input to a base pulse generator circuit 206 ⁇ ,2 which generates a basemodule of a predetermined amplitude and length at its output.
• the rising edge of the basemite may be formed based on the rising edge of the clockmite.
• the base pulse generator may be triggered to generate a basemodule wherein the rising edge of the base pulse has a high-quality low-jitter form factor.
• Each of the base pulses are then fed to amodule shaper 2G8I,2 which is configured to construct amodule of a predetermined width based on the base pulse.
• the pulse shaper may be configured to determine an inverted base pulse, which has a high-quality falling edge.
• the base pulse and a delayed, inverted basecorrecte may then be used to construct a pulse of a predetermined width and at a predetermined position in the clock cycie.
• Themodule may be constructed based on the high-quality rising edge and failing edge of the base pulse and the inverted basecorrecte respectively.
• a baseMOe generator and a pulse shaper may form a high-quality pulse generator configured to generate a narrow, low-jitter pulses wherein the rising edge and falling edge of the pulse are of the same quality as the edges of the clock signal.
• theannoe sequence generator 204 may include a plurality of pulse generators 209 ⁇ ,2, a first pulse generator 209 ⁇ formed by first baserige generator 2G6i and firstinstalle shaper 208i and a second pulse generator 2002 formed by second base pulse generator 2062 and second pulse shaper 2G8s.
• themodule generators may be provided on one common PCB board.
• a computer 208 may be used to set a width for each pulse and the position of each pulse within a clock cycle.
• Amite combiner 212 may be used to combine the two outputs of the two pulse generators into a combinedmodule signal 214, a pulse sequence signal, which - depending on the pulse selection signal - may comprise per clock cycie two pulses, one pulse or no pulses as depicted in Fig. 2B. Further embodiments may include more than two pulse generators on a common PCB board for generating a plurality of pulses per clock cycle.
• the pulse generating system may be used to drive optical component devices such as switches, phase and intensity modulators, intensifiers as well as resistive loads.
• the analog pulse signals at the output of theroue generating system may be used as a modulation signal for signal generation in optical communication, in quantum signal processing, and a stimulus and clock signal to analyse and test another electrical device.
• the pulse generating system allows the generation of pulses at high frequencies, e.g. 100 MHz or higher, and can generate two or more analog pulses per clock period, wherein each pulse can be as narrow as 250 ps or smaller, while still making sure there are no memory effects present in the pulse shape.
• a pulse looks identical regardless of whether or not there was a pulse preceding it.
• the pulse width should be at least a few times the resolution of the pulse generation, which in an embodiment may be smaller than 5 ps, preferably smaller than 3 ps.
• each pulse can be set by delay values with a resolution of 5 ps (when using a 200 MHz clock signal).
• the delay can be set over a 5 ns range and if more range is needed, the clock signal can be inverted.
• the pulse generating system may be configured to receive one or more input parameters for setting a time difference and/or a pulse width for each of the temporal modes in a clock cycle. This way, time-bin qubits with different characteristics can be generated in a flexible way.
• the pulse generator may be configured (or be programmed) to determine, for each clock cycle, which of the temporal modes (zero, one (early or late) or two (both early and late)) should be generated. Despite these requirements, pulse generating system may have a small physical size and lower power consumption.
• Fig. 3 depicts an implementation of a pulse generating system according to an embodiment of the invention.
• the pulse generating system may include a digital pulse selector 304, e.g. a FPGA-based digital pulse selector, configured to generate two-level binary output signals 314I,2 connected to a pulse sequence generator 303 and a clock 306 in a similar way as described with reference to Fig. 2.
• each binary output signal may be provided to the input of a pulse generator configured to generate a high-quality control pulse based on the binary output signal and a clock signal generated by a clock 306.
• the figure illustrates two pulse generators, each being connected via an output stage 324 to an output of the pulse sequence generator.
• Each of the pulse generators may comprise a number of logic blocks, wherein the logic blocks 316i,319i,320i,322i (highlighted in grey) form the first pulse generator which has an input 314i that is connected to a first output of the pulse selector.
• a similar set of logic blocks 3162,3192,3202,3222 (highlighted in white) may form a second pulse generator, which has an input 3142 that is connected to the second output of the pulse selector.
• An output stage 324 of the pulse generating system may be configured to combine the outputs of the logic combiners 322i,20f the first and second pulse generators into an analog output signal 312 of the pulse generating system.
• the output signal may include zero, one or multiple pulses, which may be fed to the input of further electronics, e.g. an amplifier 314.
• each separate pulse generator may generate pulses (one per clock cycle) so that the analog pulses of the output signal are independently generated and only combined at the output stage 324.
• the clock may be connected to the pulse selector so that each clock cycle, the pulse selector may generate different binary output signals.
• the logical value of the binary output signal may determine if during the clock cycle a pulse generator should generate a pulse or not.
• a plurality, e.g. two, binary output signals of the pulse selector may represent a particular pulse sequence that needs to be generated in a clock cycle by the pulse generators that process the binary output signals.
• Each clock cycle different pulse sequences can be generated for e.g. controlling an optical device such as an optical modulator (not shown). For example, in case of two binary output signals, four different pulse sequence signals (two pulses, one pulse, no pulse or vice versa or two times no pulse) can be generated.
• the clock may be a high-quality clock wherein the timing quality of the rising and falling edges of the clock is higher than the timing quality of the binary output signal of the pulse selector.
• the timing quality may be expressed in terms of jitter. In that case, the jitter associated with the edges of the clock may be lower than the jitter of the binary output signal of the pulse selector.
• Each of the logic outputs 314i,20f the pulse selector may be used to trigger the generation of a high-quality pulse using logic circuitry that forms a pulse generator.
• a first logic output 314i of the pulse selector is connected to a first pulse generator including logic blocks that are highlighted in grey.
• the logic bocks building the first pulse generator may include one or more first logic blocks forming a first base pulse generator (as described with reference to Fig. 2A), e.g. a (transparent) latch comprising a flip flop 3161 such as a D flip-flop or a circuit equivalent to a D flip flop and a delay circuit 319i produce a base pulse.
• the logic blocks may further comprise one or more second logic blocks forming a first pulse shaper (as described with reference to Fig. 2A), including an inverter-delay circuit 320i and a logic combiner 322i for pulse construction of a narrow, high-quality control pulse based on the base pulse.
• the second pulse generator may include logic blocks forming a second base pulse generator comprising a flip flop 3162 and a delay circuit 3192, and logic blocks a second pulse shaper comprising inverter-delay circuit 3202and a logic combiner 3222.
• the transparent latch may be configured to register the logic output of the pulse selector so that the timing stability requirements, in particular timing jitter, of the pulse selection circuit that is configured to generate the control signals can be eased.
• each of the binary output states of the pulse selector may be connected to its own dedicated pulse generator.
• the transparent latch may be configured to generate a base pulse based on the clock signal and the logic output of the pulse selector.
• the transparent latch may be configured to generate a base pulse signal using an edge, preferably the rising edge, of the clock signal. For example, in an embodiment, if the binary input state is a logic high and there is a rising edge transition in the clock signal, the transparent latch will be triggered to set its output to a logic high.
• the latch may be “transparent” as the output Q follows the input D when the clock input is high thereby transferring the binary information at the input (as generated by the pulse selector) directly to the output as if the flip-flop was not there (i.e. making it “transparent”).
• the output of the latch is connected via a delay circuit to the reset port R of the latch.
• the latch in response to a logic high at the output Q of the latch, the latch will reset itself after a predetermined delay time At, e.g. 2 ns or less, setting the output Q of the latch back to a logic low.
• the delay limits the maximum pulse width of the base pulse and allows for consecutive pulses at each clock cycle when the control inputs are in a fixed state.
• the rising edge of the base pulses has the timing quality associated with the clock, while the timing quality of the falling edge, which is determined by the reset logic, does not have such high timing quality.
• Fig. 4 The processing of the input states by the transparent latch is depicted in Fig. 4 showing a clock signal CLK 403 of a predetermined period Ti , wherein the clock signal that has high-timing quality rising and falling edges 404I,2.
• the digital pulse selector may provide a logic high signal 402 to the input of the transparent latch so that the rising edge of the clock will trigger the output Q of the latch to switch to a logic high.
• the timing quality of the digital pulse signal may have relatively large timing jitter 401.
• the logic high output signal will trigger the generation of delayed reset signal 410, which is provided to the reset gate R of the latch, forcing the latch to reset itself so that the output Q of the latch will switch to a logic low.
• the reset signal may be affected by timing jitter due to the reset circuity.
• a base pulse signal 405 is generated having a rising edge 404i having a timing quality of the clock signal and a falling edge 4042 having a timing quality of the reset signal.
• first output 3181 of the first latch 3161 may be connected to the inverter-delay circuit 320i which is configured to generate two signals for the logic combiner 322i, in this example a logic AND gate, to produce a first high-quality pulse of a predetermined first duration.
• the generation of these input signals are illustrated in Fig. 5, depicting first base pulse 502 that is input to the inverter-delay circuit.
• This circuit may generate a first output signal 504 which is formed by delaying the first base pulse based on a first delay value. For example, in Fig. 5 a first delay value of 2 ns was selected.
• a second output pulse 506 may be generated by the inverter-delay circuit based on the first base pulse 502. As shown in the figure, a delay between the two output pulses may be selected such that that the high-quality timing rising edge of the first output signal 504 is positioned before the high-quality timing falling edge of second output signal 506. This way, the overlap between the two output pulses may define a low jitter output pulse.
• the second output signal may be generated by inverting the first base pulse and by delaying the inverted pulse based on a second delay value. For example, in the example of Fig. 5, a second delay value of 2.3 ns was selected. The inversion operation will cause the second base pulse to have a high-quality timing falling edge.
• the first and second delay values may be selected such that the high-quality timing rising edge of the first output signal is positioned before the high-quality timing falling edge of second output signal. For example, in case of a clock signal of 200 MHz, the delay values may be selected between 2 and 7 ns.
• the inverter-delay circuit 320i may be configured to receive the delay values as an external signal by a computer. Thereafter, logic combiner 322i, a logic gate, e.g. an AND gate, may be used to combine the first and second output signal to form a first control pulse 508, that has the high quality rising edge of the first base pulse and the high quality falling edge of the second base pulse. Further, the width of the control pulse may be controlled by the delay values.
• the scheme allows the independent generation of a high- quality, narrow width, electrical control pulse may be constructed which may be used to control an optical device or the like.
• the pulse width can be easily controlled by the relative shift between the first and second base pulse providing a pulse width smaller than 1 ns, preferably smaller than 500 ps, even more preferably smaller than 250 ps without any notable signal distortion.
• each logic output of the pulse selector is connected to a pulse generator, which generates a high-quality pulse according to the signal processing schemes of Fig. 4 and 5. Then, the individual pulses may be combined into a pulse sequence, i.e. a sequence of high quality pulses.
• the delay values provided to the first pulse generator to construct the first output pulse and the delay values provided to the second pulse generator to construct the second output pulse may be selected such that they are relatively shifted in time.
• the output stage 324 of the pulse generating system may include the first logic combiner 322i, e.g.
• an AND gate for combining outputs 3211 of the first inverter-delay circuit and the second logic combiner 322a, e.g. a NOR gate with inverted inputs which effectively functions as an AND gate, for combining outputs 3212 of the of the second inverter-delay circuit.
• the output of the first and second logic gates322i,2 may be combined using a third logic gate 326, e.g. an logical OR gate, into the output signal, configured to combine the outputs of the first and second pulse generator into a pulse sequence.
• Fig. 6 depicting a first pulse 602 at the output of the first pulse generator and a second pulse 604 that is shifted in time relatively to the first pulse at the output of the second pulse generator and combined by the logic circuit to form a pulse sequence 606.
• different pulse sequences may be generated, e.g. pulse sequences as depicted in Fig. 2B which may be used to generate time bin qubits.
• the output stage of the pulse generating system effectively needs to work at very frequencies e.g. 5 GH or higher.
• the wiring between the logic blocks on the PCB on which the electronics are designed such that delays due to differences in transmission line lengths are eliminated.
• the second logic combiner which has AND gate functionality may be implemented as a NOR gate with inverted inputs. This way, a high-quality high- frequency output signal can be guaranteed.
• Fig. 7 depicts a flow diagram of a process of generating pulses for controlling an optical device according to an embodiment of the invention.
• the method may include a first step 702 wherein a clock signal and one or more logical pulse selection signals are received, wherein the timing quality of the clock signal is higher than the timing quality of the pulse selection signal.
• a first base pulse in constructed, wherein the first base pulse comprises a rising edge that has the timing quality of the clock signal.
• a second base pulse may be constructed based on the first base pulse, wherein the second base pulse has a falling edge that has the timing quality of the clock signal (step 706).
• the first base pulse and the second base pulse are combined to form a control pulse (step 708), wherein the timing quality of the rising edge and the falling edge have the timing quality of the clock signal.
• Fig. 8 depicts an example of a QKD system comprising an optical encoder according to an embodiment of the invention.
• the figure illustrates an MDI-QKD design known from the article by Valivarthi et al, A cost-effective measurement-independent quantum key distribution system for quantum networks., Quantum Sic. Technol. 2(2017) that includes one or mere optical encoders as described with the embodiments in this application.
• the system 800 may indude a first and second qubit generating modules 802, 804. Both qubit generating modules may be configured to prepare qubits and send them via optical fibers 8881,2, 8881,2 to a central measurement station 810, which may include a so-called Bell state measurement (BSM) module.
• BSM Bell state measurement
• Each qubit generating module may include an optical controller 812 for controlling a laser system 814, such as a continuous wave laser, to generate coherent optical pulses.
• optical controller 812 may comprise a pulse generating system as e.g. described with reference to Fig. 2-5 for generating each clock cycle a pulse signal wherein the pulse signal may either include zero, one or two pulses.
• the optical pulses generated by the laser system may be processed by first intensity modulator IM1 818, which is controlled by the pulse signals of the pulse generating system.
• the first intensity modulator may “carve out” time-bin optical modes, early and/or late time bins, to define a photonic qubit.
• the time-bin optical modes may be processed by a phase modulator PM 818 to control a phase between optical modes.
• a further second intensity modulator I M2 828 may be used to control the average number of photons associated with the qubit.
• both qubit generating modules (Alice and Bob) may generate time-bin qubits in a synchronized way which are transmitted via fiber connections 8062, 8882 to a central measurement station 810.
• the optical modes transmitted by the qubit generating module should be indistinguishable in all degrees of freedom (spatial, spectral, polarization and temporal).
• the central measurement station 810 may include a clock distribution system, including an 822 connected to a system of lasers 824 to produce an optical clock signal for the qubit generators.
• This clock signal may be transmitted via the optical fibers 8O61, 88 ⁇ i to the qubit generating modules, which use this high-quality clock signal to bath synchronize the qubit generation and to produce a high-quality clack signal for generating the pulses that drive the optical modulator.
• Further central measurement station may further comprise polarization beam splitters (BS) 8861,2 and a polarization maintaining beam splitter 832 and superconducting nanowire single-photon detectors (SNSPDs) 834I,2 to form a BSM measurement set up, wherein the detectors are configured to generate electrical signals that are the outcome of the BSM measurement.
• the measurement station may further include a so-called Hong-Ou-Mandel dip measurement (HOM) 832 for determining the indistinguishability of the time bins and a BSM analyzer module 836 which is configured to analyze the electrical signals produced by the SNSPDs for the generation of a secret key.
• HOM Hong-Ou-Mandel dip measurement
• pulse generating systems are particularly suitable for a MDI-QKD QKD system, they may also be advantageously used in other QKD systems, optical (quantum) communication systems, quantum signal processing systems as well as a signal generator for generating stimulus and clock signals to analyze and test electrical devices.
• the techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set).
• IC integrated circuit
• a set of ICs e.g., a chip set.
• Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

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