Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
  • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
  • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
  • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
  • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
  • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
  • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/26—Materials of the light emitting region
  • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
  • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
  • H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0093—Wafer bonding; Removal of the growth substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
  • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
  • H01L33/105—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector with a resonant cavity structure

Definitions

• the invention relates to the field of optoelectronics. It finds a particularly advantageous application in the field of light-emitting diodes based on gallium nitride (GaN) having a three-dimensional structure.
• GaN gallium nitride
• LEDs typically comprise a so-called active region where radiative recombinations of electron-hole pairs occur, which make it possible to obtain light radiation having a main wavelength.
• LEDs can be configured to produce light radiation with a primary wavelength in the blue, or in the green, or in the red. This main wavelength depends in particular on the configuration of the active region.
• the active region or active layer of a GaN-based LED typically comprises InGaN-based quantum wells.
• These InGaN-based quantum wells can extend along different crystallographic planes, for example polar planes (c or -c planes of the hexagonal crystallographic structure), non-polar planes (a or m planes of the hexagonal crystallographic structure) or semi-polar.
• axial 3D LEDs can be done by molecular beam epitaxy MBE (acronym for Molecular Beam Epitax ⁇ ).
• MBE Molecular Beam Epitax ⁇
• This growth technique makes it possible to obtain, unlike other conventionally used growth techniques, a localized deposit of InGaN at the top of GaN-based wires. InGaN-based quantum wells can thus be formed along polar planes.
• MBE molecular beam epitaxy does not have sufficient performance and is not a technique compatible with an industrial manufacturing process.
• Other growth techniques typically organometallic precursor vapor phase epitaxy (MOVPE), do not allow axial structures to be grown with good control. Parasitic growth on the sides of 3D structures is usually observed, leading to core-shell-like structures.
• the present invention aims to at least partially overcome the drawbacks mentioned above.
• an object of the present invention is to provide a method of manufacturing one or more optoelectronic devices, which is industrially compatible.
• Another object of the present invention is to provide an optoelectronic device, in particular an axial 3D LED based on GaN, which can be manufactured in an optimized manner.
• an optoelectronic device comprising a substrate and, on a first face of the substrate, at least one stack in a longitudinal direction, said stack comprising at least one injection layer. of a first type of carriers and an active layer.
• the optoelectronic device comprises a growth mask comprising a plurality of openings and the active layer of the at least one stack is confined in at least one opening of said openings and does not extend outside said at least one opening.
• the growth mask typically makes it possible to at least partially guide a growth of the stack in the longitudinal direction. It is preferably configured to provide this guidance function.
• the active layer of the device has a pseudo two-dimensional structure within the at least one opening.
• This pseudo two-dimensional structure is linked to the presence of the growth mask over the entire height of the active layer.
• the device thus advantageously has a 3D architecture while benefiting from a pseudo-2D structure.
• the pseudo-2D structure of the active layer makes it possible to easily form, in a manner compatible with an industrial manufacturing process, quantum wells according to a single type of crystallographic planes, in particular according to polar planes.
• This 3D architecture is called axial.
• the integration of such a growth mask advantageously makes it possible to use MOVPE to respectively form the injection layer and the active layer according to an axial 3D architecture.
• the growth mask can be made of a dielectric material so as to electrically insulate the substrate from a metallic contact subsequently deposited on the top of the stacks, for example. It can also be transparent so as to allow light radiation emitted or received by the stacks to pass.
• the stack (s) form axial LEDs with a 3D structure within the growth mask.
• the device therefore comprises at least one axial LED in the at least one opening of the growth mask.
• This axial LED is preferably believed by vapor phase epitaxy at Organometallic precursors (MOVPE) directly within the at least one opening of the growth mask.
• a second aspect relates to a method of manufacturing an optoelectronic device comprising a substrate and, on a first face of the substrate, at least one stack in a longitudinal direction of at least one injection layer of a first type of carriers and an active layer. This process includes:
• a supply of the substrate preferably comprising a nucleation layer
• Formation of a growth mask on the substrate said growth mask comprising at least one opening in the longitudinal direction through which is exposed an area of the substrate or of the nucleation layer,
• the formations of the injection layer and of the active layer are carried out by vapor phase epitaxy with organometallic precursors (MOVPE) in the longitudinal direction in at least one opening.
• MOVPE organometallic precursors
• MOVPE organometallic precursor vapor phase epitaxy formation of the injection layer and / or active layer improves the industrial compatibility of the 3D axial LED manufacturing process.
• MOVPE does not allow forming such axial 3D LEDs and that it is necessary to resort to MBE to fabricate such structures.
• the known solutions based on MBE aim in particular to size the equipment making it possible to implement MBE, so that they are compatible with industrial production.
• MOVPE deposit of an injection layer and / or an active layer on a protruding or recessed relief covers the sides of said relief, and the 3D structure obtained therefore has a so-called radial architecture.
• the invention provides a growth mask for an optoelectronic device comprising a substrate and, on a first face of the substrate, at least one stack in a longitudinal direction, said stack comprising at least one injection layer of a first type of carrier and an active layer.
• the growth mask has a plurality of openings.
• the growth mask is configured to at least in part guide growth of the stack in the longitudinal direction.
• the growth mask is shaped so that the active layer of the at least one stack is confined within at least one opening of the openings of the growth mask and does not extend outside said at least one opening.
• FIGURES 1A to 1E illustrate a method of forming an optoelectronic device according to an embodiment of the present invention.
• FIGURES 2A to 2F illustrate a method of forming an optoelectronic device according to another embodiment of the present invention.
• FIGURE 3A is a transmission electron microscopy (TEM) image of an optoelectronic device according to one embodiment of the present invention.
• FIGURE 3B is a transmission scanning electron microscopy (STEM) image of an optoelectronic device according to one embodiment of the present invention.
• TEM transmission electron microscopy
• FIGURES 4A-4G illustrate a method of forming an optoelectronic device according to yet another embodiment of the present invention.
• the drawings are given by way of example and do not limit the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily on the scale of practical applications. In particular, the dimensions of the various elements of the optoelectronic device are not representative of reality.
• the invention according to its first aspect includes in particular the optional characteristics below which can be used in combination or alternatively.
• the injection layer of the first type of carriers is confined in the at least one opening of the growth mask.
• the injection layer of the first type of carrier bears on a nucleation layer made of a material different from the material of said injection layer.
• said at least one stack is bordered laterally by a wall of the at least one opening, over a height greater than or equal to the sum of the thicknesses of the injection layer and of the active layer.
• the stack further comprises distributed Bragg mirrors (DBR) so as to form a resonant cavity in the longitudinal direction.
• DBR distributed Bragg mirrors
• the device comprises a first stack and a second stack respectively comprising a first active layer and a second active layer confined respectively in a first opening and a second opening of the growth mask, said first and second openings respectively having a first surface and a second surface, taken in a plane transverse to the longitudinal direction, different from each other, and said first and second active layers respectively having a first thickness and a second thickness, taken in the longitudinal direction, different from each other.
• the first and second stacks respectively comprise a first injection layer of the first type of carriers and a second injection layer of the first type of carriers confined respectively in the first and second openings of the growth mask, said first and second injection layers respectively having a first thickness and a second thickness, taken in the longitudinal direction, which are different from one another.
• the device comprises a plurality of stacks and active layers confined in a plurality of openings of the growth mask, and the openings having surfaces, taken in a plane transverse to the longitudinal direction, substantially equal to each other are separated in pairs by a separation distance ds chosen so that said openings form a resonant cavity in a plane transverse to the longitudinal direction.
• Said resonant cavity is therefore typically formed by a plurality of stacks of the same size, more particularly of size less than 1 ⁇ m. This makes it possible to form a photonic crystal. This therefore allows a more precise and reliable selection of the emission wavelength, due to the filter formed by the photonic crystal.
• a resonant cavity is here intrinsically linked to the existence of a network of openings of the same sizes or the same surfaces.
• three openings having three different sizes for example to emit at three different lengths, are not sufficient to form a resonant cavity.
• the formation of a photonic crystal implies in particular a very low tolerance on the pitch of the aperture network and on the diameter of the stacks.
• growing the stacks through a growth mask - rather than on a flat substrate - advantageously allows excellent control of the critical dimensions allowing this photonic crystal to be obtained (separation distance, size of apertures).
• a planarization is carried out after the growth of the stacks, for example by means of a filling of the openings above the stacks with a planarization material.
• This planarization can be done by deposition by centrifugation (known under the name of "spin coating"), optionally followed by mechanical-chemical polishing (known by the acronym "CMP” meaning Chemical Mechanical Polishing). This planarization improves the quality of the photonic crystal.
• the injection layer of the first type of carrier has a front face in contact with the active layer within the opening, and a rear face opposite the front face and in contact with a transparent conductive layer.
• a transparent contact on the rear face can advantageously be produced by a chip flipping and transfer process, commonly called a “flip chip” (meaning “chip flipping”).
• the invention according to its second aspect comprises in particular the optional characteristics below which can be used in combination or alternatively:
• the formation of the injection layer and the active layer are carried out by vapor phase epitaxy with organometallic precursors (MOVPE) in the longitudinal direction in at least one opening.
• MOVPE organometallic precursors
• the growth mask comprises at least a first opening and a second opening having respectively a first surface and a second surface, taken in a plane transverse to the longitudinal direction, different from one another.
• the formation of the active layer comprises a formation of a first active layer within the first opening and simultaneously, a formation of a second active layer within the second opening so that said first and second layers active have thicknesses, taken in the longitudinal direction, different from each other.
• the growth mask includes a plurality of openings.
• the openings having surfaces, taken in a plane transverse to the longitudinal direction, substantially equal to each other are separated in pairs by a separation distance ds chosen so that said openings form a resonant cavity in a plane transverse to the longitudinal direction.
• several resonant cavities can be formed by means of a single growth mask.
• a plurality of first openings having a first size and separated by a first separation distance corresponding to a first network pitch typically form a first resonant cavity.
• a plurality of second openings having a second size and separated by a second separation distance corresponding to a second network pitch typically form a second resonant cavity.
• These first, second and third resonant cavities can coexist within the growth mask, for example respectively at the level of first, second and third juxtaposed and distinct zones of the growth mask, or in an intermixed manner.
• These first, second and third resonant cavities typically make it possible to filter and / or exacerbate the emission of light according to first, second and third wavelengths.
• the separation distance ds is between 50 nm and 700 nm.
• the substrate comprises a layer of a semiconductor material on the nucleation layer and the formation of the growth mask comprises:
• the production of the growth mask from a passivated semiconductor material makes it possible to better control the diameter and the positioning of the openings for large openings. This makes it possible in particular to limit or avoid the appearance of deformations along the height of the openings.
• Passivation of the openings makes it possible to use GaN to make a large part of the growth mask. This makes it possible to avoid having to resort to the deposition of a specific material to form the growth mask.
• the GaN-based substrate can be directly used as a growth mask template. Thus, the etching of the openings is done directly in said substrate, and a simple passivation step may typically be sufficient to finalize the formation of the growth mask.
• the mask is thus produced in a layer of a semiconductor or conductor material, such as GaN, passivated at the level of the walls of the openings and between the openings.
• the bottom of the openings is not passivated, or the passivation layer is removed at the bottom of the openings, so as to allow the growth of stacks in the openings.
• the openings are preferably made on a only part of the height of the GaN-based layer of the substrate, so that the bottom of the openings directly corresponds to an exposed part of said GaN-based layer.
• Such a growth mask comprising a part of the GaN-based substrate advantageously makes it possible to significantly increase the quality of the growth of the stacks in the openings.
• the part of the GaN-based substrate forming the bottom of the openings forms a nucleation layer for the growth of the stack. It is therefore not necessary to provide an additional nucleation layer on the bottom of the openings. This helps reduce the overall thickness of the stack. This reduction in thickness of the stack considerably improves the crystalline quality of the various layers of the stack, in particular of the active zone buried within the stack.
• the passivation of the flanks or walls of the openings which allows growth directed in the longitudinal direction, without parasitic growth on the flanks of the openings, also makes it possible to avoid the recombinations of carriers which are likely to occur around the periphery of the openings. stacks.
• This passivation also helps inhibit the growth of the stack layers on the top face or top of the growth mask. This helps promote the growth of stacks at the bottom of the cavities. This passivation also makes it possible to isolate the upper layers of the stacks, for example the GaN-p-based hole injection layer, from the substrate, for example based on GaN-n.
• the semiconductor-based part of such a growth mask can advantageously improve light extraction and / or modulate the far field of light emission.
• the choice in the composition of the semiconductor can in particular exacerbate one and / or the other of these effects.
• the method comprises, before the passivation, forming a reflective layer at least in part on the wall of the at least one opening.
• the method comprises, after formation of the active layer: - Formation of an electron blocking layer on the active layer,
• Such a method is of the “flip chip” type.
• the growth mask comprises a plurality of openings distributed according to first, second and third sub-assemblies respectively comprising openings having first, second and third average surfaces, taken in a plane transverse to the longitudinal direction, different between them.
• the first, second and third average surfaces are chosen so as to form respectively first, second and third subsets comprising respectively active layers having first, second and third thicknesses, taken in the longitudinal direction, different between them, said subsets of active layers being configured to emit light radiations having respectively first, second and third wavelengths different from one another.
• the first, second and third wavelengths belong to the visible electromagnetic spectrum and are chosen from this spectrum so as to emit red, green and blue light, respectively.
• the formation of the injection layer of the first type of carrier takes place simultaneously within all the openings so that the thickness of said injection layer varies as a function of the surface, taken in a transverse plane. in the longitudinal direction, openings.
• the formation of the active layer takes place simultaneously within all the openings so that the thickness of said active layer varies depending on the surface, taken in a plane transverse to the longitudinal direction, of the openings.
• the injection layer of the first type of carriers (30) is based on GaN, and the active layer is based on InGaN.
• the manufacturing method and the optoelectronic device can comprise, mutatis mutandis, any one of the optional characteristics above.
• the technical characteristics described in detail for a given embodiment can be combined with the technical characteristics described in the context of other embodiments described by way of example and not by way of limitation.
• the number of openings, the different shapes of openings and / or the different separation distances illustrated in the figures can be combined so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.
• the manufacturing method is in particular dedicated to the manufacture of LEDs having a 3D architecture (3D LED).
• the invention can be implemented more widely for various optoelectronic devices with 3D architecture, and in particular those comprising active layers.
• active layer or active region of an optoelectronic device is meant the layer or region from which the majority of the light radiation supplied by this device is emitted, or the region from which the majority of the light radiation received by this device is captured.
• the invention can therefore also be implemented in the context of laser or photovoltaic devices.
• the relative arrangement of a third layer interposed between a first layer and a second layer does not necessarily mean that the layers are directly in contact with each other. , but means that the third layer is either directly in contact with the first and second layers, or separated from them by at least one other layer or at least one other element.
• an electron blocking layer interposed between the active layer and the injection layer of the second type of carriers is not necessarily directly in contact with one or the other, and other layers exhibiting other functions can possibly be added.
• stages in the formation of the different elements are understood in a broad sense: they can be carried out in several sub-stages which are not necessarily strictly successive.
• diameter is meant the largest transverse dimension of the opening.
• the openings do not necessarily have a circular cross section.
• this section can be hexagonal.
• the diameter then corresponds to the distance separating two opposite vertices of the section hexagonal.
• the diameter may correspond to an average diameter calculated from the diameter of a circle inscribed in the polygon of the cross section and the diameter of a circle circumscribed by this polygon.
• the separation distance ds is the smallest distance between two adjacent openings.
• LED light-emitting diode
• LED simply “diode”
• An “LED” can also be understood as a "micro-LED”.
• M-i refers to the material M which is intrinsic or not intentionally doped, according to the terminology usually used in the field of microelectronics for the suffix -i.
• M-n refers to the material M doped with N, N + or N ++, according to the terminology usually used in the field of microelectronics for the suffix -n.
• M-p refers to the material M doped with P, P + or P ++, according to the terminology usually used in the field of microelectronics for the suffix -p.
• a substrate a layer, a device, "based" on a material is meant
• a layer based on gallium nitride can for example comprise gallium nitride (GaN or GaN-i) or doped gallium nitride (GaN-p, GaN-n).
• An active region based on gallium-indium nitride can for example comprise gallium-aluminum nitride (AIGaN) or gallium nitride with different aluminum and indium contents (GalnAIN).
• a reference mark, preferably orthonormal, comprising the x, y, z axes is shown in the appended figures.
• thickness for a layer and height for a structure or a device.
• the thickness is taken in a direction normal to the main extension plane of the layer, and the height is taken perpendicular to the basal xy plane of the substrate.
• an active layer typically has a thickness along z
• an LED has a height according to z.
• a thickness of an axial deposit is taken along z.
• the longitudinal direction is parallel to z.
• the terms “vertical” and “lateral” are understood to mean directions taken respectively along z and perpendicular to z.
• a direction substantially normal to a plane means a direction having an angle of 90 ⁇ 10 ° with respect to the plane.
• the chemical compositions of the various elements can be determined using the well-known EDX or X-EDS method, acronym for “energy dispersive x-ray spectroscopy” which means “energy dispersive analysis of X photons”.
• This method is well suited for analyzing the composition of small size optoelectronic devices such as 3D LEDs. It can be implemented on metallurgical sections within a Scanning Electron Microscope (SEM) or on thin sections within a Transmission Electron Microscope (TEM).
• SEM Scanning Electron Microscope
• TEM Transmission Electron Microscope
• the optical properties of the various elements, and in particular the main emission wavelengths of axial 3D LEDs based on GaN and / or active layers based on InGaN can be determined by spectroscopy.
• CL Cathodoluminescence
• PL photoluminescence
• an optoelectronic device with axial 3D architecture comprises an active layer and / or InGaN-based quantum wells directly formed within a growth mask.
• a growth mask can be indicative of an implementation of a deposition of MOVPE type, as described in the present invention.
• a first embodiment of an optoelectronic device with axial 3D architecture according to the invention will now be described with reference to Figures 1A to 1E.
• the present invention also relates to a method of manufacturing an optoelectronic device as described through the exemplary embodiments below.
• FIG. 1A illustrates in cross section the formation of a growth mask 2 on a substrate 1.
• This growth mask 2 can be formed from a dielectric material, for example from silicon oxide. It typically comprises a plurality of openings 20, 20 'opening onto the substrate 1.
• Such a growth mask 2 is configured to guide the growth of the active layer and / or of the injection layers of carriers (electrons and / or holes ) within each opening 20, 20 '.
• the substrate 1 can in particular be in the form of a solid support made of sapphire or silicon. In the latter case, it can be in the form of a wafer with a diameter of 200 mm or 300 mm. This helps to reduce costs. It also improves technological compatibility with microelectronic technologies.
• the sapphire can be in the form of a wafer with a diameter of 200 mm and makes it possible to limit the lattice parameter mismatch with the GaN.
• the substrate 1 serves in particular as a support for the optoelectronic device. It can act as a mechanical support and / or an epitaxy support.
• the substrate 1 can advantageously be limited to the single solid support, without additional surface layer. It can be substantially plane and parallel to the xy plane.
• the substrate 1 can be textured and / or include patterns.
• the substrate 1 is a patterned sapphire substrate also called PSS (acronym for “Patterned Sapphire Substrate) known to those skilled in the art. These patterns can have various shapes, for example a conical, hemispherical or pyramidal shape.
• the substrate 1 can be in the form of a stack comprising, in the z direction, the support and at least one other layer, for example a buffer layer.
• This buffer layer can be based on GaN or on polySi. According to another possibility, it can be based on other metal nitrides, for example AIN.
• the substrate 1 can also comprise, alternatively or in combination with the buffer layer, a nucleation layer, typically based on GaN. Such a nucleation layer typically has a low thickness, for example less than 100 nm. This makes it possible to improve the crystalline quality of this GaN-based nucleation layer.
• the growth mask 2 is preferably formed directly on the substrate.
• Such a growth mask 2 is typically formed by a deposition step, for example a chemical vapor deposition CVD (acronym for “Chemical Vapor Deposition”), followed by a lithography / etching step configured to define the openings (figure 1A).
• the growth mask can be made of a dielectric material, for example silicon oxide or silicon nitride, or a combination of dielectric materials.
• the openings 20, 20 ’ open out to the surface of the substrate 1. They preferably have one or more walls substantially perpendicular to the xy plane of the substrate 1.
• the openings 20, 20’ have a closed contour in the xy plane. They typically have a lateral dimension taken in the xy plane, for example a diameter or an average diameter, between 50 nm and 500 nm.
• These openings 20, 20 ’ are preferably circular. As illustrated in Figure 1A, they may advantageously have different diameters a, a ".
• the pitch p1, p2 of each grating ie the distance separating the centers of two adjacent openings of the same grating, is preferably less than or equal to 1 ⁇ m.
• the pitch of a network of openings having a given diameter is equal to the sum of the diameter and the separation distance ds separating two adjacent openings of this network.
• each array of openings 20, 20 ' is chosen so as to form a resonant cavity in a direction parallel to the xy plane, for a determined emission wavelength.
• a growth mask 2 comprising openings ordered according to one or more networks therefore makes it possible to form one or more photonic crystals.
• the openings 20, 20 ’ are configured to each accommodate a stack 3 comprising at least one layer 30 for injecting carriers of a first type, for example electrons, and an active layer 31.
• the electron injection layer 30 of stack 3 is preferably based on GaN, in particular based on GaN-n. It is preferably oriented parallel to z in a crystallographic direction [0001] corresponding to the c axis of a hexagonal crystallographic structure.
• this GaN-n-based electron injection layer 30 can be done by epitaxy, preferably by vapor phase epitaxy with organometallic precursors MOVPE (acronym for "MetalOrganic Vapor Phase Epitaxy”). It is preferably done simultaneously in each opening 20, 20 ’of the growth mask 2.
• MOVPE organometallic precursors
• the electron injection layer 30 is formed on the exposed surface of the substrate 1, at the bottom of each opening 20, 20 ".
• the growth of layer 30 is constrained laterally by the wall of opening 20, 20 ".
• Layer 30 thus gradually fills the opening in question.
• the volume of each layer 30 deposited or epitaxied simultaneously within each opening 20, 20 ’ is substantially constant.
• the thickness h1, h2 of the layer 30 thus advantageously depends on the lateral dimension a, a ’of the opening 20, 20’ in question.
• the layer 30 advantageously has a thickness h1 for each opening 20 of diameter a, and a thickness h2 for each opening 20 "of diameter a". The larger the opening diameter, the less the layer thickness 30.
• the active layer 31 of the stack 3 is preferably based on InGaN. It preferably comprises a plurality of quantum wells based on InGaN. These wells quantum cells are typically configured to emit light radiation at a main wavelength h. They can be conventionally separated from each other by GaN-based barriers.
• the quantum wells based on InGaN of the active layer 31 extend parallel to the xy plane of the substrate 1, according to crystallographic planes of the c ⁇ 0001 ⁇ type.
• the stack 3 comprising such an active layer 31 advantageously has an axial architecture.
• This axial architecture makes it possible in particular to incorporate a high indium [In] concentration in the quantum wells of the active layer 31. The more the indium [In] concentration of InGaN-based quantum wells increases, the longer the wavelength. main increases.
• this active layer 31 can be done by periodic deposition of InGaN quantum wells and GaN barriers by MOVPE. It is preferably carried out simultaneously in each opening 20, 20 'of the growth mask 2 (FIG. 1D). As illustrated in FIG. 1D, the active layer 31 can be formed directly on the carrier injection layer 30, in each opening 20, 20 '. In each opening, the growth of the active layer 31 is constrained laterally by the wall of the opening 20, 20 '. The active layer 31 thus gradually fills the opening in question.
• the volume of each active layer 31 deposited or epitaxied simultaneously within each opening 20, 20 ' is substantially constant.
• the thickness e1, e2 of the active layer 31 thus advantageously depends on the lateral dimension a, a 'of the opening 20, 20' considered.
• the incorporation of indium also advantageously depends on the lateral dimension a, a 'of the opening 20, 20' considered.
• the active layer 31 advantageously has a thickness e1 for each opening 20 of diameter a, and a thickness e2 for each opening 20 'of diameter a'.
• the larger the opening diameter the less the thickness of the active layer 31 is.
• the larger the opening diameter the lower the indium concentration [In] in the wells of the active layer 31. This means that the main wavelength emitted by the stacks 3 formed within the apertures of larger size is smaller than the main wavelength emitted by the stacks 3 formed within the apertures of smaller size.
• the openings 20 of diameter a can be configured so that the stacks 3 formed in said openings 20 have a main emission wavelength of the order of 525 nm, in the green, and the openings 20 'of diameter a' can be configured so that the stacks 3 formed in said openings 20 ′ exhibit a main emission wavelength of the order of 450 nm, in the blue.
• the method thus advantageously makes it possible to simultaneously form several stacks 3 emitting at several main wavelengths, in particular as a function of the size characteristics of the openings of the growth mask 2.
• the stacks 3 typically comprise, in addition to the electron injection layer 30 and the active layer 31, a hole injection layer 33, for example based on GaN-p. They can also include an electron blocking layer 32 interposed between the active layer 31 and the hole injection layer 33, in a known manner (Figure 1D). These layers 32, 33 can be completely confined in the openings 20, 20 ’, as shown in Figure 1D. According to one possibility, the hole injection layer 33 may extend at least partially outside the corresponding opening. Stack 3 of layers 30, 31, 32, 33 typically forms an axial 3D LED. Stack 3 may optionally include other layers not shown, for example layers forming distributed Bragg mirrors. In the example illustrated in Figure 1D, the stack 3 advantageously has a thickness b1 for each opening 20 of diameter a, and a thickness b2 for each opening 20 ′ of diameter a ’.
• Such a contact can then be formed on the layers 33 of hole injections.
• a contact may be in the form of a conductive layer 40, for example made of metal or of transparent conductive oxide (TCO), as illustrated in FIG. 1 E.
• TCO transparent conductive oxide
• the device thus formed advantageously comprises axial 3D LEDs passivated by the growth mask 2.
• the growth mask 2 also makes it possible to laterally encapsulate the stacks 3.
• the mechanical strength of the device is thus ensured.
• the stacks are advantageously distributed, according to the size of the openings in which they are formed, into sub-assemblies emitting at different main wavelengths. This makes it possible in particular to form sub-pixels of different colors, typically red, green and blue (RGB). These subpixels can be organized into photonic arrays, as shown in Figure 1B, to improve the intensity of light emission. According to another possibility, they can be arranged alternately from one another, typically to form a pixel from three RGB sub-pixels.
• the method of manufacturing this device advantageously makes it possible to obtain stacks of different sizes, emitting at different wavelengths, during a single growth sequence of each of the layers of the stacks. It also makes it possible to implement 2D type growth conditions to produce 3D stacks. This allows the formation of active layers comprising quantum wells according to crystallographic planes of type c ⁇ 0001 ⁇ , in a 3D stack epitaxied by MOVPE. The method thus makes it possible to manufacture an optoelectronic device, in particular based on LEDs, combining the advantages of 2D growth conditions and the advantages of 3D stack architectures.
• the choice of the diameter of the openings and of the separation distance between the openings also makes it possible to control the thickness of the active layers and the incorporation of indium within the active layers of these openings, so as to ultimately adjust the length. of the main emission wave of the stacks.
• FIGS. 2A to 2F A second exemplary embodiment is illustrated in FIGS. 2A to 2F.
• This second example presents an alternative embodiment of the growth mask 2.
• the substrate 1 is surmounted by a layer 1 ′, for example made of GaN (FIG. 2A).
• This GaN layer 1 ’ is then structured and passivated to form the growth mask 2.
• a hard mask 2 ’ is previously formed by surface lithography of GaN layer 1’ ( Figure 2B).
• This 2 ′ hard mask can conventionally be made of silicon oxide (Si02) or silicon nitride (SiN). It comprises openings 21, 21 'of the same shape as the openings 20, 20' to be produced in the growth mask 2. These openings 21, 21 'have lateral dimensions slightly greater than the dimensions of the openings 20, 20' to be produced in growth mask 2.
• Anisotropic etching of layer 1 ’, along z and over the entire thickness of layer 1’, is then carried out (Figure 2C).
• This etching can be done in a known manner by plasma in chlorinated chemistry, for example from a CI2 / Ar or SiCl4 / Ar mixture.
• Passivation of the exposed walls of layer 1 ’ is then performed, typically by depositing a dielectric layer 2 ′′ of SiO 2 or SiN ( Figure 2D).
• This 2 ”layer is continuous and preferably conformal. It is preferably based on the same dielectric material as the 2 ’hard mask.
• Etching of the dielectric material is then performed so as to expose the surface of the substrate 1 while maintaining a thickness of dielectric material on the surfaces of the GaN layer 1 '.
• the growth mask 2 and the openings 20, 20 'of the growth mask 2 are thus formed.
• This etching can be isotropic if the deposition of layer 2 ”conforms, or anisotropic along z if the deposition of layer 2” is non-compliant. These options can be chosen so as to obtain a substantially constant dielectric material thickness on the surfaces of the GaN layer 1 ′.
• FIG. 3A shows a transmission electron microscopy (TEM) image of a stack 3 formed within an opening of a growth mask 2 according to the principle of the method described in this invention.
• the growth mask 2 used for this proof of concept illustrated in FIG. 3A comprises as a variant a layer 2a of great thickness in SiN and a layer 2b of small thickness in SiO 2. It has a height of around 1 ⁇ m.
• the substrate 1 used for this proof of concept comprises as a variant a nucleation layer 1a and a support layer 1b.
• the GaN-n electron injection layer 30, the active layer 31 and the GaN-p hole injection layer 33 were successively epitaxied within the opening 20 of the growth mask 2.
• the wells MQW quantums of active layer 31 extend substantially parallel to the xy plane of the surface of substrate 1. This appears even more clearly in Figure 3B showing a transmission scanning electron microscopy (STEM) image of this type. 'stack 3.
• the stack 3 of the different layers 30, 31, 33 therefore forms an axial architecture.
• the cavity 200 extending at the base of the opening 20 is here due to an overetching during the making of the opening 20 (FIG. 3A).
• This cavity 200 here houses a foot 300 of growth of the GaN-n layer 30.
• the cavity 200 and growth foot 300 illustrated in this proof of concept in Figure 3A are optional only.
• the growth of the various layers by MOVPE directly within the opening 20 does not induce structural defects in the various layers 30, 31, 33 at the level of the interface with the growth mask 2 (FIG. 3A).
• the growth mask 2 thus advantageously makes it possible to guide the growth of the stack without generating defects. It also makes it possible to passivate directly the vertical sides, ie substantially parallel to z, of the stack 3.
• FIGS. 4A to 4G A third example of a “flip chip” type production method is illustrated in FIGS. 4A to 4G.
• the device comprises a plurality of stacks 3 distributed within the growth mask 2 into different subsets SP1, SP2, SP3, SP1 ′ (FIG. 4A).
• subsets SP1, SP2, SP3, SP1 'of stacks 3 are advantageously formed within openings of the growth mask 2 having different diameters, so as to form subpixels emitting at different wavelengths, typically in red, green and blue.
• the various sub-assemblies SP1, SP2, SP3, SP1 ′ are formed as above on a first substrate 1, through the openings, then covered by a metal layer 40 (FIG. 4A).
• This metallic layer 40 is typically in contact with the GaN-p layers of the stacks 3.
• the metallic layer 40 is then structured so as to form distinct contacts on different sub-pixels taken from the subsets SP1, SP2, SP3, SP1. '( Figure 4B).
• a layer 50 of silicon oxide is then deposited, for example by plasma-assisted chemical vapor deposition (PECVD), on the front face of the first substrate 1 so as to cover the structures previously formed (FIG. 4C).
• PECVD plasma-assisted chemical vapor deposition
• This SiO 2 layer 50 makes it possible to assemble, for example by molecular bonding, a second substrate 11 on the front face of the first substrate 1 comprising the structures of the device (FIG. 4D).
• the second substrate 11 is typically made of silicon.
• the first substrate 1 is then removed, for example by trimming and polishing from its rear face, so as to expose the base of the stacks 3 and of the growth mask 2 (FIG. 4E).
• a layer 60 of transparent conductive oxide (TCO) can then be deposited “on the rear face”, on the basis of the stacks 3 and of the growth mask 2 (FIG. 4F).
• This TCO layer 60 is typically in contact with the GaN-n layers of the stacks 3.
• a passivation layer 70 for example made of silicon oxy-nitride SiON, can then be deposited on the rear face.
• the n-type contacts 61 on the TCO layer 60 and the p-type contacts 41 on the metallic layer 40 are then respectively structured, for example in the form of vias (FIG. 4G).
• flip chip Such a method making it possible to turn over the chip supporting the optoelectronic device is generally known under the name “flip chip”. It makes it possible to manufacture a device emitting from the rear face.
• the metallic layer 40 can typically act as a reflector in such a device.
• the method according to the invention advantageously makes it possible to produce different RGB sub-pixels based on 3D architectures, according to one and the same sequence. growth, with growth conditions similar to two-dimensional growth methods.

Applications Claiming Priority (2)

Publications (1)

Family

ID=72644465

Family Applications (1)

Country Status (4)

Families Citing this family (1)

Family Cites Families (7)

• 2020
  • 2020-06-30 FR FR2006904A patent/FR3112026B1/fr active Active
• 2021
  • 2021-06-29 US US18/004,002 patent/US20230268460A1/en active Pending
  • 2021-06-29 EP EP21736610.3A patent/EP4173045A1/de active Pending
  • 2021-06-29 WO PCT/EP2021/067780 patent/WO2022002896A1/fr unknown

Also Published As

Similar Documents

Legal Events