EP4158630A1 - Additionneur fondé sur un memristor et procédé de fonctionnement correspondant - Google Patents

Additionneur fondé sur un memristor et procédé de fonctionnement correspondant

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Publication number
EP4158630A1
EP4158630A1 EP21729858.7A EP21729858A EP4158630A1 EP 4158630 A1 EP4158630 A1 EP 4158630A1 EP 21729858 A EP21729858 A EP 21729858A EP 4158630 A1 EP4158630 A1 EP 4158630A1
Authority
EP
European Patent Office
Prior art keywords
read
operations
write
switchable
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21729858.7A
Other languages
German (de)
English (en)
Inventor
Nan DU
Heidemarie Schmidt
Bo ZHAI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP4158630A1 publication Critical patent/EP4158630A1/fr
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Definitions

  • the application relates to an apparatus and a method for implementing one or more logical operations and, in particular, a memristor-based full adder and method for their operation. Specifically, the application relates to an (N + M) -bit full adder with memristors and the operation of the (N + M) -bit full adder.
  • the amount of data and the speed with which new data is generated is increasing daily, also due to new mobile devices and the large number of sensors connected to the Internet (see [1]).
  • Logic operation steps can be carried out using memristors.
  • memristors can also be used to store intermediate results.
  • Lehtonen et al. (see [7]) have shown an adder concept in which the addition can be carried out using memristors by a series of sequential calculations while emulating logic arithmetic operations.
  • the scheme of an N-bit full adder presented in [7] requires 3N + 5 individual memristors and 88N + 48 cycles.
  • Kvatinsky et al. have introduced two improved designs of an N-bit full adder using a specific modification of the crossbar array structure, namely a parallel and a serial N-bit full adder.
  • the parallel adder requires 9 N single memristors and 5 N + 18 cycles and the series adder 3 N + 3 single memristors and 29 N cycles.
  • the sum operation requires in its approach one more write cycle than the carry operation, and the output of the carry operation must be read out and serves as an input variable for the second write cycle of the sum operation, requiring more steps to execute.
  • the read bias is the same as initialization and by observing spikes in current below the read bias to see the value of the output.
  • the information read out must be written back into the cell in the TC adding scheme. This requires a large number of calculation steps.
  • IMC In-Memory Computing
  • Memristors with low power consumption offer the possibility of IMC and stateful logic technology to develop that aims at in-memory computing solutions.
  • IMC logic families include the Memristor logic for Material Implication (IMPLY) (see [17]) and the Memristor Aided Logic (MAGIC) (see [18]).
  • IMPLY Memristor logic for Material Implication
  • MAGIC Memristor Aided Logic
  • memristive IMPLY logic The main disadvantage of memristive IMPLY logic is the need to perform long sequences of stateful logic operations to synthesize a given Boolean function.
  • the practicality of the memristive IMPLY logic design scheme therefore requires that operations be as parallel as possible to compensate for the latency problem.
  • the logic operation is determined by the topology of the logic circuit. If these are to be controlled separately by the input and output electrodes, the input and output electrodes must first be initialized to the specific resistance state. Regular logical operations, in which the initialization operations have to be carried out for each input and output electrode, result in great latency, a large area size and high power consumption.
  • the object of the invention is to provide improved concepts for implementing one or more logical operations.
  • the object is achieved by a device according to claim 1, by a method according to claim 15 and by a computer program according to claim 16.
  • Each of the one or more logical operations has one or more binary input variables and, depending on the implemented logical operation and depending on the one or more binary input variables, has a binary output value.
  • the device comprises one or more switchable elements.
  • the device is designed to carry out write operations and read operations.
  • the device is designed, each of the Carry out write operations in such a way that a switchable element of the one or more switchable elements is applied with a write bias voltage that switches the switchable element into a first state depending on the write bias voltage or into a second state that changes from the first state is different.
  • the device is designed to carry out each of the read operations in such a way that a read bias voltage is applied to a switchable element of the one or more switchable elements in order to determine whether the switchable element is switched to a first state or to the second state is.
  • the device is designed to select the write bias of at least one of the write operations as a function of these binary input variables for each binary input variable of the one or more binary input variables of each of the one or more binary operations.
  • the device is designed to determine the binary output value of each of the one or more logical operations by applying the reading voltage of one of the reading operations as a function of the state in which the switchable element of the one or more switchable elements is connected to which the reading voltage is connected is created.
  • a method for implementing one or more logical operations is provided.
  • Each of the one or more logical operations has one or more binary input variables and, depending on the implemented logical operation and depending on the one or more binary input variables, has a binary output.
  • the method includes performing write operations and read operations.
  • Each of the write operations is carried out in such a way that a switchable element of one or more switchable elements is applied with a write bias voltage, which switches the switchable element into a first state depending on the write bias voltage or switches it to a second state that starts from is different from the first state.
  • Each of the read operations is carried out in such a way that a read bias voltage is applied to a switchable element of the one or more switchable elements in order to determine whether the switchable element is switched to a first state or is switched to the second state.
  • the write bias of at least one of the write operations is selected as a function of this binary input variable.
  • the binary output value of each of the one or more logical operations becomes one of the read operations by applying the read voltage determined depending on the state in which the switchable element of the one or more switchable elements is switched, to which the read voltage is applied.
  • the number of individual memristors and the number of cycles are reduced for (N + M) -bit full adders based on memristors.
  • Concepts according to the invention for (N + M) -bit full adders are provided.
  • FIG. 1 shows an apparatus for implementing one or more logical
  • Fig. 2 shows an exemplary structure of a memristor with a BFO
  • FIG. 3 shows a current-voltage characteristic for the exemplary memristor of FIG. 2 according to an embodiment.
  • FIG. 4 shows the resistances that can be used for the exemplary memristor of FIG. 2 according to one embodiment.
  • Fig. 5 shows the truth table of a full adder according to a
  • Embodiment comprising carry and sum operations.
  • FIG. 6 shows a simplified schematic circuit for a 1-bit full adder using three memristors according to an embodiment.
  • Fig. 7 shows calculation cycles of a 1-bit full adder according to a
  • FIG. 8 shows a structure of a 1-bit full adder according to an embodiment.
  • Fig. 9 shows a cycle flow diagram of an (N + N) -bit full adder.
  • FIG. 10 shows a comparison of the required number of memristors of an embodiment with respect to the required number of memristors in logic computing with individual memristors.
  • Each of the one or more logical operations has one or more binary input variables and, depending on the implemented logical operation and depending on the one or more binary input variables, has a binary output value.
  • the device comprises one or more switchable elements 111, 112.
  • the device is designed to carry out write operations and read operations.
  • the device is designed to carry out each of the write operations in such a way that a switchable element of the one or more switchable elements 111, 112 a write bias voltage is applied which switches the switchable element into a first state as a function of the write bias voltage or else switches it into a second state which is different from the first state.
  • the device is designed to carry out each of the read operations in such a way that a read bias voltage is applied to a switchable element of the one or more switchable elements 111, 112 in order to determine whether the switchable element is switched to a first state or to the second state is switched.
  • the device is designed to select the write bias of at least one of the write operations as a function of these binary input variables for each binary input variable of the one or more binary input variables of each of the one or more binary operations.
  • the device is designed to determine the binary output value of each of the one or more logical operations by applying the read voltage of one of the read operations as a function of the state in which the switchable element of the one or more switchable elements 111, 112 is switched that the reading voltage is applied.
  • the device can be designed, for example, to switch either a switchable element of the one or more switchable elements 111, 112 to the first state during one of the write operations by applying the write bias voltage with a first write voltage value to the switchable element or to switch the switchable element to the second state by applying the write bias voltage to the switchable element with a second write voltage value that is different from the first voltage value.
  • the device can be designed, for example, to apply the read bias voltage to a switchable element of the one or more switchable elements 111, 112 with a first read voltage value or with a second read voltage value that is determined by the first read voltage value is different, and wherein the device is designed to determine, depending on the read bias voltage and a resistance value of the switchable element, whether the switchable element is switched into the first state or into the second state.
  • the device can be designed, for example, to determine that the switchable element has been switched to the first state, for example, if the resistance value is in a first value range and the read bias voltage was applied with the first read voltage value, or if the Resistance value lies in a second range of values, the second range of values and the first range of values do not overlap, and the read bias voltage was applied with the second read voltage value, and to determine that the switchable element was switched to the second state, for example, when the Resistance value lies in the first value range and the read bias voltage was applied with the second read voltage value, or if the resistance value is in a second value range and the read bias voltage was applied with the first read voltage value.
  • each of the one or more switchable elements 111, 112 can be, for example, a memristor.
  • each of the one or more switchable elements 111, 112 may comprise yttrium-manganese oxide, for example.
  • each of the one or more switchable elements 111, 112 may comprise bismuth ferrite and / or titanium doped bismuth ferrite.
  • the device can further include, for example, one or more multiplexers, each of the one or more multiplexers being formed, either the write bias voltage of one of the write operations or the read bias voltage of one of the read operations on one of the one or more switchable elements 111, 112 to be applied.
  • the device can have, for example, two or more switchable elements as the one or more switchable elements 111, 112.
  • the device can have, for example, exactly three switchable elements as the two or more switchable elements.
  • At least one of the one or more logical operations may include, for example, two or more binary input variables as the one or more binary input variables.
  • the device can be configured, for example, in at least one of the write operations, the write bias voltage depending on the state in which one of the one or more switchable elements 111, 112 is switched and which was determined by the device in a previous read operation , to choose.
  • the apparatus can be designed to implement two or more logical operations.
  • the apparatus can implement a full adder by having a first of the two or more logical operations implementing a sum operation and by a second of the two or more logical operations implementing a carry operation.
  • BFO bismuth ferrite: BiFeO 3
  • BFTO bismuth ferrite doped with titanium: Bi (Fe :, Ti) O 3
  • electrical measurement configuration a schematic representation of the BFTO / BFO double-layer structure (BFO stands for bismuth ferrite: BiFeO 3 ; BFTO stands for bismuth ferrite doped with titanium: Bi (Fe :, Ti) O 3 ) and the electrical measurement configuration .
  • FIG. 3 shows a current-voltage characteristic for the BFTO / BFO double-layer memristor of FIG. 2 with an approximately 600 nm thick BFO thin film and a contact area of 0.045 mm 2 .
  • Fig. 4 shows realizations of resistance states and the polarities of the applied write and read bias.
  • FIG. 2 shows an exemplary embodiment for the single memristors of an (N + N) full adder with a BFO double-layer structure
  • an exemplary IV characteristic for this is shown in FIG. 3
  • exemplary, usable resistances of the single memristor are shown in FIG. 4 shown.
  • the single memristor of FIG. 2 has at least two resistance states, for example a low-resistance state (LRS) and a high-resistance state (HRS).
  • the resistance states can be set and reset by positive write bias (5 V) and negative write bias (-5 V).
  • positive write bias the LRS and the HRS are read out by a positive read bias and a negative read bias, which are abbreviated as PLRS (positive low-resistance state) and NHRS (negative high-resistance state).
  • LRS and HRS are read out by a negative read bias and a positive read bias, which are abbreviated as NLRS (negative low-resistance state) and PHRS (positive high-resistance state).
  • full adder logic with BFTO complementary switches is provided using only a single write and read cycle.
  • the actual polarity and amplitude of the applied write bias voltage are determined by the potential of the upper electrode (T1) and the lower electrode (T2) of the resistance switch.
  • the top electrode (T1) can be viewed as a reference for the bias voltage applied to the device. This can for example be provided in an adder according to one embodiment.
  • the potential of the upper electrode is higher than that of the lower electrode, it can be considered a positive voltage applied to the device. Otherwise, if the potential of the lower electrode has a higher potential, it can be considered a negative voltage applied to the device.
  • the resistance state of the device is either a (PLRS, NHRS) state or a (PHRS, NLRS) state, which can be assigned "1" or "0".
  • the resistance state "1" or "0” can be switched only by negative write bias and positive write bias according to the reverse logic "0" or "1". Therefore, for example, the result of the write cycle can be defined by T1, T2 and the initial state, which can be viewed as address ports of input variables in write cycles.
  • a positive write bias is applied in a cycle (PLRS, NHRS)
  • this is interpreted as a first bit value (e.g. as "1")
  • a negative write bias is applied in the cycle (PHRS, NLRS)
  • this is interpreted as a second bit value (eg as "0"), which is different from the first bit value.
  • the read bias is assigned "1" or "0" according to the positive read bias or the negative read bias
  • write cycles are shown in the C.W columns
  • read cycles are shown in the C.R columns.
  • a full adder logic operation consists of a carry operation and a sum operation.
  • 5 shows the truth tables of the carry and sum operations in the (N + N) full adder on the basis of electroforming-free CRS (Complementary Resistive Switch) memistors with a non-destructive readout.
  • the input variable c is programmed into the device as the output state before the write cycle.
  • the carry bit Ci + i is calculated and saved in the device as a resistance state.
  • the input variables pi and c are programmed in T1 and T2 for total operation.
  • the intermediate state s i ' is stored in the device.
  • the output of the logic operation with BFO devices can be defined by another variable, namely read bias.
  • read bias when the polarities of the write and read bias are the same, the BFTO device will show a low resistance (PLRS or NLRS) as an output, otherwise it will show a high resistance (PHRS, NHRS) as an output.
  • the read bias to the upper electrode is always positive (+ 2.5 V) to read q + i.
  • To implement positive biasing on T1 we can provide negative bias (-2.5V) to T2, so the read bias can only be implemented through the bottom electrode.
  • the read bias is used as an input variable considered, where the positive bias and the negative bias correspond to logic "1" and "0", respectively;
  • the read bias is regarded as the input variable qi.
  • This conditional read bias can be implemented by two simple multiplexers in the circuit design. Similar to the transfer process, the read bias can also be implemented by applying a bias with reversed polarity to the bottom electrode. Therefore, the bias "q i " is applied to T2 while C i is "0", the bias is applied to T2 while q is "1".
  • the read bias for all logic operations can be applied to the bottom electrode, and the amplitude of the read bias is half the write bias. Then the read cycles and write cycles can be implemented in just one step with our scheme, and these are reconfigurable and separable cycles.
  • the structure of an (N + N) -bit full adder is provided.
  • FIG. 6 describes the simplified scheme for a 1-bit full adder.
  • FIG. 6 shows a simplified schematic circuit for a 1-bit full adder using three memristors Mo, Mi and M2.
  • the hollow square represents the write bias that can be applied to both the top electrode and the bottom electrode.
  • the dot represents the read bias applied to the lower electrode only.
  • the lower electrode potential is the sum of the applied read and write biases for T2.
  • the actually applied potentials of T 1 and T2 are determined by the logic value, where 2.5 V and -2.5 V correspond to logic "1" and "0".
  • the write bias can be applied to both the upper and lower electrodes, and the read bias can only be applied to the lower electrode. Therefore, the actual bias of T2 is equal to the sum of the applied write and read bias of T2.
  • a 1-bit full adder is implemented by three devices with this scheme. In particular, MO is used to determine the read bias logic for the sum operation. M1 and M2 are used to compute S 0 'and C 1 .
  • the 1-bit full adder can be viewed as the initialization step for the n-bit full adder, and the following (n-1) bits in the adder mode can all be implemented with a single write and a single read step.
  • FIG. 7 describes the calculation steps in detail.
  • FIG. 7 shows calculation cycles of a 1-bit full adder for each of the three memristors of FIG. 6.
  • the backgrounds of the fields in FIG. 7 are as chosen in FIG. 6.
  • the write distortion and the read distortion are shown.
  • s represents the initial resistance state of the memristors for each cycle.
  • T1 and T2 are the given logic for the top electrodes and the bottom electrodes in each cycle.
  • the bias is the overlay bias for the top electrode in each cycle.
  • the first cycle is an initialization cycle. Before all logical links, it is assumed that all devices are in an unknown state. To initialize all devices, logic signals "1" and "0" are addressed to word line WO and to all bit lines B 0 , B 1 and B 2 , which can be viewed as applying positive write bias to all devices. Then all devices are initialized to a known state "1".
  • the second cycle can also be viewed as an initialization cycle.
  • the first carry bit Co is programmed into all devices by applying a bias voltage of "c 0 " (-2.5 V) to WO and a bias voltage of "1" (2.5 V) to all bit lines. Under this bias voltage (the actual bias voltage is -5 V), Co is programmed as the initial state "0" in all devices.
  • s 0 'and Ci are calculated with Mi and M2 by setting Wo to p 0 (2.5 V), while B 1 to C 0 (-2.5 V) and B 2
  • cO is read out by setting B 0 to p 0 + "0" (2.5 V - 2.5 V).
  • the read bias voltage of Sc ' is increased by reading defined by Co.
  • the read bias is set by qo, where C 0 is "0".
  • Ci is calculated with Mo by setting Wo to p 0 (2.5 V) and B 0 to% (- 2.5 V). Meanwhile, s0 'and c1 are read out by setting Bi to p 0 + q 0 (2.5 V + 2.5 V) and B 2 to p 0 +' 0 '(2.5 V - 2.5 V) . During these four cycles, the calculation results S 0 and C 1 for the
  • FIG. 8 shows a structure of a 1-bit full adder according to an embodiment.
  • the hollow square represents the write bias and the point represents the read bias, which are selected as in FIG.
  • the columnar rectangular area is the current answer for each cycle, specifically the currents of the BFO devices in each cycle, which can get the results from reading the cycles.
  • a sense amplifier and a comparator can be viewed as analog-to-digital converters, which can convert the analog current as an output to the logical value "0" or "1". The circuit is not given in detail in this article.
  • the write cycle and the read cycle always exist simultaneously in every calculation step.
  • the component MO which is connected in the large bar array by WO and BO, plays a special role in the circuit.
  • the Q is read from Mo while the other cells are used to compute s i 'and c i +1.
  • the read bias for si ' is given by the read out c i determined.
  • the determined read bias is addressed back to the circuit and then serves as a logical variable for reading out s ,.
  • M 0 implements the computation of c i +1, which prepares to define the read bias for s i +1.
  • the read cycle and the write cycle are performed alternately with Mo. Depending on the bit length of the full adder operands, the total number of steps can be calculated as follows: 2N + 2, which can be seen from FIG.
  • CRS Complementary Resistive Switch
  • a structure of an (N + M) -bit full adder with electroforming-free CRS (Complementary Resistive Switch) memistors with a non-destructive readout is provided.
  • operation of an (N + M) -bit full adder with electroforming-free CRS memristors with non-destructive readout is provided.
  • a structure and operation of a crossbar array for the serial and for the parallel operation of (N + M) -bit full adders is provided.
  • aspects have been described in connection with a device, it goes without saying that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously to this, aspects that have been described in connection with or as a method step also represent a description of a corresponding block or details or features of a corresponding device.
  • Some or all of the method steps can be carried out by a hardware apparatus (or using a hardware Apparatus), such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some or more of the most important process steps can be performed by such an apparatus.
  • exemplary embodiments of the invention can be implemented in hardware or in software or at least partially in hardware or at least partially in software.
  • the implementation can be carried out using a digital storage medium, for example a floppy disk, a DVD, a BluRay disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or some other magnetic or optical memory Memory are carried out on the electronically readable control signals are stored, which can interact with a programmable computer system or cooperate in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer readable.
  • Some exemplary embodiments according to the invention thus comprise a data carrier which has electronically readable control signals which are able to interact with a programmable computer system in such a way that one of the methods described herein is carried out.
  • exemplary embodiments of the present invention can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.
  • the program code can, for example, also be stored on a machine-readable carrier.
  • exemplary embodiments include the computer program for performing one of the methods described herein, the computer program being stored on a machine-readable carrier.
  • an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer.
  • a further exemplary embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) which the computer program for performing one of the methods described herein is recorded.
  • the data carrier or the digital storage medium or the computer-readable medium are typically tangible and / or non-transitory.
  • a further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein.
  • the data stream or the sequence of signals can, for example, be configured to be transferred via a data communication connection, for example via the Internet.
  • Another exemplary embodiment comprises a processing device, for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • a processing device for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • Another exemplary embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.
  • a further exemplary embodiment according to the invention comprises a device or a system which is designed to transmit a computer program for carrying out at least one of the methods described herein to a receiver.
  • the transmission can take place electronically or optically, for example.
  • the receiver can be, for example, a computer, a mobile device, a storage device or a similar device.
  • the device or the system can, for example, comprise a file server for transmitting the computer program to the recipient.
  • a programmable logic component for example a field-programmable gate array, an FPGA
  • a field-programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein.
  • the methods are performed by any hardware device. This can be universally applicable hardware such as a computer processor (CPU) or hardware specific to the method, such as an ASIC.
  • CPU computer processor
  • ASIC application specific integrated circuit

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Abstract

Dans un mode de réalisation, l'invention concerne un dispositif permettant de mettre en oeuvre une ou plusieurs opérations logiques. Chaque opération logique parmi cette ou ces opérations logique présente une ou plusieurs variables d'entrée binaires et une valeur de sortie binaire en fonction de l'opération logique mise en oeuvre et en fonction de la ou des variables d'entrée binaires. Le dispositif comprend un ou plusieurs éléments commutables (111, 112). Le dispositif est conçu pour exécuter des opérations d'écriture et des opérations de lecture. À cet effet, le dispositif est conçu pour exécuter chaque opération d'écriture de manière qu'une prétension d'écriture soit appliquée à un élément commutable parmi l'élément ou les éléments commutables (111, 112), qui, en en fonction de la prétension d'écriture, commute l'élément commutable vers un premier état ou vers un deuxième état différent du premier état. De plus, le dispositif est conçu pour exécuter chacune des opérations de lecture de manière qu'une prétension de lecture soit appliquée à un élément commutable parmi l'élément ou les éléments commutables (111, 112) pour déterminer si l'élément commutable est commuté vers un premier état ou vers un deuxième état. Le dispositif est conçu pour sélectionner pour chaque variable d'entrée binaire parmi la ou les variables d'entrée binaire de chaque opération binaire parmi l'opération ou les opérations binaires, la prétension d'écriture d'au moins une des opérations d'écriture en fonction de ces variables d'entrée binaires. En outre, le dispositif est conçu pour déterminer la valeur de sortie binaire de chaque opération logique parmi l'opération ou les opérations binaires, par application de la tension de lecture d'une des opérations de lecture en fonction de l'état vers lequel est commuté l'élément commutable parmi l'élément ou les éléments commutables (111, 112) auquel est appliquée la tension de lecture.
EP21729858.7A 2020-05-29 2021-05-27 Additionneur fondé sur un memristor et procédé de fonctionnement correspondant Pending EP4158630A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020206796.1A DE102020206796A1 (de) 2020-05-29 2020-05-29 Memristor-basierte Volladdierer und Verfahren zu deren Betrieb
PCT/EP2021/064270 WO2021239911A1 (fr) 2020-05-29 2021-05-27 Additionneur fondé sur un memristor et procédé de fonctionnement correspondant

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