EP3982412A1 - Boîtier de capteur d'image et son procédé de fabrication - Google Patents

Boîtier de capteur d'image et son procédé de fabrication Download PDF

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Publication number
EP3982412A1
EP3982412A1 EP21180265.7A EP21180265A EP3982412A1 EP 3982412 A1 EP3982412 A1 EP 3982412A1 EP 21180265 A EP21180265 A EP 21180265A EP 3982412 A1 EP3982412 A1 EP 3982412A1
Authority
EP
European Patent Office
Prior art keywords
image sensor
package
dam
chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP21180265.7A
Other languages
German (de)
English (en)
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EP3982412B1 (fr
Inventor
BongJin SON
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of EP3982412A1 publication Critical patent/EP3982412A1/fr
Application granted granted Critical
Publication of EP3982412B1 publication Critical patent/EP3982412B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L27/14636—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L27/14618—
    • H01L27/1462—
    • H01L27/14683—
    • H01L31/02005—
    • H01L31/0203—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Definitions

  • the disclosure generally relates to an image sensor.
  • the present invention generally relates image sensor packages and/or a method of fabricating an image sensor package.
  • An image sensor package which is a core component mounted in some devices such as a camera device, has been used in a wide variety of fields, such as portable terminals, such as mobile phones and/or tablets, beyond the scope of typical cameras.
  • the image sensor package may have various package structures, such as a chip-on board (COB) package, a chip-on flexible (COF) printed circuit board (PCB) package, a chip-on glass (COG) package, a wafer-level chip-scale package (WLCSP) package, an image sensor ball grid array (IBGA) package, and a plastic leadless chip carrier (PLCC) package.
  • COB chip-on board
  • COF chip-on flexible
  • COG chip-on glass
  • WLCSP wafer-level chip-scale package
  • IBGA image sensor ball grid array
  • PLCC plastic leadless chip carrier
  • the fabrication of an IBGA image sensor package which is widely applied to vehicles such as autonomous vehicles, may include mounting an image sensor on a substrate and adhering a transparent member (
  • Claims 1 and 10 each define an image sensor package.
  • Claim 14 defines a method of fabricating an image sensor package. Preferred embodiments are defined in the dependent claims.
  • Some embodiments provide an image sensor package having improved reliability and/or a method of fabricating the image sensor package.
  • an image sensor package including a package substrate, an image sensor chip mounted on the package substrate, a transparent cover on the image sensor chip, an encapsulant encapsulating the image sensor chip and covering a side surface of the transparent cover, a dam on an upper surface of the image sensor chip and alongan outer portion of the upper surface of the image sensor, the transparent cover on the dam, a bonding wire electrically connecting a chip pad of the image sensor chip to a substrate pad of the package substrate, the dam covering a first end of the bonding wire connected to the chip pad, and a stress reducing layer covering a second end of the bonding wire connected to the substrate pad, the stress reducing layer including substantially the same material as the dam.
  • an image sensor package including a package substrate having an upper surface on which a substrate pad is located and having a lower surface on which an external connection terminal is located, an image sensor chip on the package substrate, the image sensor chip comprising a sensor circuitry in an upper central portion of the image sensor chip, a dam on an upper surface of the image sensor chip, the dam along an outer portion of the upper surface of the image sensor chip, the dam covering a chip pad of the image sensor chip, a transparent cover on the dam and apart from the upper surface of the image sensor chip, a bonding wire configured to electrically connect the chip pad to the substrate pad, a stress reducing layer on the package substrate, the stress reducing layer covering the substrate pad, and an encapsulant on the package substrate, the encapsulant encapsulating the image sensor chip and covering a side surface of the transparent cover.
  • a material of the stress reducing layer is substantially the same as a material of the dam, and the dam covers a first end of the bonding wire which is connected to the chip pad, the stress reducing layer covers a second end of the bonding wire which is connected to the substrate pad, and the encapsulant covers a middle portion of the bonding wire between the first end and the second end.
  • a method of fabricating an image sensor package includes preparing a package substrate, mounting an image sensor chip on the package substrate, connecting a chip pad of the image sensor chip to a substrate pad of the package substrate by using a bonding wire, forming a dam on an upper surface of the image sensor chip, the dam along an outer portion of the upper surface of the image sensor chip and covering a first end of the bonding wire connected to the chip pad, forming a stress reducing layer on the package substrate, the stress reducing layer covering a second end of the bonding wire connected to the substrate pad, adhering a transparent cover to the dam to be apart from the upper surface of the image sensor chip, forming an encapsulant on the package substrate, the encapsulant encapsulating the image sensor chip and cover a side surface of the transparent cover, and forming an external connection terminal on a lower surface of the package substrate.
  • a material of the stress reducing layer is substantially the same as a material of the dam.
  • FIGS. 1A and 1B are respectively a cross-sectional view and a plan view of an image sensor package 100 according to some example embodiments.
  • the image sensor package 100 may include a package substrate 110, an image sensor chip 120, bonding wires 130, a transparent cover 140, an encapsulant 150, a dam 160, and/or a stress reducing layer 170.
  • the package substrate 110 may include a body layer 111, upper substrate pads 113, lower substrate pads 115, and/or upper and lower protective layers 117u and 117d.
  • the body layer 111 may include various materials.
  • the body layer 111 may include at least one of silicon, ceramic, an organic material, glass, or an epoxy resin according to a kind of the package substrate 110.
  • the package substrate 110 may include a printed circuit board (PCB), which is based on an epoxy resin.
  • PCB printed circuit board
  • Single-layered or multilayered wirings may be formed in the body layer 111.
  • the upper substrate pads 113 may be electrically connected to the lower substrate pads 115 through the wirings of the body layer 111.
  • the package substrate 110 may have a long rectangular shape extending in one direction.
  • the package substrate 110 may have a long rectangular shape, e.g. a line shape, in a first direction (x direction), and/or the upper substrate pads 113 may be arranged on both sides of the package substrate 110 in the first direction (x direction).
  • the package substrate 110 may have a square shape; however, a shape of the package substrate 110 is not limited thereto.
  • the package substrate 110 may have a first length L1 in a lengthwise direction, for example, the first direction (x direction).
  • the first length L1 may be, for example, about 8.0 mm or less. However, the first length L1 is not limited to the above-described value.
  • a side surface of the encapsulant 150 on the package substrate 110 may be limited by a side surface of the package substrate 110. Accordingly, a planar size of the image sensor package 100 may be typically determined by a planar size of the package substrate 110.
  • the upper substrate pads 113 may be formed on an upper surface of the body layer 111 and may be connected to the wirings of the body layer 111.
  • the upper substrate pads 113 may be arranged along both side surfaces of the image sensor chip 120 mounted on the package substrate 110 and may be electrically connected to the chip pads 126 of the image sensor chip 120 by using a wire bonding process.
  • the upper substrate pads 113 may be in outer portions of both side surfaces of the package substrate 110 in the first direction (x direction) and arranged in a second direction (y direction).
  • the upper substrate pads 113 may be arranged in one column in the second direction (y direction).
  • the upper substrate pads 113 may be arranged in at least two columns in the second direction (y direction).
  • the lower substrate pads 115 may be formed on a lower surface of the body layer 111 and may be connected to the wirings of the body layer 111.
  • the lower substrate pads 115 may be arranged in three columns in the second direction (y direction).
  • the arrangement of the lower substrate pads 115 is not limited thereto.
  • the lower substrate pads 115 may be arranged in two, three, four, or more columns or arranged in a two-dimensional (2D) array structure over the entire lower surface of the body layer 111.
  • the upper and lower protective layers 117u and 117d may respectively cover an upper surface and the lower surface of the body layer 111 and may protect the body layer 111.
  • the upper protective layer 117u may be on the upper surface of the body layer 111, and/or the lower protective layer 117d may be on a lower surface of the body layer 111.
  • the upper and lower protective layers 117u 117d may include the same or different materials, and may include, for example, solder resist (SR). However, a material of the upper and lower protective layers 117u and 117d is not limited to SR.
  • the upper substrate pad 113 and the lower substrate pad 115 may pass through the upper and lower protective layers 117u and 117d corresponding thereto and may be exposed at the upper and lower protective layers 117u and 117d, respectively.
  • An external connection terminal 180 may be on the lower substrate pad 115.
  • the external connection terminal 180 may include, for example, a solder ball.
  • the image sensor package 100 of some example embodiments may be classified as a ball grid array (BGA) package, and in particular may be classified as an image sensor ball grid array (IBGA) package.
  • the image sensor package 100 of some example embodiments may be mounted on an external substrate (refer to 510 in FIG. 5 ) of a device such as a camera device, via the external connection terminal 180.
  • the image sensor chip 120 may be mounted on the package substrate 110.
  • the image sensor chip 120 may be adhered and fixed to an upper surface of the package substrate 110 by an adhesive layer 125.
  • the adhesive layer 125 may not only adhere the image sensor chip 120 to the package substrate 110.
  • the adhesive layer may reduce external impact on the image sensor chip 120.
  • the image sensor chip 120 may include a chip body 122, a sensor circuitry or sensor unit 124, and/or chip pads 126.
  • the chip body 122 may include a substrate and a wiring layer of the image sensor chip 120.
  • the substrate may include, for example, a silicon bulk wafer and/or an epitaxial wafer.
  • the epitaxial wafer may include a crystalline material layer (i.e., a heterogeneous or homogeneous epitaxial layer), which is grown on a bulk substrate by using an epitaxial process.
  • the substrate is not limited to a bulk wafer or an epitaxial wafer and may include various wafers, such as a polished wafer, an annealed wafer, and a silicon on insulator (SOI) wafer.
  • the wiring layer may be formed on any surface of the substrate.
  • the wiring layer may be under the sensor unit 124.
  • the sensor unit 124 may include a pixel area PIa including a plurality of pixels, and/or an active pixel sensor (APS) area.
  • the pixels may be arranged in a 2D array structure.
  • Each of the pixels of the pixel area PIa may include a photodiode formed in the substrate.
  • the photodiode may be formed by doping, e.g. implanting impurity ions into the pixel area PIa using an ion implantation process such as a beamline ion implantation process and/or a plasma assisted doping (PLAD) process.
  • PAD plasma assisted doping
  • Each of the pixels of the pixel area PIa may absorb incident light, may generate and accumulate charges corresponding to the amount of incident light, and may transmit the accumulated charges to the outside through a pixel transistor.
  • the pixel transistors may include, for example, a transfer transistor, a source-follower transistor, a reset transistor, and a selection transistor.
  • the sensor unit 124 may include a color filter and a microlens, which are over the pixel area PIa. As can be seen from FIG. 1B , the sensor unit 124 may be in a central portion of the image sensor chip 120.
  • the chip pads 126 may be in a peripheral area PEa of the image sensor chip 120.
  • the peripheral area PEa may refer to an outer portion of the image sensor chip 120, which surrounds the sensor unit 124.
  • the chip pads 126 may be arranged in the second direction (y direction) in outer portions of both peripheral areas PEa of the image sensor chip 120 in the first direction (x direction).
  • the chip pads 126 may be electrically connected to the wiring layer of the image sensor chip 120.
  • the chip pads 126 may be electrically connected to the upper substrate pads 113 of the package substrate 110 by using a wire bonding process.
  • first ends (e.g. 130t1 in FIG. 2A ) of the bonding wires 130 may be connected to the chip pads 126, and second ends (e.g. 130t2 in FIG. 2A ) of the bonding wires 130 may be connected to the upper substrate pads 113.
  • the bonding wires 130 may include, for example, at least one of gold (Au), copper (Cu), silver (Ag), and aluminum (Al).
  • the bonding wires 130 may include, for example, gold.
  • the transparent cover 140 may be over the image sensor chip 120.
  • the transparent cover 140 may be on the dam 160 formed on an upper surface of the image sensor chip 120.
  • the transparent cover 140 may be apart from the image sensor chip 120 by a height of the dam 160, and a cavity C may be formed between the transparent cover 140 and the image sensor chip 120.
  • the cavity C may include air, such as clean, dry air; however, example embodiments are not limited thereto.
  • the transparent cover 140 may include, for example, at least one of transparent glass, a transparent resin, or transmissive ceramic.
  • the dam 160 may support the transparent cover 140.
  • the dam 160 may encapsulate the cavity C and may prevent or reduce the likelihood of contamination of the image sensor chip 120 (e.g., the sensor unit 124) by inhibiting external moisture and/or foreign materials from penetrating into the cavity C.
  • the dam 160 may have a rectangular ring/rectangular annulus shape along an outer portion of the upper surface of the image sensor chip 120.
  • the dam may surround another portion of the upper surface.
  • the dam 160 may cover the chip pads 126 of the image sensor chip 120 and/or cover first ends 130t1 of the bonding wires 130.
  • the dam 160 may support the transparent cover 140 and may prevent or reduce the likelihood of contamination of the sensor unit 124.
  • the dam 160 may surround the sensor unit 124 and be formed on the upper surface of the image sensor chip 120.
  • a first width W1 which is a distance between an edge of the sensor unit 124 and an edge of the image sensor chip 120, is generally reduced due to the shrinking/miniaturization of the image sensor chip 120.
  • the first width W1 may be about 520 ⁇ m or less. As the first width W1 is reduced, as shown in FIG.
  • the dam 160 may have a rectangular ring shape/annular shape along an outermost portion of the image sensor chip 120 and covering the chip pad 126 arranged in the outermost portion of the image sensor chip 120 and the first end 130t1 of the bonding wire 130, which is connected to the chip pad 126.
  • an outer side surface of the dam 160 may be substantially adjacent to or the same as the side surface of the image sensor chip 120 in the first direction (x direction).
  • a size of the transparent cover 140 may be greater than a size of the image sensor chip 120.
  • a length of the transparent cover 140 may be greater than a length of the image sensor chip 120 in the first direction (x direction).
  • the outer side surface of the dam 160 may be on an inner side of a side surface of the transparent cover 140.
  • the dam 160 may include an appropriate material considering or based on the stress of the bonding wires 130 and physical properties of the encapsulant 150.
  • the dam 160 may include a glue adhesive.
  • a material of the dam 160 is not limited to a glue adhesive. The material of the dam 160 will be described in further detail with reference to FIGS. 2A and 2B .
  • the encapsulant 150 may be on the package substrate 110 and may encapsulate the image sensor chip 120, the bonding wires 130, and/or the transparent cover 140.
  • the encapsulant 150 may be formed on an upper surface of the package substrate 110 to cover side surfaces of the image sensor chip 120 and the transparent cover 140.
  • the encapsulant 150 may cover the outer side surface of the dam 160 while covering the bonding wires 130.
  • the encapsulant 150, along with the dam 160 may prevent or reduce the likelihood of the sensor unit 124 of the image sensor chip 120 being contaminated with foreign materials.
  • the encapsulant 150 may protect the image sensor package 100 from external impact.
  • the encapsulant 150 may surround the entire side surface of the transparent cover 140, and an upper surface of the encapsulant 150 may be inclined at a slight angle with respect to an upper surface of the transparent cover 140. However, in some example embodiments, the upper surface of the encapsulant 150 may be substantially coplanar with the upper surface of the transparent cover 140.
  • the encapsulant 150 may include, for example, an epoxy molding compound (EMC). However, a material of the encapsulant 150 is not limited to an EMC. A material of the encapsulant 150 will be described in further detail with reference to FIGS. 2A and 2B along with the material of the dam 160.
  • the stress reducing layers 170 may be formed in both outer portions of the package substrate 110 in the first direction (x direction) and extend in the second direction (y direction). Alternatively or additionally, the stress reducing layers 170 may cover the upper substrate pads 113 and the second ends 130t2 of the bonding wires 130, which may be connected to the upper substrate pads 113.
  • the stress reducing layer 170 may include (e.g., consist or comprise of) substantially the same material as the dam 160. In embodiments, substantially the same material may mean exactly the same material, a same type of material such as a glue adhesive, and/or having at least one substantially the same stress-related physical property (e.g., viscosity preferably at a predetermined temperature, glass temperature and/or CTE at a predetermined temperature).
  • the stress reducing layer 170 may include a glue adhesive.
  • a material of the stress reducing layer 170 is not limited to a glue adhesive. The material of the stress reducing layer 170 will be described in further detail with reference to FIGS. 2A and 2B along with the material of the dam 160.
  • the stress reducing layer 170 may be formed to have a greater thickness than the dam 160.
  • a width of the stress reducing layer 170 may be greater than a width of the dam 160 in the first direction (x direction).
  • at least one of the thickness and the width of the stress reducing layer 170 may be less than the thickness and/or the width of the dam 160 due to process restrictions.
  • the image sensor chip 120 may be mounted on the package substrate 110 by using a wire bonding technique. End portions of the bonding wires 130 for the wire bonding process may be covered by the dam 160 and/or the stress reducing layer 170.
  • the first ends 130t1 of the bonding wires 130, which are connected to the chip pads 126, may be covered by the dam 160, and the second ends 130t2 of the bonding wires 130, which are connected to the upper substrate pads 113, may be covered by the stress reducing layer 170.
  • the stress reducing layer 170 may include substantially the same material as the dam 160.
  • defects e.g., cracks
  • an image sensor package having improved reliability may be implemented.
  • FIGS. 2A and 2B are enlarged views for explaining a cause of cracks in bonding wires in a wire bonding structure of an image sensor package.
  • FIG. 2A is an enlarged view of a wire bonding portion
  • FIG. 2B is an enlarged view of region A of FIG. 2A .
  • a bonding wire 130 is illustrated in a right-angled form for brevity. The description of components of some example embodiments that are the same as those described with reference to FIGS. 1A and 1B will be omitted or briefly presented.
  • a portion of the bonding wire 130 on which stress is concentrated may be a portion of the bonding wire 130, which may be connected to a chip pad 126.
  • the bonding wire 130 is divided into a first end 130t1 connected to the chip pad 126, a second end 130t2 connected to the upper substrate pad 113, and a middle line 130m between the first end 130t1 and the second end 130t2, as indicated by dashed circles in FIG. 2B , both side surfaces of a connection portion between the first end 130t1 and the middle line 130m may be detected as or correspond to large, e.g.
  • a glass temperature, e.g. a glass transition temperature, Tg of the encapsulant 150 may be low, and/or a coefficient of thermal expansion (CTE) of the encapsulant 150 may be high at the glass temperature Tg or higher.
  • the encapsulant 150 may expand and pull the bonding wires 130 owing to thermal expansion, and thus, stress may be applied to the bonding wires 130.
  • stress may be concentrated on the connection portion between the first end 130t1 and the middle line 130m, which is covered by the dam 160.
  • the stress reducing layer 170 configured to cover the second end 130t2 of the bonding wire 130 may be formed to reduce stress applied to the connection portion between the first end 130t1 of the bonding wire 130 and the middle line 130m.
  • the stress reducing layer 170 may include substantially the same material as the dam 160. Additionally or alternatively, the stress reducing layer 170 may include a material having appropriate physical properties considering stress of the bonding wires 130 and/or physical properties of the encapsulant 150.
  • a thermal shock experiment may be conducted under a first thermal cycle (TC) condition of about - 65 °C to about 150 °C or a second TC condition of about - 55 °C to about 125 °C.
  • TC thermal cycle
  • the dam 160 and/or the encapsulant 150 may have the following physical properties in the image sensor package 100 of some example embodiments.
  • each of the dam 160 and the encapsulant 150 may have a viscosity of about 40000 centipoise (cps) to about 80000(cps) (@ 25 °C).
  • Each of the dam 160 and the encapsulant 150 may have a glass temperature of about 125 °C to about 160 °C.
  • Each of the dam 160 and the encapsulant 150 may have a CTE of about 18 ppm or less below the glass temperature and have a CTE of about 70 ppm or less at the glass temperature or higher.
  • the stress reducing layer 170 may include, e.g. may consist of or consist essentially of, substantially the same material as the dam 160.
  • a glue adhesive may be mainly used for a dam.
  • the glue adhesive may have a viscosity of about 90000 cps (@25 °C) and/or a glass temperature of about 115 °C.
  • the glue adhesive may have a CTE of about 53 ppm below the glass temperature and/or a CTE of about 163 ppm at the glass temperature or higher.
  • a first material used for the encapsulant 150 may have a viscosity of about 80000 cps (@25 °C) and/or a glass temperature of about 50 °C.
  • the first material may have a CTE of about 20 ppm below the glass temperature and/or a CTE of about 100 ppm at the glass temperature or higher.
  • a second material used for the encapsulant 150 may have a viscosity of about 42000 cps (@25 °C) and/or a glass temperature of about 148 °C.
  • the second material may have a CTE of about 18 ppm below the glass temperature and/or a CTE of about 65 ppm at the glass temperature or higher.
  • the glue adhesive may be used as the dam 160 and/or the stress reducing layer 170 and may meet or approximately be in the ranges of physical properties described above by adjusting components or a content ratio of a filler.
  • the second material described above may be used as the encapsulant 150 and may meet or approximately be in the ranges of physical properties described above by adjusting components or a content ratio of a filler.
  • Table 1 shows the results of a comparison of stress applied to the bonding wire 130 between a first package structure without the stress reducing layer 170 and a second package structure including the stress reducing layer 170. [Table 1] Use or disuse of stress reducing layer Stress@125 °C First package structure ⁇ 137.29 Second package structure ⁇ 134.49
  • both the first package structure and the second package structure may include the dam 160, and stress may be expressed in units of mega Pascal (MPa).
  • MPa mega Pascal
  • the image sensor package 100 of some example embodiments may reduce the stress applied to the bonding wire 130 by using the following methods.
  • stress applied to the bonding wire 130 may be reduced by using a method of reducing a length of the bonding wire 130, a method of adjusting physical properties of the encapsulant 150, and/or a method of increasing a package size.
  • moment such as bending moment may increase at a bonding portion of the chip pad 126, which may lead to an increase in the stress applied to the bonding wire 130.
  • the length of the bonding wire 130 may be relatively increased, and/or moment such as bending moment may increase, thereby increasing stress applied to the bonding wire 130.
  • Table 2 shows examples of stress applied to a bonding wire with respect to a package size (or PKG Size), a material of an encapsulant (or Encap.), and a length of the bonding wire (or Wire Length).
  • PKG Size Encap. Wire Length Stress@125 °C Ref. 8.0 mm First 0.4 mm 137.29 Case 1 8.0 mm First 0.3 mm 114.79 Case 2 8.0 mm First 0.5 mm 156.82 Case 3 7.3 mm First 0.4 mm 134.44 Case 4 8.7 mm First 0.4 mm 133.06 Case 5 8.0 mm Second 0.4 mm 54.34
  • PKG size may refer to a first length L1
  • First may refer to the first material
  • Second may refer to the second material.
  • the length of the bonding wire may be defined as a distance between the chip pad 126 and the upper substrate pad 113 in a first direction (x direction), and stress may be expressed in units of MPa.
  • the package size may be adjusted to about 8.0 mm or more, and/or the length of the bonding wire 130 may be adjusted to about 0.7 mm or less.
  • the length of the bonding wire 130 may be adjusted to about 0.5 mm or less.
  • the bonding wire 130 may have a length of about 1.2 mm and is currently being reduced to about 0.8 mm to about 0.9 mm.
  • a wire length of about 0.3 mm or about 0.4 mm may correspond to a length of a test level that is not yet put to practical use.
  • FIGS. 3A to 3C are plan views of image sensor packages 100a, 100b, and 100c according to some example embodiments. The description of components of some example embodiments that are the same as those described with reference to FIGS. 1A to 2B will be omitted or briefly presented.
  • the image sensor package 100a of some example embodiments may be different from the image sensor package 100 of FIG. 1B in terms of a structure of a stress reducing layer 170a.
  • the stress reducing layer 170a may extend in a second direction (y direction) and/or may cover some upper substrate pads 113 and/or second ends (refer to 130t2 in FIG. 2A ) of some bonding wires 130 corresponding thereto.
  • the stress reducing layer 170a may not cover all upper substrate pads 113, which are arranged in the second direction (y direction), and the second ends 130t2 of all bonding wires 130 corresponding thereto.
  • a plurality of stress reducing layers 170a may be arranged to correspond to all upper substrate pads 113 arranged on either side in a first direction (x direction).
  • each of the stress reducing layers 170a may cover two upper substrate pads 113, which are adjacent to each other in the second direction (y direction), and second ends 130t2 of two bonding wires 130 corresponding thereto.
  • each of the stress reducing layers 170a may cover at least three upper substrate pads 113 and the second ends 130t2 of at least three bonding wires 130 corresponding thereto.
  • the stress reducing layer 170a may cover one upper substrate pad 113 and the second end 130t2 of one bonding wire 130 corresponding thereto.
  • the image sensor package 100b of some example embodiments may be different from the image sensor package 100 of FIG. 1B in terms of the arrangement of upper substrate pads 113a of a package substrate 110a and a wire bonding structure caused thereby.
  • the upper substrate pads 113a may be arranged at a greater pitch, e.g. a greater repeating edge-to-edge distance, than chip pads 126 of an image sensor chip 120.
  • the upper substrate pads 113a may be arranged at a first pitch P1 in a second direction (y direction), and the chip pads 126 may be arranged at a second pitch P2, which is less than the first pitch PI, in the second direction (y direction).
  • the upper substrate pads 113 may be arranged at substantially the same pitch as the chip pads 126 in the second direction (y direction).
  • bonding wires 130a may have a greater length toward both outer portions of the package substrate 110a in the second direction (y direction) and may spread out, such as in a fan rib shape.
  • the stress reducing layers 170 may cover all upper substrate pads 113a, which are arranged in the second direction (y direction), and the second ends 130t2 of all bonding wires 130a corresponding thereto.
  • the stress reducing layer 170 may cover some upper substrate pads 113a and the second ends 130t2 of some bonding wires 130a corresponding thereto.
  • a plurality of stress reducing layers 170 may be arranged to correspond to all upper substrate pads 113 on either side in a first direction (x direction).
  • the image sensor package 100c of some example embodiments may be different from the image sensor package 100 of FIG. 1B in that a package substrate 110b and an image sensor chip 120a have square shapes.
  • the image sensor package 100c of some example embodiments may be different from the image sensor package 100 of FIG. 1B in that upper substrate pads 113b of the package substrate 110b and chip pads 126a of the image sensor chip 120a are arranged on preferably all four sides of the package substrate 110b and a wire bonding structure is formed on preferably each of the four sides of the package substrate 110b.
  • the package substrate 110b may have a square shape in a plan view, e.g. in a view from above.
  • the upper substrate pads 113b may be arranged on at least three, such as all four sides of an outer portion of an upper surface of the package substrate 110b.
  • the upper substrate pads 113b may be arranged in a second direction (y direction) on both sides of the package substrate 110b in a first direction (x direction) and also, arranged in the first direction (x direction) on both sides of the package substrate 110b in the second direction (y direction).
  • the image sensor chip 120a may have a square shape in a plan view, and the chip pads 126a may be arranged on all four sides of an outer portion of an upper surface of the image sensor chip 120a.
  • at least one of the package substrate 110b and the image sensor chip 120a may have a long rectangular shape in one direction, for example, the first direction (x direction).
  • a wire bonding structure may be configured such that the upper substrate pad 113b of the package substrate 110b is connected to a corresponding one of the chip pads 126a of the image sensor chip 120a through the bonding wire 130.
  • the wire bonding structure may be formed on each of all four sides of the package substrate 110b or the image sensor chip 120a to correspond to the arrangement of the upper substrate pads 113b and the chip pads 126a.
  • the upper substrate pads 113b may be arranged at substantially the same pitch as the chip pads 126a.
  • the bonding wires 130 may extend parallel to each other in the first direction (x direction) or in the second direction (y direction).
  • a pitch between the upper substrate pads 113b may be greater than a pitch between the chip pads 126a.
  • a wire bonding structure may be configured such that the bonding wires 130 spread in a fan rib shape.
  • the stress reducing layer 170b may have a rectangular ring shape along the entire outer portion of the upper surface of the package substrate 110b.
  • the layer 170b may surround another portion of the upper surface.
  • the stress reducing layer 170b may have the rectangular ring shape and cover all the upper substrate pads 113b on the upper surface of the package substrate 110b and second ends 130t2 of all the bonding wires 130 corresponding thereto.
  • the stress reducing layer 170b may only cover some upper substrate pads 113b and the second ends 130t2 of some bonding wires 130 corresponding thereto. In this case, a plurality of stress reducing layers 170b may be arranged.
  • each of the stress reducing layers 170b may cover all upper substrate pads 113b arranged in a side corresponding thereto and the second ends 130t2 of all bonding wires 130 corresponding thereto.
  • two, three, or five or more stress reducing layers 170b may be arranged on the upper surface of the package substrate 110b.
  • FIGS. 4A to 4D are cross-sectional views of image sensor packages 100d, 100e, 100f, and 100g according to some example embodiments.
  • the description of components of some example embodiments that are the same as those described with reference to FIGS. 1A to 3C will be omitted or briefly presented.
  • the image sensor package 100d of some example embodiments may be different from the image sensor package 100 of FIG. 1A in that the image sensor package 100d further includes a coating layer 142 formed on a transparent cover 140.
  • the coating layer 142 may be formed conformally, and/or may be formed on a lower surface and on a side surface of the transparent cover 140.
  • the coating layer 142 may have various functions.
  • the coating layer 142 may block infrared (IR) light.
  • IR infrared
  • an IR filter configured to block IR light may be omitted from a camera device, which may reduce costs.
  • the coating layer 142 may increase transmittance and/or prevent or reduce the likelihood of reflection.
  • the coating layer 142 may be or may include a blue filter coating layer and/or an anti-reflection coating layer.
  • the function of the coating layer 142 is not limited to the above-described functions
  • the image sensor package 100e of some example embodiments may be different from the image sensor package 100 of FIG. 1A in terms of a structure of an encapsulant 150a.
  • the encapsulant 150a may cover only a portion of a side surface of a transparent cover 140.
  • the encapsulant 150a may cover only a lower portion of the side surface of the transparent cover 140 but expose an upper portion of the side surface of the transparent cover 140.
  • the encapsulant 150a may cover an upper surface of the transparent cover 140.
  • an overflow defect may occur. Accordingly, only a portion of the side surface of the transparent cover 140 may be covered by the encapsulant 150a, and thus, the overflow defect may be prevented or reduced in likelihood of occurrence in advance.
  • the image sensor package 100f of some example embodiments may be different from the image sensor package 100 of FIG. 1A in terms of the arrangement of upper substrate pads 113c and a wire bonding structure caused thereby.
  • the upper substrate pad 113c may be most adjacent to an image sensor chip 120 within a range in which a wire bonding process may be performed.
  • stress applied to a bonding wire 130 may be reduced as a length of the bonding wire 130 is reduced.
  • the upper substrate pad 113c of a package substrate 110c may be as close as possible to the image sensor chip 120.
  • a length of the bonding wire 130 may be reduced, thereby reducing stress applied to the bonding wire 130.
  • a stress reducing layer 170c may cover the upper substrate pad 113c and a second end 130t2 of the bonding wire 130, which is connected to the upper substrate pad 113c.
  • the stress reducing layer 170c may be moved to an inner portion of the package substrate 110.
  • the image sensor package 100g of some example embodiments may be different from the image sensor package 100 of FIG. 1A in terms of a structure of a package substrate 110d and a mounting structure and a wire bonding structure of an image sensor chip 120, which are caused by the structure of the package substrate 110d.
  • the package substrate 110d may include a groove G formed in a central portion thereof.
  • the image sensor chip 120 may be inside the groove G and adhered to and mounted on the package substrate 110d by using an adhesive layer 125.
  • Upper substrate pads 113d may be arranged in a second direction (e.g. in a y direction) in outer portions of both side surfaces of the package substrate 110d in a first direction (x direction). However, if the image sensor chip 120 is inside the groove G of the package substrate 110d, a top level of the image sensor chip 120 may be similar to a top level of the package substrate 110d. Also, the upper substrate pad 113d of the package substrate 110d may be maintained at substantially the same level as a chip pad 126 of the image sensor chip 120. Accordingly, when the upper substrate pad 113d is maintained at substantially the same level as the chip pad 126, the upper substrate pad 113d may be as close as possible to the image sensor chip 120. Thus, a length of the bonding wire 130 may be reduced, thereby reducing stress of the bonding wire 130.
  • the stress reducing layer 170d may cover the upper substrate pad 113d and the second end 130t2 of the bonding wire 130, which is connected to the upper substrate pad 113d. If the upper substrate pad 113d is maintained at substantially the same level as the chip pad 126, when the stress reducing layer 170d is formed to the same thickness as a dam 160, the stress reducing layer 170d may be at substantially the same top level as the dam 160.
  • a top level of the transparent cover 140 stacked on the image sensor chip 120 by using the dam 160 may be lowered by as much as a depth of the groove G, and a thickness of the encapsulant 150 may also be reduced. Accordingly, a total thickness of the image sensor package 100g may be reduced. As a result, the image sensor package 100g of some example embodiments may contribute to implementing an image sensor package having a small thickness.
  • Example embodiments are not limited to those described above. Furthermore, none of the above described example embodiments are necessarily mutually exclusive to one another. For example, some example embodiments may include some features described with reference to one figure, and may simultaneously include some other features described with reference to one or more other figures.
  • FIG. 5 is a cross-sectional view of a camera device 1000 including an image sensor package 100, according to some example embodiments.
  • the description of components of some example embodiments that are the same as those described with reference to FIGS. 1A to 4D will be omitted or briefly presented.
  • the camera device 1000 of some example embodiments may include the image sensor package 100 and a camera appearance form factor or chassis, or camera appearance unit 500.
  • the image sensor package 100 may include the image sensor package 100 of FIG. 1A .
  • inventive concepts are not limited thereto, and the camera device 1000 of some example embodiments may adopt one or more of the image sensor packages 100a to 100g shown in FIGS. 3A to 3C and FIGS. 4A to 4D instead of or in addition to the image sensor package 100 of FIG. 1A .
  • the camera appearance unit 500 may include an external substrate 510, a housing 520, a filter 530, and/or a lens 540.
  • the image sensor package 100 may be mounted on the external substrate 510 by using an external connection terminal 180.
  • the external connection terminal 180 may be or may include, for example, a solder ball.
  • the image sensor package 100 may be electrically connected to the external substrate 510 through the external connection terminal 180.
  • the external substrate 510 may include a circuit configured to perform an additional function or a circuit to be connected to another device. When there is no need to form a substrate separately, the external substrate 510 may constitute a portion of the housing 520.
  • the housing 520 may surround the image sensor package 100 and may protect the image sensor package 100 from external physical impact. Additionally or alternatively, the housing 520 may include an electromagnetic interference (EMI) shielding material and may shield the image sensor package 100 from disturbance.
  • EMI electromagnetic interference
  • the filter 530 may be positioned at an entrance side of the housing 520 in which the lens 540 is located, and be a predetermined distance apart from the image sensor package 100.
  • the filter 530 may include, for example, an infrared (IR) cut-off filter, namely, an IR filter.
  • the filter 530 may be provided as a separate component from the camera appearance unit 500.
  • a coating layer 142 configured to block IR light is formed on a transparent cover 140 as described above, the filter 530 may be omitted.
  • the lens 540 may be at an entrance portion (e.g., a barrel portion) of the housing 520 and refract external incident light and emit the refracted light to the image sensor package 100.
  • the external incident light may be condensed on the sensor unit 124 of the image sensor chip 120 of the image sensor package 100 through the lens 540.
  • a plurality of lenses 540 may be at the barrel portion of the housing 520.
  • the camera device 1000 of some example embodiments may be used in various fields.
  • the camera device 1000 may be applied to front and rear cameras for vehicles. Compulsory installation of image sensor packages for vehicles is underway worldwide, and may be starting with rear cameras. The image sensor packages for the vehicles have been transitioning away from the role of parking assistance and linked to driving systems, and more weight is being placed on the image sensor packages for autonomous vehicles. Accordingly, the reliability of the image sensor packages for vehicles is emerging as a more important issue than before.
  • the image sensor package 100 of the camera device 1000 of some example embodiments may include a stress reducing layer 170 including the same material as a dam 160, and an encapsulant 150 and the dam 160 may have physical properties in the same ranges as those described above.
  • stress applied to a bonding wire 130 may be reduced, and thus, defects (e.g., cracks) may be prevented or reduced in likelihood from occurring in the bonding wire 130 to greatly improve reliability.
  • the camera device 1000 of some example embodiments may include the image sensor package 100 having high reliability and be useful for vehicle cameras.
  • FIGS. 6A to 6I are cross-sectional views of a method of fabricating an image sensor, according to some example embodiments.
  • FIGS. 6A to 6I will be described with reference to FIGS. 1A and 1B .
  • the description of components of some example embodiments that are the same as those described with reference to FIGS. 1A to 5 will be omitted or briefly presented.
  • the method of manufacturing/fabricating the image sensor package may include preparing a package substrate 110.
  • the package substrate 110 may include a body layer 111, an upper substrate pad 113, a lower substrate pad 115, and/or upper and/or lower protective layers 117u and 117d.
  • the body layer 111 may include single-layered or multilayered wirings, and the upper substrate pad 113 may be electrically connected to the lower substrate pad 115 corresponding thereto through the wirings of the body layer 111.
  • the package substrate 110 shown in FIG. 6A may be a portion of a prototype substrate including a plurality of package substrates 110.
  • the upper substrate pads 113 may be on an upper surface of the package substrate 110 and arranged in a second direction (y direction) in outer portions of both side surfaces of the package substrate 110 in a first direction (x direction).
  • the lower substrate pads 115 may be formed on a lower surface of the body layer 111 and arranged in three columns. However, in some example embodiments, the lower substrate pads 115 may be arranged in two or four or more columns or arranged in a 2D array structure over the entire lower surface of the body layer 111.
  • the upper substrate pads 113 and the lower substrate pads 115 may pass through the upper and lower protective layers 117u and 117d respectively corresponding thereto and be exposed at the upper and lower protective layers 117u and 117d.
  • an adhesive layer 125 may be formed by coating the upper surface of the package substrate 110 with an adhesive.
  • the adhesive layer 125 may be formed in a central portion of the upper surface of the package substrate 110 to correspond to a position at which the image sensor chip 120 is to be mounted.
  • the formation of the adhesive layer 125 may include coating the upper surface of the package substrate 110 with a flowable adhesive by using a dispenser, and curing the flowable adhesive to some extent, and/or may include adhering an adhesive film to the central portion of the upper surface of the package substrate 110.
  • the image sensor chip 120 may be mounted on the package substrate 110.
  • the image sensor chip 120 may be adhered and fixed to the package substrate 110 by the adhesive layer 125.
  • the image sensor chip 120 may include a chip body 122, a sensor unit 124, and/or a chip pad 126.
  • the chip body 122 may include a substrate and a wiring layer of the image sensor chip 120.
  • the sensor unit 124 may include a pixel area PIa including a plurality of pixels, and the pixels may be arranged in a 2D array structure in the pixel area PIa. Each of the pixels of pixel area PIa may include a photodiode formed in or within the substrate.
  • the sensor unit 124 may be in a central portion of the image sensor chip 120.
  • the chip pad 126 may be in a peripheral area PEa of the image sensor chip 120.
  • the chip pads 126 may be arranged in the second direction (y direction) in outer portions of both peripheral areas of the image sensor chip 120 in the first direction (x direction
  • a wire bonding process for connecting the chip pads 126 of the image sensor chip 120 to the upper substrate pads 113 of the package substrate 110, which correspond thereto, by using bonding wires 130 may be performed.
  • the wire bonding process may be performed using, for example, capillary. Due to the wire bonding process, a first end 130t1 of the bonding wire 130 may be connected to the chip pad 126, and a second end 130t2 of the bonding wire 130 may be connected to the upper substrate pad 113.
  • the bonding wire 130 may include or consist of, for example, gold. However, a material of the bonding wire 130 is not limited to gold.
  • the dam 160 may be formed on an upper surface of the image sensor chip 120.
  • the dam 160 may be formed by a dispensing method using a dispenser. As shown in FIG. 1B , the dam 160 may be along an outer portion of the upper surface of the image sensor chip 120 and/or have a rectangular ring shape. Preferably, the dam may surround another portion of the upper surface. Moreover, the dam 160 may cover the chip pad 126 of the image sensor chip 120 and the first end 130t1 of the bonding wire 130, which may be connected to the chip pad 126.
  • the dam 160 may include a material having the above-described physical properties.
  • the dam 160 may include a material having a viscosity of about 40000 cps to about 80000 cps (@25 °C), a glass temperature of about 125 °C to about 160 °C, a CTE of about 18 ppm or less at a temperature lower than the glass temperature, and/or a CTE of about 70 ppm or less at the glass temperature or higher.
  • the dam 160 may include a glue adhesive.
  • the glue adhesive may meet or approximately be within the ranges of physical properties described above, by adjusting components of and/or a content ratio of a filler.
  • the stress reducing layer 170 may be formed on the package substrate 110.
  • the stress reducing layer 170 may also be formed by a dispensing method using a dispenser.
  • the stress reducing layer 170 may have a straight line shape extending in the second direction (y direction) in the outer portions of both the side surfaces of the package substrate 110 in the first direction (x direction).
  • the stress reducing layer 170 may cover the upper substrate pad 113 of the package substrate 110 and the second end 130t2 of the bonding wire 130, which is connected to the upper substrate pad 113.
  • the stress reducing layer 170 may include or consist of substantially the same material as the dam 160.
  • the stress reducing layer 170 may include the glue adhesive.
  • the glue adhesive may meet or approximately be in the ranges of physical properties described above by adjusting components or a content ratio of a filler.
  • a transparent cover 140 may be stacked on the dam 160.
  • the stacking of the transparent cover 140 on the dam 160 may be performed while heat and pressure are applied.
  • the dam 160 may be adhered to the transparent cover 140 due to viscosity and encapsulate a cavity C.
  • the dam 160 may encapsulate the cavity C and prevent or reduce the likelihood of external moisture or foreign materials from penetrating into the sensor unit 124 of the image sensor chip 120.
  • the image sensor chip 120, the bonding wire 130, and/or the transparent cover 140 may be encapsulated by coating the package substrate 110 with an encapsulant 150.
  • the encapsulant 150 may cover side surfaces of the image sensor chip 120 and the dam 160. Alternatively or additionally, the encapsulant 150 may cover a side surface and/or a portion of the lower surface of the transparent cover 140. Alternatively or additionally, the encapsulant 150 may cover a middle line 130m of the bonding wire 130 between the first end 130t1 and the second end 130t2.
  • the encapsulant 150 may prevent or reduce the likelihood of the sensor unit 124 of the image sensor chip 120 from being contaminated with foreign materials and/or protect the image sensor package 100 from external impact.
  • the encapsulant 150 may include a material having the above-described physical properties.
  • the encapsulant 150 may include a material having a viscosity of about 40000 cps to about 80000 cps (@25 °C), a glass temperature of about 125 °C to about 160 °C, a CTE of about 18 ppm or less at a temperature lower than the glass temperature, and/or a CTE of about 70 ppm or less at the glass temperature or higher.
  • the encapsulant 150 may include the second material described above. The second material may meet or approximately be within the ranges of physical properties described above by adjusting components or a content ratio of a filler.
  • the encapsulant 150 may be formed by, for example, a dispensing method using a dispenser.
  • an external connection terminal 180 may be adhered to the lower substrate pad 115 on the lower surface of the package substrate 110.
  • the external connection terminal 180 may include, for example, a solder ball.
  • the operations described with reference to FIGS. 6A to 6I may be performed on a prototype substrate including a plurality of package substrates 110.
  • a singulation process may be performed.
  • the image sensor package 100 of FIG. 1A may be fabricated.
  • FIGS. 7A and 7B are cross-sectional views of a method of fabricating an image sensor package, according to some example embodiments.
  • FIGS. 7A and 7B will be described with reference to FIGS. 1A and 1B .
  • the description of components of some example embodiments that are the same as those described with reference to FIGS. 6A to 6I will be omitted or briefly presented.
  • the method of fabricating the image sensor package of some example embodiments may include sequentially performing the operations of FIGS. 6A to 6D . Thereafter, as shown in FIG. 6F , a stress reducing layer 170 may be formed on the package substrate 110. At least one of a shape, a forming method, and a material of the stress reducing layer 170 may be the same as those described with reference to FIG. 6F .
  • a dam 160 may be formed on the upper surface of the image sensor chip 120 as shown in FIG. 6E .
  • a shape, a forming method, and a material of the dam 160 may be the same as those described with reference to FIG. 6E .
  • the operations described with reference to FIGS. 6G to 6I and a singulation process may be performed, and thus, the image sensor package 100 of FIG. 1A may be fabricated.
  • the method of fabricating the image sensor package of some example embodiments may be different from the method of fabricating the image sensor package, which has been described with reference to FIGS. 6A to 6I , in that the stress reducing layer 170 is formed earlier than the dam 160. Moreover, if both the stress reducing layer 170 and the dam 160 are formed by a dispensing method using a dispenser, in some example embodiments, the stress reducing layer 170 and the dam 160 may be simultaneously formed together.

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US20230397354A1 (en) * 2022-06-06 2023-12-07 Tong Hsing Electronic Industries, Ltd. Sensor package structure
CN115086533B (zh) * 2022-07-15 2024-08-23 维沃移动通信有限公司 摄像模组和电子设备

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