EP3977682A1 - Dispositif de test de détection d'erreur pour une station d'abonné d'un système de bus série et procédé de test de mécanismes de détection d'erreur lors d'une communication dans un système de bus série - Google Patents

Dispositif de test de détection d'erreur pour une station d'abonné d'un système de bus série et procédé de test de mécanismes de détection d'erreur lors d'une communication dans un système de bus série

Info

Publication number
EP3977682A1
EP3977682A1 EP20728742.6A EP20728742A EP3977682A1 EP 3977682 A1 EP3977682 A1 EP 3977682A1 EP 20728742 A EP20728742 A EP 20728742A EP 3977682 A1 EP3977682 A1 EP 3977682A1
Authority
EP
European Patent Office
Prior art keywords
signal
bit
frame
error detection
test device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20728742.6A
Other languages
German (de)
English (en)
Other versions
EP3977682B1 (fr
Inventor
Florian Hartwich
Christian Horst
Carsten Gebauer
Arthur Mutter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3977682A1 publication Critical patent/EP3977682A1/fr
Application granted granted Critical
Publication of EP3977682B1 publication Critical patent/EP3977682B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/4013—Management of data rate on the bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

Definitions

  • the present invention relates to an error detection test device for a subscriber station of a serial bus system and a method for testing mechanisms for error detection during communication in a serial bus system, with which the function of im during operation
  • a bus system can be used instead of a point-to-point connection for cost reasons, in which data is provided as messages in the ISO11898-l: 2015 standard as a CAN protocol specification with CAN FD be transmitted.
  • the messages are between the
  • CAN FD is currently used in the introductory phase in the first step mostly with a data bit rate of 2Mbit / s for the transmission of bits of the data field and with an arbitration bit rate of 500kbit / s for the transmission of bits of the arbitration field in the vehicle.
  • Subscriber stations in the bus system.
  • the speed of data transmission in the bus system is also influenced by the fact that data transmission in the bus system functions correctly. Therefore mechanisms for error detection are in place. If errors occur, a frame that is currently being transmitted is aborted and then transmitted again. This results in multiple transmission of data, which in turn reduces the speed of data transmission.
  • CRC checksum
  • CRCs checksums
  • an error detection test device for a subscriber station of a serial bus system and a method for testing mechanisms for error detection in a
  • Communication are provided in a serial bus system, in which, when compatible with earlier communication versions of the subscriber station and with high system security an increase in the amount of user data per frame compared to earlier communication versions of the
  • Subscriber station can be realized.
  • the task is performed by a fault detection test facility for a
  • the error detection test device has an evaluation module for evaluating which bit in a signal must be disturbed so that the
  • Receivers of the resulting signal in which the at least one bit is disturbed, can check the function of a predetermined error detection mechanism, the signal being processed by a protocol control unit during operation of the subscriber station in order to be transmitted as a frame on a bus of the bus system or to decode the signal from the frame after receiving a frame from the bus, and an output connection for outputting a switching signal to the protocol control unit in order to read the at least one bit evaluated by the evaluation module in relation to that of the protocol To disturb the control unit output signal, wherein the evaluation module is designed to generate the switching signal on the basis of the evaluated by the evaluation module at least one bit.
  • the error detection test device enables the subscriber station, as the transmitter and / or receiver of a frame, which can in particular be a CAN frame or another serially transmitted frame, to falsify a correct frame by specifically interspersing bit errors.
  • the error detection test device can falsify the frame in such a way that the receiver of the frame detects a predetermined error, in particular a checksum error (CRC error) or a format error in the frame or a stuff error, depending on the position of the bit error.
  • CRC error checksum error
  • a stuffing error occurs when a stuffing rule that was used when the frame was created is violated.
  • a dynamic bit stuffing rule applies to CAN FD up to the beginning of the CRC field, according to which an inverse stuff bit is to be inserted after 5 identical bits in a row.
  • a fixed stuffing rule applies to CAN FD from the beginning of the CRC field, according to which a fixed stuff bit must be inserted after a fixed number of bits.
  • a number of 2 or more bits can be inserted as fixed stuff bits will.
  • the mentioned bit stuffing rules can be modified with a CAN FD successor or other bit stuffing rules can be used.
  • the recipients of the frame falsified by the error detection test device have recognized the error, the recipients can report the error using the options available for this, in particular by sending an error frame.
  • the error detection test device can therefore be used to verify the correct functioning of the mechanisms for error detection defined in the protocol in the finished system. Therefore, these mechanisms can be taken into account when considering system security.
  • the subscriber station can also increase the
  • the method carried out by the subscriber station can also be used if there is also at least one CAN subscriber station and / or at least one CAN FD subscriber station in the bus system which
  • the fault detection test device also has a control module for switching on the fault detection test device shortly before Start of the signal or to switch off the error detection test device after the end of the signal.
  • the evaluation module and / or the control module are / is optionally designed to also evaluate an identifier of the frame and / or a control bit in relation to the frame to be sent (in order to determine whether the error detection test device should be switched on shortly before the start of the signal or not.
  • the evaluation module and / or the control module are / is optionally designed to also evaluate a control bit in the memory for the frame to be sent in order to determine whether or not the error detection test device should be switched on shortly before the start of the signal.
  • the error detection test device can also have at least one counter for counting bits of the signal, at least one configuration register for specifying a predetermined counter value for the counter after the error detection test device is switched on, at least one input connection for receiving information on the signal from the protocol Control unit, and at least one output connection for signaling with the switching signal when at least part of a bit in the signal is to be disturbed, the disturbance of the signal corresponding to a checksum error and / or a stuff error and / or a format error.
  • the at least one counter can be designed to count each bit of the signal on the basis of the information received at the at least one input connection and to output the switching signal at the at least one output connection on the basis of the counter value specified by the at least one configuration register .
  • the at least one counter is designed to count each bit of the signal on the basis of the information received at the at least one input connection and when the from
  • the signal is a transmission signal that is to be sent on the bus in one frame, or that the signal is a reception signal that is to be received by the bus in one frame, or that the signal is for an interframe distance between frames was generated on the bus.
  • bit time of one differs in the first
  • the evaluation module can be designed to generate the switching signal in such a way that the bit of the signal is inverted.
  • the evaluation module is designed to generate the switching signal in such a way that at least one time quantum of the bit of the signal is inverted, the bit being divided into at least two time quanta and the error detection test device being designed such that it can be configured in how many time quanta the bit is divided.
  • the frame can be designed to be compatible with CAN FD.
  • At least one of the previously described error detection test devices can be part of a subscriber station for a serial bus system.
  • Subscriber station also has a communication control device for
  • Communication control device has the protocol control unit, which is designed to process the signal during operation of the subscriber station in order to be transmitted as a frame on a bus of the bus system or to decode the signal from the frame after receiving a frame from the bus, and a transmission - / Receiving device for sending a transmission signal generated by the communication control device as a frame on the bus and / or for receiving a frame from the bus.
  • the subscriber station can also have a logic module for inputting the signal processed by the protocol control unit and the switching signal and for outputting the disturbed signal, the switching signal only being active for the part of the bit that is to be disturbed, and the transmission / Receiving device is designed to store the signal disturbed by the at least one error detection test device in order to evaluate the disturbed signal.
  • the subscriber station described above can be part of a bus system which also comprises a bus and at least two subscriber stations which are connected to one another via the bus in such a way that they can communicate with one another serially.
  • at least one of the at least two subscriber stations is a previously described subscriber station.
  • the aforementioned object is also achieved by a method for testing mechanisms for error detection during communication in a serial bus system according to claim 15.
  • the method is carried out with an error detection test device for a subscriber station of the bus system, the method comprising the steps of evaluating, with an evaluation module of the error detection test device, which bit in a signal must be disturbed so that the receivers of the resulting signal in which the at least one bit is disturbed, the function of a predetermined error detection mechanism can be checked, the signal being processed by a protocol control unit of the subscriber station during operation of the subscriber station in order to be transmitted as a frame on a bus of the bus system or after receiving a frame from the bus, decoding the signal from the frame, and outputting, with an output connection, a switching signal to the protocol control unit in order to reduce the at least one bit evaluated by the evaluation module in the signal output by the protocol control unit to disturb, the evaluation module sending the switching signal to the The basis of the at least one bit evaluated by the evaluation module is generated.
  • FIG. 1 shows a simplified block diagram of a bus system according to a first exemplary embodiment
  • FIG. 2 shows a diagram to illustrate the structure of a message that can be sent by a subscriber station of the bus system according to the first exemplary embodiment
  • FIG. 3 shows a simplified schematic block diagram of a subscriber station of the bus system according to the first exemplary embodiment
  • bus signals CAN_H and CAN_L which can be bus signals CAN-FX_H and CAN-FX_L in the subscriber station according to the first embodiment
  • 6 and 7 each show a timing diagram to illustrate a special bit sequence of a transmission signal TXD.
  • FIG. 8 and FIG. 9 each show different transmission signals emanating from the
  • Subscriber station can be generated according to a second embodiment.
  • elements that are the same or have the same function are provided with the same reference symbols, unless otherwise specified.
  • FIG. 1 shows a bus system 1 which is a serial bus system in which data is transmitted serially.
  • the bus system 1 can in particular fundamentally be designed for a CAN bus system, a CAN FD bus system, a CAN FD successor bus system, which is hereinafter referred to as the CAN FX bus system, and / or modifications thereof, as described below as an example.
  • the bus system 1 can be used in a vehicle, in particular a motor vehicle, an airplane, etc., or in a hospital or an industrial plant, etc. use.
  • the bus system 1 has a multiplicity of subscriber stations 10, 20, 30, each of which is connected to a bus 40 with a first bus core 41 and a second bus core 42.
  • the bus wires 41, 42 can also be called CAN_H and CAN_L or CAN-FX_H and CAN-FX_L in a CAN-based bus system and are used for electrical signal transmission
  • Messages 45, 46 in the form of signals between the individual subscriber stations 10, 20, 30 can be transmitted serially via bus 40. If an error occurs during communication on bus 40, as shown by the jagged black block arrow in FIG. 1, an error frame 47 (error flag) can optionally be sent.
  • the error frame 47 can optionally be designed in such a way that the error frame 47 reports the type of error detected.
  • the subscriber stations 10, 20, 30 are for example
  • Control units, sensors, display devices, etc. of a motor vehicle Control units, sensors, display devices, etc. of a motor vehicle.
  • the subscriber station 10 has a
  • the subscriber station 20 has a
  • Communication control device 21 a transmitting / receiving device 22 and a communication error detection module 14.
  • Subscriber station 20 also has an error detection test device 15.
  • Subscriber station 30 has a communication control device 31, a transceiver 32 and a communication error detection module 34.
  • Subscriber station 30 also optionally has an error detection test device 35. Transmit / receive devices 12, 22 , 32 the
  • Subscriber stations 10, 20, 30 are each connected directly to bus 40, even if this is not illustrated in FIG. 1.
  • the communication control devices 11, 21, 31 each serve to control communication between the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.
  • the communication control devices 11, 31 create and read first
  • Messages 45 which are modified CAN messages 45, for example.
  • the modified CAN messages 45 are constructed on the basis of a CAN FD successor format, which is also called CAN FX format below and which is described in more detail with reference to FIG. 2.
  • Communication control devices 11, 31 can also be designed to provide a CAN FX message 45 or a CAN FD message 46 for the transmitting / receiving devices 12, 32 or to receive it from them, as required.
  • the modules 14, 34 and the devices 15, 35 are used here, as described in more detail below.
  • Communication control devices 11, 31 thus create and read a first message 45 or second message 46, the first and second messages 45, 46 differing in their data transmission standard, namely in this case CAN FX or CAN FD.
  • the communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1: 2015, ie like a CAN FD tolerant Classical CAN CAN controller or a CAN FD controller.
  • the communication control device 21 creates and reads second messages 46, for example CAN FD messages 46.
  • the CAN FD messages 46 can include a number of 0 to 64 data bytes, which also have a significantly faster data rate than a Classical CAN Message to be transmitted.
  • the communication control device 21 is designed like a conventional CAN FD controller.
  • the transmitting / receiving device 22 can be like a conventional CAN
  • Transceiver according to ISO 11898-1: 2015 or CAN FD transceiver.
  • the transmitting / receiving devices 12, 32 can be designed to receive messages 45 according to the CAN FX format or messages 46 according to the current CAN FD format for the associated
  • Communication control device 11, 31 to provide or to receive from this.
  • the modules 14, 24, 34 can be constructed identically in terms of their function.
  • Devices 15, 25, 35 can be constructed identically in terms of their function.
  • FIG. 2 shows a CAN FX frame 450 for the message 45, as it is provided by the communication control device 11 for the transmitting / receiving device 12 for sending on the bus 40.
  • Communication control device 11 defines the frame 450 in the present exemplary embodiment as compatible with CAN FD, as also in FIG. 2
  • the CAN FX frame 450 for CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 and a data phase 452.
  • the frame 450 has an arbitration field 453, a control field 454 Data field 455, a checksum field 456 for a checksum F_CRC, a synchronization field 457 and a
  • ID which has 11 bits, for example, is negotiated bit by bit in the arbitration field 453 between the subscriber stations 10, 20, 30 which subscriber station 10, 20, 30 would like to send the message 45, 46 with the highest priority and therefore for the next time to send in the
  • subsequent data phase 452 receives exclusive access to bus 40 of bus system 1.
  • the frames 450 arbitrate with their identifier (ID) left-justified against other frames 450 or against CAN FD frames for the next exclusive, collision-free access to the bus 40.
  • ID identifier
  • the identifier (ID) is followed by an RRS bit.
  • the following IDE bit is sent dominantly, since a recessively sent IDE bit in CAN FD format switches to a 29-bit identifier.
  • bits which are shown with a thick line on their lower line in FIG. 2 are transmitted as dominant in frame 450.
  • bits which are shown with a thick line on their upper line in FIG. 2 are sent as recessive in frame 450.
  • a physical layer as in CAN and CAN-FD is used.
  • the physical layer corresponds to
  • phase 451 An important point during phase 451 is that the known CSMA / CR method is used, which allows simultaneous access to the
  • Subscriber stations 10, 20, 30 allowed on the bus 40 without the higher priority message 45, 46 being destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to bus system 1 relatively easily, which is very advantageous.
  • Bus wiring results in longer time constants. This leads to a
  • a sender of the message 45 does not begin sending bits of the data phase 452 on the bus 40 until the subscriber station 10 as the sender
  • the subscriber station 10 uses a CAN / CAN-FD partially, in particular up to the FDF bit (inclusive), to create the frame 450 in the arbitration phase 451 as the first communication phase
  • the subscriber station 10 uses the FDF bit in the first communication phase and in the second communication phase, the
  • the FXF bit follows directly after the FDF bit, the position of which corresponds to the “res bit” in the CAN FD base frame format, as mentioned above. If the FXF bit is sent as 1, i.e. recessive, it identifies frame 450 as a CAN FX frame. For a CAN FD frame, the communication control device 11 sets the FXF bit as 0, that is to say dominant.
  • the res bit known from CAN FD which is referred to below as the FXF bit, is therefore used to switch from the CAN FD format to the CAN FX format. Therefore the frame formats of CAN FD and CAN FX are the same up to the res bit.
  • a CAN FX subscriber station that is to say here the subscriber stations 10, 30, also supports CAN FD.
  • the dynamic bit stuffing rule of CAN FD applies up to the FXF bit in control field 454, so that an inverse stuff bit must be inserted after 5 identical bits in a row.
  • a fixed stuffing rule applies, so that a fixed stuff bit must be inserted after a fixed number of bits.
  • a number of 2 or more bits can be inserted as fixed stuff bits.
  • the FXF bit is followed in frame 450 by a resFX bit, which is a dominant bit for future use.
  • the resFX bit could also be defined exactly the other way around, atseals, so that it must be sent as 1, i.e. recessive, so that the receiving
  • Protocol exception state goes.
  • the CAN FD controller in the present example the Communication control device 21, placed in an operating state in which the CAN FD controller does not influence the CAN bus 40.
  • the res FXF bit is followed in frame 450 by a sequence BRS AD in which a predetermined bit sequence is coded.
  • This bit sequence allows a simple and reliable switchover of the arbitration bit rate
  • the bit sequence of the BRS AD consists of a recessive arbitration bit followed by a dominant data bit.
  • the bit rate can be switched on the edge between the two bits mentioned.
  • the data type identifies the content of the
  • Data field 455 with regard to what type of information is contained in data field 455.
  • additional headers or trailers are transmitted in data field 455, in addition to the actual
  • the DT field is at the beginning of the data field 455, e.g. arranged in the first byte of data field 455. Additional functions such as safety can be implemented with the DT field
  • the communication protocol is modular and can therefore be easily expanded in the future in order to insert additional functions without having to change the frame format. New additional functions can be added to old implementations using software so that the different implementations remain compatible.
  • the communication protocol used for the bus system can therefore also be expanded very flexibly.
  • a data field 455 of length 0 could be permitted, as is the case with CAN, for example.
  • the DLC field is followed in frame 450 by a header checksum H_CRC.
  • the header checksum is a checksum to secure the header of the frame 450, i.e. all bits from the beginning of the frame 450 with the SOF bit to the beginning of the header checksum H_CRC, including all dynamic and optionally the fixed stuff bits up to the beginning the header checksum H_CRC.
  • the length of the header checksum H_CRC and thus the checksum polynomial according to the cyclic redundancy check (CRC) must be selected according to the desired Hamming distance.
  • the data word to be protected by the header checksum H_CRC is longer than 27 bits with a data length code (DLC) of 11 bits. Therefore, the polynomial of the head checksum H_CRC must be at least 13 bits long in order to achieve a Hamming distance of 6.
  • DLC data length code
  • the header checksum H_CRC is followed in the frame 450 by the data field 455 (data field).
  • the data field 455 consists of 1 to n data bytes, where n is, for example, 2048 bytes or 4096 bytes or any other value. Alternatively, a data field length of 0 is conceivable.
  • the length of the data field 455 is encoded in the DLC field as previously described.
  • the DT field is optionally at the beginning of the data field 455, e.g. arranged in the first byte of data field 455.
  • the data field 455 is followed in the frame 450 by a frame checksum F_CRC.
  • the frame checksum F_CRC consists of the bits of the Framework checksum F_CRC.
  • the length of the frame checksum F_CRC and thus of the CRC polynomial must be selected according to the desired Hamming distance.
  • the frame checksum F_CRC safeguards the entire frame 450.
  • only the data field 455 is optionally secured with the frame checksum F_CRC.
  • the frame checksum F_CRC is followed in frame 450 by a sequence BRS DA in which a predetermined bit sequence is coded.
  • Bit sequence allows a simple and reliable switchover from the data bit rate of the data phase 452 to the arbitration bit rate of the arbitration phase 451.
  • the bit sequence of the BRS DA consists of a recessive data bit, followed by a dominant arbitration bit.
  • the bit rate can be switched on the edge between the two bits mentioned.
  • the sequence BRS DA is followed in frame 450 by a sync field in which a synchronization pattern (sync pattern) is held.
  • Synchronization pattern is a bit pattern that a receiving
  • Subscriber station 10, 30 allows the start of the arbitration phase 451 after the data phase 452 to be recognized.
  • the synchronization pattern allows
  • Subscriber stations send a "Negative Acknowledge" to report the incorrect reception. This is particularly important when CAN FX no longer allows error frames 47 (error flags) in data field 455.
  • the sync field is followed in the frame 450 by an acknowledgment field (ACK field) which consists of several bits, namely in the example of FIG. 2 an ACK bit, an ACK-dlm bit, a NACK bit and a NACK -dlm bit bit.
  • the NACK bit and the NACK-dlm bit are optional bits.
  • the receiving subscriber stations 10, 30 send the ACK bit as dominant if they have received a frame 450 correctly.
  • the sending subscriber station sends the ACK bit as recessive.
  • the bit originally sent to the bus 40 in the frame 450 can therefore be overwritten by the receiving subscriber stations 10, 30.
  • the ACK-dlm bit is sent as a recessive bit, which is used to separate from other fields.
  • the NACK bit and the NACK-dlm bit are used to enable a receiving subscriber station to signal incorrect reception of the frame 450 on the bus 40.
  • the function of the bits is like that of the ACK bit and the ACK-dl
  • the end field (EOF) bit sequence is used to identify the end of frame 450.
  • the end field (EOF) ensures that a number of 8 recessive bits are sent at the end of frame 450. This is a bit sequence that cannot occur within frame 450.
  • the end of the frame 450 can be reliably recognized by the subscriber stations 10, 20, 30.
  • the end field (EOF) has a length that differs depending on whether a dominant bit or a recessive bit was seen in the NACK bit. If the sending subscriber station has received the NACK bit as dominant, then the end field (EOF) has a number of 7 recessive bits. Otherwise the end field (EOF) is only 5 recessive bits long.
  • the end field (EOF) is followed in or after the frame 450
  • the interframe distance (I FS) is designed as with CAN FD in accordance with ISO11898-l: 2015.
  • the interframe distance (I FS) is a minimum of 3 bits.
  • FIG. 2 gives a specific example of the order of the divisions of the header for the frame 450.
  • the order is the
  • Subdivisions of the header can be sorted differently.
  • the DLC field can be arranged before the DT field.
  • Fig. 3 shows the basic structure of the subscriber station 10 with the
  • the communication error detection module 14 is part of the communication control device 11, more precisely its protocol control unit 111, which is also called a protocol Controller can be designated.
  • the communication control device 11 and the error detection test device 15 are part of the microcontroller 13.
  • the subscriber stations 20, 30 are constructed in a similar manner to that shown in FIG. 3, but the error detection test devices 25, 35 according to FIG. 1 are only optionally present. As an alternative or in addition, it is optionally possible for the communication error detection module 14 to be separate from the
  • Communication control device 31 and the transmitting / receiving device 32 is arranged. The same applies to the subscriber station 20. Therefore, the subscriber stations 20, 30 are not described separately.
  • the communication control device 11 is assigned to the microcontroller 13.
  • the microcontroller 13 has a central processing unit (CPU) 131.
  • an energy supply device (not shown) is usually built into the microcontroller 13, which supplies the transmitting / receiving device 12 with electrical energy.
  • the energy supply device usually supplies a voltage CAN_Supply of 5 V. However, depending on requirements, the energy supply device can supply a different voltage with a different value. Additionally or alternatively, the energy supply device can be configured as a power source.
  • the communication control device 11 is responsible for the implementation of the CAN FX functions, which were previously explained with reference to the frame 450 of FIG. 2. In addition, the communication control device 11 can implement the CAN FD functions as described above.
  • the communication control device 11 has a logic module 112 in addition to the protocol control unit 111.
  • the transmitting / receiving device 12 shown in FIG. 3 has a transmitting module (not shown) and a receiving module. Even if the transmitting / receiving device 12 is always referred to below, it is alternatively possible to have the receiving module in a separate device external to the transmitting module to be provided.
  • the transmission module and the reception module can be constructed as in a conventional transmission / reception device 22.
  • the transmitting / receiving device 12 is connected to the bus 40, more precisely its first bus core 41 for CAN_H or CAN-FX_H and its second bus core 42 for CAN_L or CAN-FX_L.
  • the transmission module of the transmission / reception device 12 sets a transmission signal TXD or TXD1
  • Communication control device 11 converts into corresponding signals CAN_H and CAN_L or CAN-FX_H and CAN-FX_L for bus wires 41, 42 and sends these signals CAN_H and CAN_L or CAN-FX_H and CAN-FX_L to the connections for CAN_H and CAN_L on bus 40.
  • the transmitting / receiving device 12 implements layer 1 of the known OSI model, that is to say the transmitting / receiving device 12 physically encodes the individual bits to be transmitted on the bus 40, for example as one
  • the receiver of the transmitting / receiving device 12 forms a received signal RXD from CAN signals received from bus 40 and forwards this to the communication control device 11.
  • the transceiver 12 with the receiver always listens to a transmission of data or messages 45, 46 on the bus 40 in normal operation, regardless of whether the subscriber station 10 or its transmitting / receiving device 12 is the sender of the message 45 or not.
  • the signals CAN-FX_H and CAN-FX_L have the dominant and recessive bus levels 401, 402, as known from CAN, at least in the arbitration phase 451.
  • a differential signal VDIFF CAN-FX_H - CAN-FX_L, which is shown in FIG. 5, is formed on bus 40.
  • the individual bits of the VDIFF signal with the bit time t_bt can be recognized with a reception threshold T_a of 0.7 V.
  • the bits of the signals CAN-FX_H and CAN-FX_L become faster, i.e. with a shorter bit time t_bt, than in the arbitration phase 451.
  • the signals CAN-FX_H and CAN-FX_L differ in the data phase 452 at least in their higher bit rate from the conventional signals CAN_H and CAN_L.
  • the bit time t_bt of the bit of the transmission signal TXD or TXD1 corresponds to the respective bits for the arbitration phase 451 and the bits for the data phase 452.
  • the sequence of states 401, 402 for signals CAN-FX_H, CAN-FX_L in FIG. 4 and the resulting profile of voltage VDI FF from FIG. 5 only serves to illustrate the function of subscriber station 10 for sending a frame 450.
  • the sequence of the data states for the bus states 401, 402 can be selected as required.
  • the transmitter module of the transmitter / receiver device 12 generates a first data state as bus state 402 with different bus levels for two bus wires 41, 42 of the bus line and a second data state as bus state 401 with the same bus level for the two in a first operating mode according to FIG Bus wires 41, 42 of the bus line of bus 40.
  • the transmission module transmits the transmission / reception device 12 for the temporal progressions of the signals CAN-FX_H, CAN-FX_L in a second
  • the bits with a higher bit rate on the bus 40 can also be generated in the data phase 452 with a different physical layer than with CAN FD. As a result, the bit rate in the data phase 452 can be increased even further than with CAN FD.
  • the protocol control unit 111 receives a send message TX from the microcontroller 13, more precisely from its central processing unit 131, if the subscriber station 10 wishes to send data to the bus 40.
  • the send message TX contains data that are to be sent to another subscriber station 10, 20, 30 of the bus system 1 via the bus 40, in particular in a frame 450 or a frame for CAN FD.
  • the protocol control unit 111 sends a to the microcontroller 13
  • Received message RX when a frame is received from the bus 40 by the transceiver 12 and from the transceiver 12 is converted as the received signal RXD. More precisely, the received message RX is sent to the central processing unit 131.
  • Received message RX contains data that were sent from another subscriber station 10, 20, 30 of bus system 1 via bus 40, in particular in a frame 450 or another frame, and from the
  • Subscriber station more precisely their transmitting / receiving device 12, were received.
  • the protocol control unit 111 compiles the data of the transmission message TX with additional control and check bits, which from the
  • the TXD signal formed in this way which is also called a transmission frame or frame, uses at least one checksum for a frame for the bus 40, which is calculated by the communication error detection module 14.
  • the at least one checksum comprises the frame checksum F_CRC described above with reference to the frame 450 and / or the above-described header checksum H_CRC and / or at least one other checksum.
  • the calculation of the at least one checksum can in principle alternatively or additionally be implemented in software that runs on the central
  • Processing unit 131 of the microcontroller 13 is executed.
  • the protocol control unit 111 extracts the control and test bits which are defined by the communication protocol for the serial transmission on the bus 40 from a received RXD signal.
  • the resulting received message RX forwards the protocol control unit 111 to the microcontroller 13.
  • the protocol control unit 111 outputs information about the transmission signal TXD to the error detection test device 15, more precisely to its first connection 1521 and / or second connection 1522.
  • Such information is, for example, a message as to when the protocol control unit 111 begins to send a frame 450 or some other frame for the bus 40 (Send_Start).
  • such information is signaling by means of a pulse or an edge per transmitted bit of the transmission signal TXD or of the frame 450 (bit pulse).
  • the error detection test device 15 signals the protocol Control unit 111 with a switching signal SJNV, when a bit of the transmission signal TXD or of the frame 450 is to be disturbed (invert bit).
  • the signaling can take place in particular by means of a third connection 156 of the device 15. This is described in more detail below.
  • the error detection test device 15 has at least one
  • Configuration register 151 at least one counter 152, an evaluation module 153, a control module 154, a logic module 155, an output connection 156 and optionally an additional output connection 157.
  • the value range of the at least one counter 152 should be at least so large that the bits of the longest possible frame 450 or of another longest possible frame transmitted via the bus 40 can be counted.
  • the at least one configuration register 151 should be just as wide as the at least one counter 152.
  • the evaluation module 153 checks whether the at least one counter 152 has a predetermined counter value.
  • Control module 154 can be configured as control logic.
  • the error detection test device 15 can be switched on or off with the control module 154.
  • the evaluation module 153 can also have software that determines, in particular, calculates which bit of a predetermined transmission signal TXD (the test frame) must be inverted so that the receivers of the disturbed test frame can check the function of a predetermined and previously described error detection mechanism .
  • the software can, however, alternatively or additionally be provided externally by the evaluation module 153, for example on an external computer (PC). In the latter example, the at least one bit can be determined with the software offline in a software tool on the PC. Independently of this, the software creates a list of test messages (test messages) with test bit positions. The list is determined once by software and generated as a list of test frames, including error bit positions.
  • the value determined or calculated by the software is then written into the at least one configuration register 151, in particular the central processing unit 131 then fetches test messages from the list and writes the corresponding check bit position into the
  • Configuration register 151 Here, depending on the desired error condition or the error mechanism to be checked, a suitable test message is selected from the list. The test message is passed on to the protocol control unit 111 in order to generate the corresponding frame from the test message. The corresponding error bit position is written into the at least one configuration register 151. In addition, the error detection test device 15 is switched on shortly before the start of transmission of the test frame or the predetermined transmission signal TXD. At the latest with a signal (Send_Start) of the control unit 111, the value of the at least one
  • Configuration register 151 are written into the at least one counter 152.
  • the signaling by means of a pulse or an edge per
  • the transmitted bit of the transmission signal TXD or of the frame 450 causes the at least one counter 152 to be incremented if the counter is an up counter, or the at least one counter 152 to be decremented if the counter is a down counter.
  • the switching signal SJNV which can interfere with a specific bit in the test frame or the predetermined transmission signal TXD, is only active for a bit time t_bt, which is shown, for example, in each of FIGS. 4 to 6.
  • the bit time t_bt can, if necessary, be subdivided into at least two time quanta TQ1 to TQN, as shown in FIG. 6, where N is any natural number> 1.
  • the at least one counter 152 from FIG. 3 is loaded with the content of the at least one configuration register 151 when the TXD signal starts to send for a frame 450 or another frame to be sent via the bus 40.
  • the at least one counter 152 is then decremented once per transmitted bit.
  • the evaluation module 153 activates the switching signal SJNV and forwards the switching signal SJNV to the logic module 112 via the logic module 155 and the connection 156.
  • the currently sent bit of the transmission signal TXD is inverted.
  • the logic module 155 can be designed as an AND gate, for example.
  • the at least one counter 152 is loaded with the counter value 0 and then incremented once per transmitted bit of the predetermined transmission signal TXD.
  • the evaluation module 153 is designed such that the switching signal SJNV is then activated in order to invert the bit of the transmission signal TXD when the at least one counter 152 accepts the value of one of the configuration registers 151.
  • the switching signal SJNV in the communication control device 11, optionally in the protocol control unit 111, can thus invert the serial data input of the output connection driver of the communication control device 11.
  • the inversion can take place in particular by means of the logic module 112, which is designed, for example, as an EXOR gate.
  • the logic module 112 is activated in time by the error detection test device 15 in such a way that a specific, selected bit of the currently transmitted transmission signal TXD from, for example, FIG. 6 is inverted for a frame 450 or another frame.
  • the error detection test device 15 works in parallel with the protocol control unit 111.
  • the bit sequence of the transmit signal TXD after activation of the switching signal SJNV, as described above, is no longer 010, but 000.
  • Other changes in the protocol control unit 111 are not necessary to correct the error mechanisms of bus system 1 to test.
  • the logic module 112 thus outputs a modified or disturbed transmission signal TXD1 to the transceiver 12.
  • the error detection test device 15 can switch itself off after the error detection test device 15 has disrupted the test frame or the predetermined transmission signal TXD by inverting at least one bit, such as previously described.
  • the signals from the protocol control unit 111 to the error detection test device 15 are already present in the protocol control unit 111. Therefore, the outlay for the signaling described above is very low.
  • the simple communication interface between the error detection test device 15 and the protocol control unit 111 also makes it possible to offer different versions of the communication interface without major changes.
  • One version cannot have any fault detection test device 15 at all.
  • Other versions may differ in the version of the error detection test device 15.
  • a great advantage of the configuration of the subscriber station 10 described above is that the protocol control unit 111, which generates or decodes frames 450 or other frames for the bus 40, not with additional ones
  • Extension of the protocol control unit 111 would, apart from the increased expenditure for the verification of the control unit 111, also significantly increase the digital circuit of the control unit 111, which is disadvantageous.
  • the reason for this is that the configuration of the functions of the device 15 must then also be taken into account by the control unit 111 in each state. This would also reduce the risk of undetected design errors in control unit 111 climb.
  • the subscriber station 10 is also designed to apply the error detection test device 15 additionally or alternatively to the received signal RXD1.
  • the subscriber station 10 can carry out a test locally, that is to say impress a bit error that only the subscriber station 10 sees.
  • the advantage is that the flexibility of the application is increased.
  • an error detection test device 15 should be used for the TX signal and an error detection test device 15 for the RX signal.
  • a receive buffer is the one received from the CAN protocol control unit
  • Messages stores also capable of or configured to store messages 45, 46 which are marked as faulty by the protocol control unit 111.
  • An evaluation of a message 45, 46 in software is thus possible and thus offers more flexibility in error handling.
  • the interference (inversion) of the TXD signal takes place outside the protocol control unit 111.
  • the logic module 112 is arranged separately from the communication control device 11, for example.
  • the logic module 112 is arranged separately between the devices 11, 12.
  • the logic module 112 is arranged in the device 12.
  • the fault detection test device 15 is configured, the central one
  • the switching signal SJNV can be provided as an interrupt source for the device 131 (CPU), in particular at an optional additional connection 157 of the error detection test device 15 Faults are not signaled by interrupt, the interrupt function should be deactivated with the activation (enable) of the error detection test device 15 until the bit in or after the test frame has been disturbed. As a result, the function of the fault detection test device 15 is then monitored in that an unintended disturbance of the transmission signal triggers an interrupt signal.
  • FIGS. 6 and 7 are also helpful for explaining the transmission signal from FIG. 8, that of a switching signal from FIG. 9 according to a second
  • Embodiment is disturbed, as explained below.
  • a bit time t_bt can be divided into at least two time quanta TQ, that is to say time quanta TQ1 to TQN, as shown in FIG. 6, where N is any natural number> 1.
  • a bit can be configured as an integer multiple N of a time quantum TQ.
  • the time quantum TQ corresponds to the time resolution with which the protocol control unit 111 works.
  • the error detection test device 15 is able to control not only the disturbance (inverting) of whole bits but also the disturbance (inverting) of parts of bits.
  • the number N of the time quanta TQ per bit with which the control unit 111 works is also known in the error detection test device 15. This can be done via
  • Evaluation module 153 take place.
  • the number N of time quanta TQ per bit is provided by the protocol control unit 111 via a status signal at the first connection 1521.
  • the information can be provided in at least one of the configuration registers 151 as to which or which time quanta TQ of the bit should be disturbed (inverted).
  • the error detection test device 15 waits for the bit to be disrupted and within the bit it generates the appropriate one for each time quantum TQ
  • Switching signal SJNV (invert signal).
  • the error detection test device 15 of the central processing device 131 (CPU) signal that a bit or a time quantum TQ of a bit has been disturbed.
  • the switching signal SJNV can be provided as an interrupt source for the device 131 (CPU), as before with reference to the preceding one
  • the error detection test device 15 contains, for example, a register 151 which, for each time quantum TQ of the bit, configures whether or not the bit should be inverted for this time quantum TQ.
  • the bit with the value 1 consists of 16 time quanta TQ.
  • FIG. 8 shows the resulting disturbed transmission signal TXD1, in which all time quanta TQ marked with 1 from FIG. 6 are inverted in comparison to the transmission signal TXD from FIG. 7.
  • FIG. 9 shows the switching signal SJNV which is output at the connection 156 in order to generate the disturbed transmission signal TXD1, as described above.
  • the described embodiment of the error detection test device 15 has the advantage that a bit in the temporal resolution of time quanta TQ can be corrupted. This means that more than just simple bit errors can be generated. For example, a (slightly) disturbed physical layer can be emulated which is disturbed due to cabling or properties and / or errors of the transmitting / receiving device 12. The robustness of the subscriber station 10 or the bus system 1 can thus be tested during operation.
  • a frame ID can be configured in one of the configuration registers 151 and / or in the evaluation module 153 of the error detection test device 15, that is to say an identifier (ID), as shown for example in FIG. 2.
  • the error detection test device 15 or the evaluation module 153 waits after the activation (enable) of the
  • the protocol control unit 111 sends a frame 450 or some other frame for the bus 40 with the configured frame ID. Only if the frame ID configured in one of the configuration registers 151 and / or in the evaluation module 153 matches the frame ID sent does the error detection test device 15 signal with the Switching signal S_INV that a bit should be disturbed (inverted). For this purpose, the protocol control unit 111 provides the frame ID of the frame just sent. This information, ie the frame ID, is available in the protocol control unit 111.
  • the error detection test device 15 waits for the frame with the matching ID, then for the bit to be disrupted and within the bit it generates the appropriate switching signal SJNV for each time quantum TQ by at least one To disturb (invert) the time quantum TQ of the bit accordingly.
  • the configuration of the error detection test device 15 has two major advantages.
  • the first advantage is that the device 131 (CPU) and / or its software does not have to activate the error detection test device 15 immediately before the test frame is sent, which reduces the time requirement for the software.
  • the second advantage is that this ensures in a simple manner that only the test frame is actually disturbed and not other frames accidentally.
  • Message handler who issues the send job to protocol control unit 111, activate error detection test device 15 when the send job for the test frame is issued. For this purpose, for example, a control bit in the memory for the test frame to be sent is evaluated.
  • This memory can be the TX memory.
  • At least one is the
  • Error detection test device 15 configurable or designed to disrupt bits after the end of a frame. This can be used, for example, to disturb the bits that are in the minimum
  • Interframe distance (I FS) according to FIG. 2 are sent.
  • the Interframe distance (IFS) can also be referred to as interframe time IFS (interframe time) or is called intermission in CAN.
  • Embodiment it is required as a precondition that a bit outside a frame may only be disturbed immediately after a test frame with a predetermined frame ID.
  • the predetermined frame ID can be configured in at least one of the configuration registers 151 and / or the evaluation module 153 of the error detection test device 15.
  • the error detection test device 15, 25, 35 can be separate from the
  • Communication methods are used in which two different communication phases are used, in which the bus states differ, which are generated for the different communication phases.
  • the invention can be used in the development of other serial communication networks, such as Ethernet and / or 100 Base-Tl Ethernet, field bus systems, etc.
  • bus system 1 can be a communication network in which data is serial with two
  • Subscriber station 10, 20, 30 is guaranteed on a common channel.
  • Bus system 1 of the exemplary embodiments is arbitrary.
  • Subscriber station 20 in bus system 1 is omitted. It is possible for one or more of the subscriber stations 10 or 30 to be present in the bus system 1. It is conceivable that all subscriber stations in the bus system 1 are configured identically, that is to say only subscriber stations 10 or only
  • Subscriber stations 30 are available.

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Abstract

L'invention concerne un dispositif de test de détection d'erreur (15 ; 25 ; 35) pour une station d'abonné (10; 20; 30) d'un système de bus série (1). Le dispositif de test de détection d'erreur (15 ; 25 ; 35) comprend un module d'évaluation (153) destiné à évaluer quel bit d'un signal (TXD ; RXD) doit être brouillé afin que les récepteurs du signal obtenu (TXD ; RXD), dans lequel ledit au moins un bit est brouillé, puissent tester la fonctionnalité d'un mécanisme de détection d'erreur prédéfini, le signal (TXD ; RXD) étant traité par une unité de contrôle de protocole (111) pendant le fonctionnement de la station d'abonné (10 ; 20 ; 30) de façon à être transmis sous forme de trame (450) à un bus (40) du système de bus (1) ou, après réception d'une trame (450) par le bus (40), de façon à décoder le signal (RXD) de la trame (450). Le dispositif de test de détection d'erreur comprend également une borne de sortie (156) pour délivrer en sortie un signal de commutation (SJNV) à l'unité de contrôle de protocole (111) afin de brouiller ledit au moins un bit évalué par le module d'évaluation (153) dans le signal (TXD ; RXD) émis par l'unité de contrôle de protocole (111), le module d'évaluation (153) étant conçu pour générer le signal de commutation (S_INV) sur la base dudit au moins un bit évalué par le module d'évaluation (153).
EP20728742.6A 2019-06-03 2020-05-27 Dispositif de test de détection d'erreur pour une station d'abonné d'un système de bus série et procédé de test de mécanismes de détection d'erreur lors d'une communication dans un système de bus série Active EP3977682B1 (fr)

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PCT/EP2020/064666 WO2020244983A1 (fr) 2019-06-03 2020-05-27 Dispositif de test de détection d'erreur pour une station d'abonné d'un système de bus série et procédé de test de mécanismes de détection d'erreur lors d'une communication dans un système de bus série

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KR20220012988A (ko) 2022-02-04
WO2020244983A1 (fr) 2020-12-10

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