Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
  • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
  • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
  • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/26—Materials of the light emitting region
  • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
  • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

• the present invention relates to an optoelectronic device comprising a substrate delimiting a support face and at least one light-emitting diode 10 formed on the support face, having a generally wire shape elongated along a longitudinal axis extending in a first direction oriented transversely to the support face. .
• the invention also relates to a method of manufacturing an optoelectronic device.
• the invention finds application in particular in display screens or image projection systems.
• optical device is meant here a device suitable for converting an electrical signal into electromagnetic radiation to be emitted, in particular light.
• optoelectronic devices comprising light-emitting diodes, also known by the acronym LED for “light-emitting diode” according to the dedicated English terminology, formed on a substrate.
• each light-emitting diode comprises an active material which may or may not use quantum wells, a semiconductor portion doped according to a first type of doping to play the role of an N-doped junction and a semiconductor portion doped according to a second type of doping to play. the role of a p-doped junction.
• optoelectronic devices comprising a matrix of light emitting diodes having a certain emission surface through which the light radiation emitted by the light emitting diodes is transmitted.
• Such optoelectronic devices can in particular be used in the constitution of display screens or image projection systems, where the matrix of light-emitting diodes in fact defines a matrix of luminous pixels where each pixel traditionally comprises at least one sub. -pixel for generating each color, each sub-pixel itself containing at least one light emitting diode.
• a sub-pixel can for example contain up to 100,000 light-emitting diodes.
• Each three-dimensional light-emitting diode can be formed on the basis of three-dimensional micrometric or even nanometric semiconductor wireframe elements, themselves at least partially obtained by growth by epitaxy such as vapor phase epitaxy with organometallics (also known by the acronyms MOVPE for " metalorganic vapor phase epitaxy ”) or as epitaxy by molecular beams (MBE for“ Molecular Beam Epitaxy ”according to the English expression) by vapor deposition of organometallics (MOCVD) or by plasma assisted deposition (PECVD).
• epitaxy such as vapor phase epitaxy with organometallics (also known by the acronyms MOVPE for " metalorganic vapor phase epitaxy ”) or as epitaxy by molecular beams (MBE for“ Molecular Beam Epitaxy ”according to the English expression) by vapor deposition of organometallics (MOCVD) or by plasma assisted deposition (PECVD).
• Light-emitting diodes are typically formed from a semiconductor material comprising, for example, elements from column III and from column V of the periodic table, such as a III-V compound, in particular gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AIGaN).
• a III-V compound in particular gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AIGaN).
• the structure of three-dimensional light-emitting diodes may be of the “core-shell” type with a first semiconductor portion doped according to a first type of doping and of wire form, an active semiconductor portion covering this first portion and a second semiconductor portion doped according to a second type. doping and covering the active portion.
• the first portion being the “heart” and the active portion and the second portion forming the “shell” since they surround the first portion.
• a second known structure is called "axial".
• the first semiconductor portion doped according to a first type of doping, the active portion and the second semiconductor portion doped according to a second type of doping are stacked in whole or in part along the longitudinal axis of the light-emitting diode.
• One of the difficulties in the axial structure is that the methods of forming the active portion and the second semiconductor portion can hardly make it possible to obtain the active portion and the second semiconductor portion only by covering the first semiconductor portion so as to be stacked along the longitudinal axis of the light-emitting diode. It A parasitic deposit results on the side faces of the wireframe form of the first portion of the light-emitting diodes. This parasitic deposit is likely to be in electrical contact with the first and second semiconductor portions and to generate leakage currents between the first and second semiconductor portions. A proportion of the current coming from the second semiconductor portion and normally intended to pass through the active portion to the first semiconductor portion passes through the external parasitic deposit and therefore does not pass through the active portion which generates a loss of electronic efficiency of the light-emitting diode.
• a known solution consists in forming one or more electron barrier layers (EBL for “Electron blocking layer” according to the English expression) after the formation of the active portion.
• EBL electron barrier layer
• the electron barrier may nevertheless be deposited in insufficient quantity on the side faces of the wire-like form of the light-emitting diodes. Thus, current leaks can still appear at locations where the electron barrier is thinner or absent.
• the object of the present invention is to respond to all or part of the problems presented above.
• one goal is to provide a solution meeting at least one of the following objectives:
• an optoelectronic device comprising a substrate delimiting a support face, at least a first light-emitting diode and a second adjacent light-emitting diode formed on the support face, the first light-emitting diode and the second light-emitting diode each comprising:
• a first semiconductor portion doped according to a first type of doping having a generally elongated wire shape along a longitudinal axis extending in a first direction oriented transversely to the support face and having lateral surfaces generally parallel to the longitudinal axis,
• an active portion arranged at least in part on a top end of the first semiconductor portion, opposite along the axis to a lower end of the first semiconductor portion facing the support face,
• a second semiconductor portion doped according to a second type of doping and arranged, at least in part, on all or part of the active portion, an electrically resistive layer, the electrical resistance of which is greater than that of the active portion, covering at least all or part of the side surfaces of the first semiconductor portion and all or part of the surface of the top end of the first semiconductor portion not covered by the active portion;
• the electrically resistive layer of the first light emitting diode and the electrically resistive layer of the second light emitting diode being separated from each other.
• the electrically resistive layer is configured so as to be able to prevent the formation of a material by epitaxy on its free surfaces.
• the electrically resistive layer is electrically insulating.
• the electrically resistive layer is transparent to all or part of the light radiation emitted by the active portion. According to a non-limiting embodiment, for each of the first and second light-emitting diodes, the electrically resistive layer does not laterally cover the active portion.
• the electrically resistive layer does not laterally cover the second semiconductor portion.
• the electrically resistive layer and the active portion cover, by continuity or overlap, the first semiconductor portion.
• the electrically resistive layer has a thickness between a lower value of a few angstroms and a higher value of about 200 nm.
• the electrically resistive layer covers all of the side surfaces of the first semiconductor portion without laterally covering the active portion, the active portion covers all of the top end of the first semiconductor portion without covering the electrically resistive layer, and the second semiconductor portion covers the upper part and the side walls of the active portion until it reaches the electrically resistive layer.
• the electrically resistive layer covers all of the side surfaces of the first semiconductor portion without laterally covering the active portion, the active portion covers all of the top end of the first semiconductor portion and all of the free surfaces of the electrically resistive layer, and the second semiconductor portion covers the top part and the side walls of the active portion.
• the electrically resistive layer covers all of the side surfaces of the first semiconductor portion without laterally covering the active portion, the active portion covers all of the top end of the first semiconductor portion without covering the electrically resistive layer, and the second semiconductor portion covers the part top and the side walls of the active portion and the free surfaces of the electrically resistive layer.
• step d) is carried out by dry etching.
• step d) is implemented by a directional etching method.
• the etching step of step d) is implemented by a first dry sub-etching not completely passing through the resistive layer electrically and by a second wet sub-etching exposing the top end of the first semiconductor portion.
• step e) is carried out by epitaxial growth.
• step f) is carried out by epitaxial growth.
• FIG. 1 shows in schematic cross section a first step of a first example of a method of manufacturing a first embodiment of an optoelectronic device according to the invention.
• FIG. 2 represents, in schematic cross section, a second step of the first exemplary manufacturing method of the first embodiment of an optoelectronic device according to the invention.
• FIG. 3 represents, in schematic cross section, a third step of the first exemplary manufacturing method of the first embodiment of an optoelectronic device according to the invention.
• FIG. 4 represents a schematic cross section of a second embodiment of an optoelectronic device according to the invention containing a light emitting diode.
• FIG. 5 illustrates a schematic cross section of a third embodiment of an optoelectronic device according to the invention containing a light emitting diode.
• FIG. 6 illustrates a schematic cross section of a fourth embodiment of an optoelectronic device according to the invention comprising at least two adjacent light emitting diodes, the respective electrically resistive layers of which are separated from one another.
• the invention relates firstly to an optoelectronic device 10, which firstly comprises a substrate 101 having a support face 101a, which is an element common to the various embodiments.
• the optoelectronic device 10 also comprises at least a first light-emitting diode 11 and a second light-emitting diode 11, adjacent to each other. These two light-emitting diodes, visible in FIG. 6, may or may not be identical, provided that they meet the characteristics described below.
• the optoelectronic device 10 can comprise a very large number of light-emitting diodes 11, for example several thousand, distributed in the general plane of the support face 101a of the substrate 101.
• Two light-emitting diodes 11 are said to be adjacent when they are located in proximity. immediate one from the other in the general plane of the support face 101a of the substrate 101.
• the second light-emitting diode 11 called “adjacent” to the first light-emitting diode 11 is the light-emitting diode closest to the first diode electroluminescent in the general plane of the support face 101a, and vice versa.
• Each of the first and second light-emitting diodes 11 is three-dimensional and has, for example, an elongated wire shape along an axis oriented transversely to the support face 101a.
• Such an organization is very advantageous for obtaining an optoelectronic device 10 with high resolution and high contrast while not generating any limitation as to materials and techniques. used for manufacture, and while conferring all the known advantages with regard to the use of such wired light-emitting diodes, in particular in terms of cost and efficiency.
• a particularly targeted application is the supply of an image display screen or an image projection device. But it is clear that the embodiments can relate to other applications, in particular the detection or measurement of electromagnetic radiations or even photovoltaic applications.
• Each of the first and second light-emitting diodes 11 comprises a first semiconductor portion 112 formed (directly by means of physical contact, or indirectly by interposition of a possible intermediate layer) on the support face 101a of the substrate 101.
• the first semiconductor portion 112 is doped according to a first type of doping, for example of N or P type, but preferably of N type.
• the first semiconductor portion 112 has a generally wire shape elongated along a longitudinal axis 11b, which extends generally parallel to a first direction 112a oriented transversely to the support face 101a.
• the shape of each light-emitting diode 11 is three-dimensional and generally wire-bound.
• generally parallel is meant that the longitudinal axis 11b and the direction 112a are collinear within 30 ⁇ m and oriented at an angle within plus or minus 10 ° between them.
• the first semiconductor portion 112 of each of the first and second light emitting diode further has side surfaces 112b generally parallel to the longitudinal axis 11b.
• Each of the first and second light-emitting diodes 11 also includes an active portion 111 arranged at least in part on the top end 11a of the first semiconductor portion 112.
• the top end 11a is the opposite end along the longitudinal axis 11b. at a lower end of the first semiconductor portion 112 facing towards the support face 101a of the substrate 101.
• the active portion 111 of the light-emitting diodes 11 is the layer, or the stack of layers, from where the majority of the radiation delivered by the light-emitting diode 11 is emitted. It may include means for confining the carriers of electric charge, such as quantum wells. It is, for example, made up of alternating layers of GaN and an InGaN alloy or alternatively an AIGalnN alloy. GaN layers can be doped. Alternatively, the active portion 111 consists of a single layer of InGaN for example.
• each of the first and second light-emitting diodes 11 comprises a second semiconductor portion 113 doped according to a second type of doping, for example of N or P type, but preferably of P type in order to be able to form with the first N-doped semiconductor portion 112 a PN junction.
• the second semiconductor portion 113 is arranged, at least in part, on all or part of the active portion 111.
• the first and second semiconductor portions 112, 113 and the active portion 111 making up the light-emitting diodes 11 may be, at least in part, formed from group IV semiconductor materials such as silicon or germanium or else mainly comprising a III-V compound, for example III-N compounds.
• group IV semiconductor materials such as silicon or germanium or else mainly comprising a III-V compound, for example III-N compounds.
• Group III include gallium, indium or aluminum.
• III-N compounds are GaN, AIN, InGaN or AlInGaN.
• Other elements of group V can also be used, for example, phosphorus, arsenic or antimony.
• the elements in compound III-V can be combined with different mole fractions.
• the light-emitting diodes 11 can equally well be formed from semiconductor materials predominantly comprising a II-VI compound.
• the dopant may be chosen, in the case of a III-V compound, from the group comprising a type P dopant of group II, for example magnesium, zinc, cadmium or mercury, a dopant of the P type of group IV, for example carbon, or an N-type dopant of group IV, for example silicon, germanium, selenium, sulfur, terbium or tin.
• a type P dopant of group II for example magnesium, zinc, cadmium or mercury
• a dopant of the P type of group IV for example carbon
• an N-type dopant of group IV for example silicon, germanium, selenium, sulfur, terbium or tin.
• Each of the first and second light-emitting diodes 11 advantageously comprises an electrically resistive layer 114, described below both in its arrangement and in its method of formation.
• the electrically resistive layer 114 can be obtained by means of, for example, techniques known to those skilled in the art, such as physical deposition (PVD for “Physical Vapor Deposition” according to the dedicated expression) or even chemical phase deposition. vapor (CVD for “Chemical Vapor Deposition” according to the English expression), or equivalent.
• PVD Physical Vapor Deposition
• CVD Chemical Vapor Deposition
• the cross section of the first and second light-emitting diodes 11 thus formed by the first and second semiconductor portions 112, 113, by the active portion 111 and by the electrically resistive layer 114, taken in any plane parallel to the general plane of the support face 101a, can have different shapes such as, for example, an oval, circular or polygonal shape (for example square, rectangular, triangular or hexagonal).
• the invention also relates to a method of manufacturing an optoelectronic device 10 having at least two light emitting diodes.
• the substrate 101 is constituted, for example, by a stack of a monolithic layer (not shown), of a lower electrode layer (not shown) which can be a conductive seed layer and of a first electrically insulating layer. (not shown).
• a monolithic layer not shown
• a lower electrode layer not shown
• Those skilled in the art may refer for example to patent application FR-A1-3053530 to implement such a substrate 101.
• the support face 101a of the substrate 101 is formed for example by the exposed face of said first electrically insulating layer.
• the monolithic layer can be formed in a semiconductor material doped or not, for example GAI2O3 or silicon or even germanium, and more particularly monocrystalline silicon. It can also be formed from sapphire or even from a III-V semiconductor material, for example GaN. It may alternatively be a silicon-on-insulator or “SOI” type substrate for “Silicon On Insulator” according to the established English terminology. Alternatively, the monolithic layer can be formed from an electrically insulating material.
• the lower electrode layer can serve as a seed layer for the growth of semiconductor portions of light emitting diodes.
• the lower electrode layer can be continuous or discontinuous.
• the material composing the lower electrode layer can be a nitride, a carbide or an arsenide or a phosphide or a boride of a transition metal from column IV, V or VI of the periodic table of the elements or a combination of these compounds.
• the lower electrode layer can be made of aluminum nitride, aluminum oxide, boron, boron nitride, titanium, titanium nitride, tantalum, tantalum nitride, hafnium, hafnium nitride, niobium, niobium nitride, zirconium, zirconium boride, zirconium nitride, silicon carbide, tantalum nitride and carbide, or magnesium nitride in the form MgxNy, where x is about 3 and y is about 2, for example magnesium nitride in the form of Mg3N2.
• the lower electrode layer can be doped and of the same type of conductivity as that of the semiconductor elements intended to grow, and have a thickness for example between 1 nm and 200 nm, preferably between 10 nm and 50 nm.
• the lower electrode layer can be composed of an alloy or of a stack of at least one material mentioned in the list above.
• Said first electrically insulating layer may include a first intermediate insulating layer which covers said lower electrode layer. It forms a growth mask allowing the growth, for example epitaxial, of the light-emitting diodes 11 from through openings opening locally on the surfaces of the lower electrode layer.
• the first intermediate insulating layer is made of at least one dielectric material such as, for example, a silicon oxide (for example S1O 2 or SiON) or a silicon nitride (for example S1 3 N 4 or SiN) or silicon oxynitride, an aluminum oxide (e.g. Al 2 O 3) or hafnium oxide (Hf0 2 for example).
• This first intermediate insulating layer can also be formed in a large gap semiconductor material such as GAIN.
• the thickness of the first intermediate insulating layer may be between 5 nm and 1 ⁇ m, preferably between 20 nm and 500 nm, for example equal to approximately 100 nm.
• Said first electrically insulating layer may further include a second electrically intermediate insulating layer (not shown) which covers the first electrodes and participates in providing electrical insulation between the first electrodes and the second electrodes already mentioned above.
• This second electrically intermediate insulating layer can also cover the growth mask formed by the first intermediate insulating layer.
• the second intermediate insulating layer can be made of a dielectric material identical to or different from that of this growth mask, such as, for example, a silicon oxide (for example S1O 2 ) or a silicon nitride (for example S1 3 N 4 or SiN) or silicon oxynitride, an aluminum oxide (e.g. Al 2 O 3) or hafnium oxide (Hf0 2 for example).
• the thickness of the second intermediate insulating layer may be between 5 nm and 1 ⁇ m, preferably between 20 nm and 500 nm, for example equal to approximately 100 nm.
• the electrically resistive layer 114 has an electrical resistance greater than that of the active portion 111, and covers at least all or part of the side surfaces 112b of the corresponding first semiconductor portion 112. On the other hand, the electrically resistive layer 114 does not laterally cover the active portion 111. In other words, the electrically resistive layer 114 does not directly or indirectly cover all or part of the lateral faces of the active portion 111.
• the electrically resistive layer 114 does not laterally cover the second semiconductor portion 113.
• the electrically resistive layer 114 and the active portion 111 cover, by continuity or overlap, the first semiconductor portion 112 so that there can be no short-circuit between the first semiconductor portion 112 and the second semiconductor portion 113.
• the second semiconductor portion 113 does not come into electrical contact with the first semiconductor portion 112. Likewise, this makes it possible to avoid short-circuits between the first semiconductor portion 112 and an element of another adjacent light emitting diode 11.
• the respective electrically resistive layers 114 of at least the first light-emitting diode 11 and the second light-emitting diode 11, adjacent to one another, have the particularity of being separated from one another.
• the space separating two adjacent light-emitting diodes 11 should not be filled with an electrically resistive layer extending at the same height as the first semiconductor portion 112 before the step of growing the active portion 111, such as described in particular in the publication US2011 / 0114915.
• the associated technical effect is that a potential parasitic deposit, occurring during the formation of the active portion 111, is thus not formed continuously between the two active portions 111 of two adjacent light-emitting diodes 11. This is to prevent short circuits between light emitting diodes 11.
• each of Figures 1 to 5 shows a single light emitting diode 11 of the optoelectronic device 10, this being purely by way of illustration. Indeed, the number of light emitting diodes 11 is, once again, not limited in itself and may be greater than several thousand.
• FIG. 6 illustrates precisely a first light-emitting diode 11 and a second light-emitting diode 11 adjacent to one another.
• the electrically resistive layers 114 form thin walls on the side surfaces 112b of the first semiconductor portions 112 of the first and second light emitting diodes 11.
• the electrically resistive layer 114 has a thickness between a lower value of a few angstroms, for example 5 angstroms, and a higher value of approximately 200 nm.
• the thickness of the electrically resistive layer 114 is between 3 nm and 50 nm, and is preferably about 20 nm.
• the electrically resistive layer 114 covers all of the side surfaces 112b of the first semiconductor portion 112 but without laterally covering the active portion 111,
• the active portion 111 covers the whole of the top end 11a of the first semiconductor portion 112 left bare or exposed beforehand but without covering the electrically resistive layer 114,
• the second semiconductor portion 113 covers the upper part and the side walls of the active portion 111 until it reaches the electrically resistive layer 114.
• the electrically resistive layer 114 in this particular case, does not cover any surface of the top end 11a of the first semiconductor portion 112. It could be otherwise in the case where the active portion 111 only partially covers the surface of the top end 11a.
• Such an arrangement of the active portion 111, only on the top end 11a and without covering the top end of the electrically resistive layer 114, can be obtained advantageously by choosing the nature of the electrically resistive layer 114, which may be potentially apt not to allow the growth of a material by epitaxy on its surface, unlike the area corresponding to the top end marked 11a. This helps build up what is known as a growth mask. This can be obtained by using materials such as S1O2, SiN, SiON or even T1O2 for the electrically resistive layer 114.
• the electrically resistive layer 114 is able to prevent epitaxial growth on its free surfaces, then, once the active portion 111 formed by epitaxy selectively on the top end 11a of the first semiconductor portion 112, the second semiconductor portion 113 obtained by epitaxy is therefore formed selectively only from the active portion 111.
• This combination of materials and this arrangement of various portions and layers advantageously make it possible to create a light-emitting diode 11 having an axial structure whose side surfaces are free from current leaks between the first and the second semiconductor portions 112, 113.
• the electric current will preferably pass through the active portion 111 which is less electrically resistive than the res layer electrically istive 114.
• the electrically resistive layer 114 has an electrical resistivity greater than 1 Ohm.m.
• the electrically resistive layer 114 is transparent to at least part of the light radiation intended to be emitted by the active portion 111. Typically, it allows more than 30% of the light emitted by the active portion 111 and which passes through it to pass.
• the electrically resistive layer 114 covers all of the side surfaces 112b of the first semiconductor portion 112 but without laterally covering the active portion 111,
• the active portion 111 covers both the entire top end 11a of the first semiconductor portion 112 left bare or exposed beforehand and all of the free surfaces (top and side) of the electrically resistive layer 114, and the second semiconductor portion 113 covers the upper part and the side walls of the active portion 111, typically until it reaches the support face 101a of the substrate 101.
• the electrically resistive layer 114 in this particular case, does not cover any surface of the top end 11a of the first semiconductor portion 112. It could be otherwise in the case where the active portion 111 only partially covers the surface of the top end 11a.
• the situation of FIG. 4 is therefore obtained for example by forming the active portion 111 on the top end 11a of the first semiconductor portion 112, left bare or exposed beforehand, as well as on the lateral and upper surfaces free of the electrically resistive layer 114, for example by epitaxy. Then the active portion 111 is covered by the second semiconductor portion 113 obtained for example by the MOVPE technique.
• the electrically resistive layer 114 is not arranged to be a mask for epitaxial growth, but it is simply arranged so as to be more electrically resistive than the active portion 111.
• the electrically resistive layer 114 is completely electrically insulating with a resistivity greater than 1 Ohm.m. The electrically resistive layer 114 does not laterally cover the active portion 111.
• the material used to form the electrically resistive layer 114 may for example be chosen from among AIN, Al2O3, T1O2, SiN, S1O2, SiO.
• the electrically resistive layer 114 allows growth of the active portion 111 on its free surfaces by an MBE technique for example.
• the second semiconductor portion 113 then only seeing the active portion 111, it can be formed over the entire free surface of the active portion 111, for example by the MBE or MOVPE techniques.
• a core-shell type structure is then obtained, the core being the first semiconductor portion 112 and the shell being the combination of the active portion 111 and of the second semiconductor portion 113.
• the electrically resistive layer 114 placed between the first semiconductor portion 112 and the active portion 111, current leaks between the first and second semiconductor portions 112, 113 are eliminated.
• the electric current will preferably pass through the active portion 111 which is less electrically resistive than the electrically resistive layer 114.
• the electrically resistive layer 114 covers all of the side surfaces 112b of the first semiconductor portion 112 but without laterally covering the active portion 111,
• the active portion 111 covers the whole of the top end 11a of the first semiconductor portion 112 left bare or exposed beforehand without covering the electrically resistive layer 114,
• the second semiconductor portion 113 covers the upper part and the side walls of the active portion 111 and the free surfaces (top and side) of the electrically resistive layer 114, typically until it reaches the support face 101a of the substrate 101.
• the electrically resistive layer 114 in this particular case, does not cover any surface of the top end 11a of the first semiconductor portion 112. It could be otherwise in the case where the active portion 111 only partially covers the surface of the top end 11a.
• the situation in FIG. 5 is therefore obtained for example by forming the active portion 111 by epitaxy according to the MBE technique selectively on the top end 11a of the first semiconductor portion 112, left bare or exposed beforehand, the resistive layer electrically 114 being arranged only on the side walls 112b of the first semiconductor portion 112 and being composed in this example of a material capable of obtaining a growth mask as described above.
• the second semiconductor portion 113 is arranged on the free surfaces (top and side) of the active portion 111 as well as on the free surfaces (side and top) of the electrically resistive layer 114.
• the electrically resistive layer 114 does not laterally cover the portion. active 111.
• each light-emitting diode 11, and therefore each first semiconductor portion 112 is electrically connected to a first electrode, typically formed in or on the substrate 101 (not shown and which may be the seed layer), continuous or not.
• a first electrode typically formed in or on the substrate 101 (not shown and which may be the seed layer), continuous or not.
• Those skilled in the art may refer to patent application FR-A1-3053530 to produce the substrate 101 containing such first electrodes.
• FIGS. 1 to 3 represent the steps of a first method of manufacturing an optoelectronic device 10 according to the invention.
• the associated technical effect is to prevent short-circuits between all or part of the adjacent light-emitting diodes 11 during parasitic lateral deposition, inevitable in reality and known to those skilled in the art of optoelectronic devices, taking place during the formation of the active portion 111, and of the second semiconductor portion 113.
• the etching carried out in step d) is directional. This is possible for example with the use of plasmas such as for example an etching by active ions (RIE for “Reactive Ion Etching” according to the English expression). Another method can be the use of chemical mechanical polishing. Another method can be the use of annealing in a dihydrogen atmosphere.
• plasmas such as for example an etching by active ions (RIE for “Reactive Ion Etching” according to the English expression).
• RIE reactive Ion Etching
• Another method can be the use of chemical mechanical polishing.
• Another method can be the use of annealing in a dihydrogen atmosphere.
• the etching carried out in step d) is a dry etching using for example a plasma.
• the etching step d) is implemented by two sub-steps: a first dry or directional sub-etching not completely crossing the electrically resistive layer 114 at the level of the top end 11a and a second wet underetching exposing the top end 11a of the first semiconductor portion 112. This advantageously makes it possible to reduce the defects present on the surface of the top end 11a of the first semiconductor portion 112 to promote the resumption of epitaxial growth of the active portion 111 on the top end 11a.

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• 2019
  • 2019-05-28 FR FR1905638A patent/FR3096834B1/fr active Active
• 2020
  • 2020-05-28 US US17/613,699 patent/US12002841B2/en active Active
  • 2020-05-28 EP EP20737521.3A patent/EP3977512A1/de active Pending
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