EP3921862A1 - Procede d'enrobage de puces - Google Patents
Procede d'enrobage de pucesInfo
- Publication number
- EP3921862A1 EP3921862A1 EP20725802.1A EP20725802A EP3921862A1 EP 3921862 A1 EP3921862 A1 EP 3921862A1 EP 20725802 A EP20725802 A EP 20725802A EP 3921862 A1 EP3921862 A1 EP 3921862A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- coating film
- chips
- photosensitive coating
- inter
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/014—Manufacture or treatment using batch processing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
Definitions
- the invention relates to a method for coating microchips transferred onto a support substrate.
- the present invention relates to a chip coating process making it possible to preserve the integrity, for example mechanical integrity, of said chips.
- the method according to the present invention is advantageously implemented to coat chips exhibiting mechanical fragility with regard to the methods known from the state of the art.
- the coating method comprises a first step (FIG. La) of assembling the chips 11 on a main face of the support substrate 10.
- the chips are assembled on the main face of the support by their rear face, opposite their face. before, and are spaced from each other by spaces, called inter-chip spaces.
- a second step, illustrated in FIG. 1b, comprises the formation of a coating film 12 for the chips, covering the front faces of said chips and the inter-chip spaces.
- the coating film may in particular comprise an epoxy composite material loaded with silica beads.
- the second step is followed by a third step intended to expose contact areas 11a at the level of the front face of the chips (figure le)
- the third step comprises, in this regard, a step of thinning and planarization of the coating film.
- This step is generally implemented in order to allow the realization of subsequent micro-manufacturing steps such as steps photolithography, deposition or even etching, or even transfer of other functional chips.
- the thinning and planarization step comprises in particular a mechanical abrasion of the coating film which, when it is completed, reaches the front face of the chips.
- the method can comprise a fourth and last step of removing the support substrate and cutting at the level of inter-chip spaces.
- the formation of the coating film generally involves heating to temperatures of the order of 150 ° C, or even 200 ° C which are not compatible with certain types of chips, among which there may be mentioned light-emitting diodes.
- organic and more generally devices made in organic electronics.
- a difference between the thermal expansion coefficients of the support substrate and of the coating film can generate, under the effect of this heating, stresses, and more particularly detachment of the chips.
- the coating films used in the process known from the state of the art are generally composites comprising a polymer matrix, usually of epoxy type, loaded with silica beads.
- a polymer matrix usually of epoxy type
- silica beads due to the presence of these beads of known mean diameter, this solution limits the reduction in size of the inter-chip space of the order of 500 ⁇ m (5 times the conventional mean diameter of the beads).
- the third step is likely to weaken, or even render inoperative, the chips when the latter have low mechanical strength.
- the chips comprise electroluminescent devices, and more particularly electroluminescent devices with microwires or nanowires as described in document [1] cited at the end of the description.
- the third step does not make it possible to keep said coating film exclusively. at the level of the inter-chip spaces and, set back from the front faces of the chips, without degrading said front faces.
- An aim of the present invention is therefore to provide a chip coating process which makes it possible to uncover the front face of the chips while preserving the integrity of the latter.
- Another aim of the present invention is to provide a method for coating chips present exclusively in an inter-chip space, and advantageously flush with or set back from the front face of said chips.
- Another object of the present invention is to provide a chip coating method for which the thermal budget is reduced compared to the method known in the art.
- Another aim of the present invention is to propose a chip coating method making it possible to reduce the inter-chip space.
- the objects of the present invention are, at least in part, achieved by a chip coating process resting, by a rear face opposite a front face, on a main face of a substrate, and separated from each other by an inter-chip space, the method comprising the following steps:
- a first photolithographic sequence which comprises a sub-step b1) of exposure, and a sub-step b2) of dissolution, said sequence leading to a partial removal of the photosensitive coating film so as to keep said film exclusively at the level of the inter-chip spaces and, advantageously flush with or set back from the front faces.
- the insolation sub-step b1) is carried out by means of radiation, in particular light radiation in the ultraviolet range.
- This exposure step depending on the tone of the photosensitive coating film (the tone may be positive or negative), makes it possible, within said film, to discriminate, in terms of solubility, the first regions, in line with the front faces, second regions overlapping the inter-chip spaces.
- step b1) is carried out so that the first regions are soluble in a given solvent, and that the second regions are resistant to the latter.
- the method according to the present invention makes it possible to discover the front faces, and to keep the photosensitive coating film only at the level of the inter-chip spaces, without applying any mechanical force to the chips.
- the method according to the present invention therefore makes it possible to preserve the mechanical integrity of the chips, and can, in this regard, be implemented to coat chips having on their surface elements (material and / or structure) having low mechanical resistance. .
- the thickness of the photosensitive coating film at the level of the inter-chip spaces is less than or equal to a height H measured between the front face and the main face.
- a height H measured between two essentially parallel faces corresponds to the shortest distance between the two faces.
- the method further comprises a step of creeping the photosensitive coating film, advantageously carried out between steps a) and b), or after step b).
- the formation of the photosensitive coating film comprises an application, under vacuum, of a dry film made of a photosensitive material, preferably by vacuum lamination.
- the formation of the coating film according to this embodiment makes it possible to fill the entire inter-chip space by limiting, or even eliminating, the formation of voids at the level of the inter-chip spaces.
- the temperatures involved of around one hundred degrees Celsius make it possible to maintain the integrity of temperature-sensitive materials (for example organic materials) as well as to limit the relative expansion when the chip and the substrate are each made of materials having a different coefficient of thermal expansion.
- the film used is preferably not loaded, in particular with silica beads (conventional photosensitive resin), it is possible to consider a narrowing of the inter-chip space.
- the formation of the photosensitive coating film comprises the spreading of a liquid material by centrifugal coating.
- the formation of the photosensitive coating film comprises spraying in the form of droplets of a liquid material.
- the photosensitive coating film has a Young's modulus of an order of magnitude of 100 to 100,000 times lower than that of the support substrate.
- the constraints liable to be imposed by the photosensitive coating film are not such as to generate detachment of the chips at the level of the main surface.
- the photosensitive coating film has a negative tone, and, at the end of step a), is of a thickness E less than or equal to a height H measured between the main face and the front face of a chip.
- a film of negative tone (negative tone) makes it possible, during the exposure of said film at the level of the inter-chip space, to crosslink said film, and consequently to keep a film that is more chemically stable at the level of the inter-chip space.
- the photosensitive coating film has a positive tone.
- the photosensitive coating film has a thickness E less than or equal to a height H measured between the main face and the front face of a chip.
- the photosensitive coating film has a thickness E greater than a height H measured between the main face and the front face of a chip.
- the sub-step b1) is executed so that at the end of the sub-step b2), the photosensitive coating film remaining at the level of the inter-chip spaces is set back relative to on the front panels.
- the method also comprises a step c) of opening contacts on the main face at the level of the inter-chip spaces.
- step c) comprises a second photolithographic sequence.
- the chips include electroluminescent devices.
- the electroluminescent devices comprise nanowires or microwires in projection with respect to the front face.
- control circuit comprises control circuits intended to interconnect the chips or as a control circuit for the chip.
- FIGS. 2a to 2d are schematic representations of the steps of a chip coating method according to a first variant of the present invention, the various views relating to this method represent the chips and / or the support substrate according to a plane of cut perpendicular to the main face of the support substrate and / or the front face of the chips, this first variant uses a photosensitive coating film of negative tone;
- FIGS. 3a to 3d are schematic representations of the steps of a chip coating method according to a second variant of the present invention, the various views relating to this method represent the chips and / or the support substrate according to a plane of cut perpendicular to the main face of the support substrate and / or the front face of the chips, this second variant uses a photosensitive coating film of positive tone;
- FIGS. 4a and 4b are schematic representations, respectively, of an exemplary embodiment of step a) and of sub-step b1) involving a photosensitive coating film of positive tone and of a thickness greater than the height H;
- FIGS. 5a and 5b are schematic representations illustrating the making of contact at the level of the inter-chip space.
- the invention relates to a method of embedding chips involving the formation of a photosensitive coating film and the implementation of a photolithography sequence for uncovering the front faces of the chips.
- This method unlike the methods known from the state of the art, does not involve mechanical abrasion of the coating film so that the mechanical integrity of the chips is preserved.
- FIGS. 2a-2d and 3a-3d represent the different steps of the chip coating process according to the present invention.
- the method comprises in particular the provision of a support substrate 100 on one face of which, called the main face 100a, rest, by their rear face 110b, chips 110 (FIGS. 2a and 3a).
- Chips 110 also include a front face 110a opposite to the rear face 110b.
- the chips 110 can be arranged on the main face 100a in a matrix fashion.
- matrix arrangement is understood to mean a mesh with N rows and M columns.
- the chips 110 may have been transferred onto the support substrate 100 collectively or individually.
- the support substrate 100 can comprise a semiconductor material, an insulating material.
- the support substrate 100 can comprise silicon on one face of which (in particular the main face 100a) microelectronic devices are formed.
- the microelectronic devices can in particular comprise control circuits intended to be interconnected with the chips 110.
- each control circuit can be paired (or interconnected) with one or more chips 110.
- the one or more chips 110 rest (s) on said control circuit.
- the arrangement of chips 110 on the main face 100a of the support substrate 100 reproduce the arrangement of the control circuits.
- the chips 110 resting on the main face 100a are distant from each other, and therefore separated from each other, by an inter-chip space 120.
- the inter-chip space formed at the level of the main face 100a and between the chips 110 is also set back with respect to the front faces 110a of said chips 110.
- said setback corresponds to a height H measured between the main face 100a and the front face 110a.
- the method according to the present invention comprises a step a) of forming a photosensitive coating film 130 covering the front faces 110a and the inter-chip space 120 (FIGS. 2b and 3b).
- photosensitive coating film is understood to mean a film on which it is possible to delimit patterns by a photolithographic sequence.
- a photolithographic sequence comprises an exposure, in particular an exposure to radiation, for example light, of specific regions through a mask, as well as a dissolution step.
- step a) of forming the photosensitive coating film 130 may in particular comprise an application, under vacuum, of a dry film made of a photosensitive material. This formation can be done by rolling, for example.
- under vacuum is meant a pressure of less than 1.10 4 Pa.
- the dry film can in particular comprise a film like "cells wide MX5000" sold by the company Dupont ®.
- the invention is however not limited to this example, and those skilled in the art will be able to select other photosensitive dry films and use them to carry out the present invention.
- This method of applying a film under vacuum is relatively compliant, and also makes it possible to limit the formation of voids (“voids” according to the English terminology).
- voids according to the English terminology.
- the photosensitive coating film faithfully follows the topology imposed by the chips 110.
- moderate heating for example at a temperature below 120 ° C., can also be imposed during application of the dry film.
- an unfilled photosensitive coating film makes it possible to consider a reduction in inter-chip spaces 120.
- step a) of forming the photosensitive coating film 130 may comprise the spreading of a photolithographic resin by centrifugal coating (“Spin coating” according to the English terminology).
- step a) of forming the photosensitive coating film 130 may comprise the spreading of a photolithographic resin by spraying (“spray coating” according to the English terminology) in the form of droplets of said spray. resin.
- spraying in the form of droplets can advantageously be replaced by the use of a doctor blade or a slot die (“slot die” according to Anglo-Saxon terminology).
- the photolithographic resin may include a negative tone resin or a positive tone resin.
- a resin of negative tone can comprise at least one of the elements chosen from: “MX5000 series” and “WBR series” sold by the company Dupont, “SINR series” sold by the company ShinEtsu, “LQ.C series” sold by the company ECSC, “THB N series” sold by the company JSR Micro, “AL-X2000 series” sold by the company AGC, “LTC9300 series” sold by the company Fujifilm, “SU8 series” sold by the company MicroChem.
- a resin of positive tone can comprise at least one of the elements chosen from: “THB P series” and “PFR IX series” sold by the company JSR Micro, “4500 series” sold by the company AZ, “TELR series” »Sold by the company TOK.
- the material forming the photosensitive coating film may have a Young's modulus of an order of magnitude of 100 to 100,000 times lower than that of the support substrate 100.
- the method according to the present invention also comprises the execution of a first photolithographic sequence b) ( Figures 2c, 2d, 3c and 3d).
- the first photolithographic sequence comprises in particular: b1) a substep of exposure to radiation R through a mask
- the first photolithographic sequence leads to a partial removal of the photosensitive coating film, in particular of the first portions 130a, so as to keep second portions 130b of said film exclusively at the level of the inter-chip spaces 120.
- the first photolithographic sequence can advantageously be carried out so that at the end of said film sequence 130, the second portions 130b are set back relative to the front faces 110a.
- the second portions 130b have a thickness less than the height H.
- the photolithographic coating film may, at the end of step a), have a thickness E less than the height H.
- FIGS. 4a and 4b are schematic representations, respectively of step a) and of sub-step b1).
- FIG. 4a illustrates in particular a step of forming a photosensitive coating film of positive tone covering the front faces 110a and the inter-chip spaces.
- the thickness of said film is greater than the height H.
- This film can be obtained by applying, under vacuum, one or more dry films so as to achieve the desired thickness.
- Sub-step b1), illustrated in FIG. 4b, can then be carried out by focusing the light radiation at the level of the first portions 130a and an upper section A of the second portions 130b (FIG. 4b) of the photosensitive coating film so that only a lower section B (interposed between the upper section A and the main face 100a) of the second portions 130b is resistant to the dissolution carried out during the sub-step b2). This result is obtained for a coating film that is both compliant and non-compliant with the surface on which it rests.
- the exposure sub-step b1) can be carried out by means of light radiation R, in particular light radiation in the ultraviolet range, projected onto the photosensitive coating film through a photolithographic mask M (FIGS. 2c and 3c ).
- This exposure step depending on the tone of the photosensitive coating film (the tone may be positive or negative), allows, within said film, to discriminate in terms of solubility of the first regions directly above the front faces, second regions overlapping the inter-chip spaces.
- step b1) is carried out so that the first regions are soluble in a given solvent, and that the second regions are resistant to the latter.
- the method according to the present invention makes it possible to uncover the front faces, and to keep the photosensitive coating film only at the level of the inter-chip spaces, without applying any mechanical force to the chips 110.
- the method according to the present invention therefore makes it possible to preserve the mechanical integrity of the chips 110, and can, in this regard, be implemented to coat chips 110 having low mechanical strength.
- a photosensitive coating film of negative tone involves during the execution of step b1) to insulate the second regions 130b so as to make the latter resistant to the dissolution of the sub-step b2 ).
- the photolithographic mask must mask the first regions 130a and allow the exposure of the second regions 130b.
- a photosensitive coating film of positive tone involves during the execution of step b1) to insulate the first regions 130a so as to make the latter sensitive to the dissolution of sub-step b2) .
- the photolithographic mask must mask the second regions 130a and allow the exposure of the first regions 130b.
- a photosensitive coating film of positive tone advantageously makes it possible to open contacts 140 on the main face 100a at the level of the inter-chip spaces 120 (FIG. 5a).
- the contact opening can in particular be performed according to a second photolithographic sequence intended to form openings 131 at the level of the second regions 130b.
- the openings 131 are in particular through and allow access to the contacts 140 on the main face 100a at the level of the inter-chip spaces 120.
- the formation of the openings can also be followed by a step of filling said openings with a metallic species, in particular copper deposited by an electrodeposition process (FIG. 5b).
- a metallic species in particular copper deposited by an electrodeposition process (FIG. 5b).
- the method can also include at least one step of creeping the photosensitive coating film.
- creep is understood to mean a heat treatment which comprises a rise in temperature, in particular at a temperature above the glass transition temperature of the material considered.
- This creep step can be carried out immediately after step a).
- the creep step can be performed after step b). Under these conditions, the creep step makes it possible to correct faults liable to appear after step b). These defects can in particular be due to a bad dimensioning of the photolithographic mask M or to its bad alignment.
- the method makes it possible to fully discover the front face of the chips in order to carry out subsequent steps at said faces.
- the process is therefore particularly suitable for coating chips comprising electroluminescent devices at their front face.
- the electroluminescent devices may be electroluminescent devices with nanowires or microwires in projection relative to the front face, such as those described in document [1] cited at the end of the description.
- the chips each comprise, on their front face, a matrix of GaN nanowires pixels of micrometric diameter and of approximate height of 10 ⁇ m.
- Each chip can be hybridized, by an interconnection layer with a thickness of about 15 ⁇ m on the main face of the support substrate.
- the hybridization is carried out at the level of a control circuit (for example a CMOS control circuit) formed on the main face of the support substrate.
- a control circuit for example a CMOS control circuit
- the chips can be square in shape with the side measuring about 21.2mm, and arranged on the front face in a pitch of 22mm (in other words, the inter-chip space measures about 800pm).
- step a) Two photosensitive dry films of negative polarity ( "MX5000 cells wide” sold by DuPont ®) and 15 micrometer thick, are successively applied by vacuum lamination, on the front and space inter chip. This implementation of step a) makes it possible to limit, or even avoid, the presence of voids.
- Step b1) comprises exposure, for example with ultraviolet radiation, of the second regions.
- Step b2) comprises dissolving the first regions with a chemical solution which comprises 0.75% K2CO3.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Materials For Photolithography (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1902486A FR3093861B1 (fr) | 2019-03-12 | 2019-03-12 | Procédé d’enrobage de puces |
| PCT/FR2020/050410 WO2020183090A1 (fr) | 2019-03-12 | 2020-03-02 | Procede d'enrobage de puces |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP3921862A1 true EP3921862A1 (fr) | 2021-12-15 |
Family
ID=67107845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP20725802.1A Pending EP3921862A1 (fr) | 2019-03-12 | 2020-03-02 | Procede d'enrobage de puces |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11955585B2 (fr) |
| EP (1) | EP3921862A1 (fr) |
| FR (1) | FR3093861B1 (fr) |
| TW (1) | TWI884144B (fr) |
| WO (1) | WO2020183090A1 (fr) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8507320B2 (en) * | 2008-03-18 | 2013-08-13 | Infineon Technologies Ag | Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof |
| US8470641B2 (en) * | 2009-12-17 | 2013-06-25 | Texas Instruments Incorporated | Exposed mold |
| US9508623B2 (en) | 2014-06-08 | 2016-11-29 | UTAC Headquarters Pte. Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
| JP6056844B2 (ja) * | 2014-12-26 | 2017-01-11 | 大日本印刷株式会社 | カラーフィルタ用色材分散液、カラーフィルタ用着色樹脂組成物、色材、カラーフィルタ、液晶表示装置及び発光表示装置 |
| FR3031242B1 (fr) | 2014-12-29 | 2016-12-30 | Aledia | Procede de fabrication de nanofils ou de microfils semiconducteurs a pieds isoles |
| JPWO2016203967A1 (ja) * | 2015-06-15 | 2018-03-29 | ソニー株式会社 | 半導体装置、電子機器、並びに製造方法 |
| CN106887488B (zh) * | 2015-12-15 | 2019-06-11 | 群创光电股份有限公司 | 发光二极管及使用此发光二极管所制得的显示装置 |
| FR3053530B1 (fr) | 2016-06-30 | 2018-07-27 | Aledia | Dispositif optoelectronique a pixels a contraste et luminance ameliores |
| JP2018067659A (ja) * | 2016-10-20 | 2018-04-26 | 日立化成株式会社 | 半導体装置の製造方法 |
-
2019
- 2019-03-12 FR FR1902486A patent/FR3093861B1/fr active Active
-
2020
- 2020-03-02 US US17/435,102 patent/US11955585B2/en active Active
- 2020-03-02 EP EP20725802.1A patent/EP3921862A1/fr active Pending
- 2020-03-02 WO PCT/FR2020/050410 patent/WO2020183090A1/fr not_active Ceased
- 2020-03-10 TW TW109107858A patent/TWI884144B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| US11955585B2 (en) | 2024-04-09 |
| TW202105538A (zh) | 2021-02-01 |
| US20220149245A1 (en) | 2022-05-12 |
| TWI884144B (zh) | 2025-05-21 |
| WO2020183090A1 (fr) | 2020-09-17 |
| FR3093861B1 (fr) | 2021-09-17 |
| FR3093861A1 (fr) | 2020-09-18 |
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