EP3915139A1 - Procede de fabrication d'une structure - Google Patents
Procede de fabrication d'une structureInfo
- Publication number
- EP3915139A1 EP3915139A1 EP20726189.2A EP20726189A EP3915139A1 EP 3915139 A1 EP3915139 A1 EP 3915139A1 EP 20726189 A EP20726189 A EP 20726189A EP 3915139 A1 EP3915139 A1 EP 3915139A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- face
- passivation layer
- front face
- compound
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/221—Structures or relative sizes
- H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/231—Shapes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
- H10W72/387—Flow barriers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- the present invention relates to a method of manufacturing a structure, and in particular a method of encapsulating an interconnection space interposed between an active element and a support to which said element is assembled.
- Three-dimensional integration (“three-dimensional integration” according to Anglo-Saxon terminology), well known to those skilled in the art, has allowed many technological advances, in particular, for improving performance and increasing the density of microelectronic and / or optronic devices.
- 3D integration makes it possible in particular to reduce the lengths of interconnections, and consequently their density, without necessarily reducing their lateral dimensions.
- This technology can involve the formation of VIAs, interconnection bumps (“Bump” according to Anglo-Saxon terminology), thinning of substrates, assembly of substrates or active elements, as well as encapsulation. .
- encapsulation by an adhesive can be implemented to reinforce the mechanical strength and the reliability of an assembly comprising an active element placed on a support.
- the support performs a mechanical function but can also include CMOS functions for integrating CMOS or detection functions (of the active element) with the CMOS functions of said support.
- Encapsulation also makes it possible to limit contamination at the assembly interface.
- an encapsulation process illustrated in FIG. 1 and known from the state of the art, comprises the following steps: al) a step of providing an active element 10 provided with a front face 11 and a rear face 12, mutually parallel and connected by a contour 13;
- Step c) is generally carried out by causing the adhesive to flow by capillary action in the interconnection space.
- the adhesive when it spreads by capillary action, the adhesive creates a meniscus M (FIG. 2) which covers, at least partially, the contour 13.
- This meniscus generates mechanical stresses liable to put under tension the interconnections formed by the interconnection pads as well as the active element 10, and ultimately, to cause a breakage, by peeling, of the assembly formed by the active element and the support.
- the active element 10 may comprise, from its front face 11 towards its rear face 12, an active layer 10a formed on a handle layer 10b intended to be removed at the end of step c1) (FIG. 2 and 3).
- the active layer 10a can comprise any type of device.
- the active layer 10a can comprise at least one of the elements chosen from: an electronic device, a micro-electronic device, an optoelectronic device, a micro electromechanical system (“MEMS” according to Anglo-Saxon terminology).
- MEMS micro electromechanical system
- the active layer 10a can, in particular, comprise one or more electroluminescent structures, for example in the form of nanowires or microwires as described in document [1] cited at the end of the description. Additional manufacturing steps can then be implemented at the level of the active layer 10a thus discovered.
- These additional manufacturing steps can in particular comprise the formation of color filters involving at least one photolithography step.
- the step of removing the handle layer generally carried out by chemical etching or by chemical mechanical polishing (“CMP” or “Chemical Mechanical Polishing” according to Anglo-Saxon terminology), leaves the meniscus M intact so that the topology associated with the latter makes any photolithography step impossible (FIG. 3).
- CMP chemical mechanical polishing
- the capillary force intended to activate the flow of the adhesive between the front face 11 and the main face 21 is no longer sufficient so that the filling is incomplete, and lets appear bubbles (“voids” according to Anglo-Saxon terminology) (FIG. 4).
- the method proposed in document [2] does not seem to be suitable for preventing, or at the very least limiting, the covering, by the meniscus, of the contour of the active element.
- An aim of the present invention is therefore to provide an encapsulation method at the level of an assembly interface for which the overlap of the outline of the active element by the meniscus is reduced compared to the known methods of the state of. the technique.
- Another aim of the present invention is to provide an encapsulation method at the assembly interface level for which the time constraints are less severe with regard to the method described in document [2] cited at the end of the section. description.
- Another aim of the present invention is to provide an encapsulation process for which the filling with the adhesive between the front face and the main face is complete and without coating bubbles.
- the aims of the present invention are, at least in part, achieved by a method of manufacturing a structure comprising the following steps:
- the method being remarkable in that it further comprises a step b), carried out before step c), of forming, by a method other than a plasma method, a first passivation layer covering the contour, and made of a first compound making it possible to limit the wetting of said contour by the adhesive with regard to the front face and the main face.
- an interface capable of being formed between the adhesive and the first passivation layer has an interface energy greater than that of a interface capable of being formed between said adhesive and the contour without a first passivation layer.
- the first passivation layer limits the glue covering the contour.
- the glue preferably wets the front face and the main face.
- step b) begins with a masking of the front face and ends with a removal of the masking of said face.
- the masking makes it possible to keep the front face intact, and thus to preserve its wettability by the adhesive. More particularly, the masking makes it possible to avoid contamination of the interconnection pads by the first passivation layer.
- the first passivation layer is also formed on the rear face.
- the first passivation layer comprises a self-assembled single layer of the first compound.
- the first compound comprises a linear aliphatic chain provided with at least 6 carbon atoms.
- the aliphatic chain comprises one or more fluorine substituents.
- the fluorine substituent makes it possible to increase the interface energy of an interface capable of being formed between the first passivation layer and the adhesive.
- the aliphatic chain is terminated at one of these ends with a silane function.
- the silane function comprises one, two or three chlorine substituents, advantageously, the first compound comprises perfluorodecyltrichlorosilane.
- the method further comprises a step d), executed before step e), of forming a second passivation layer, by a method other than a plasma method, on the front face and the main face, and made of a second compound configured so that the interface energy between the glue and the second passivation layer is less than the interface energy between the adhesive and the front and main faces devoid of said second passivation layer.
- the second passivation layer improves the wettability of the front face and of the main face by the adhesive, and thus makes it possible to consider an active element having a large surface area, in particular greater than 1 cm 2 , or even greater than 2 cm 2 .
- the second passivation layer is formed according to a vapor phase process after step c).
- the second passivation layer comprises a self-assembled single layer of the second compound.
- the second compound comprises a linear aliphatic chain terminated at one of these ends with an epoxy function if the adhesive is epoxy-based, with an amine function if the adhesive is amine-based.
- the other end of the aliphatic chain of the second compound is terminated by a silane function.
- the second compound comprises epoxybutyltrimethoxysilane.
- the active element comprises, from its front face towards its rear face, an active layer and a handle layer.
- step e) is followed by a step f) of removing the handle layer so as to expose the active layer.
- the action layer comprises at least one electroluminescent structure, and in particular electroluminescent nanowires or microwires.
- FIG. 1 is a schematic representation of the various steps of an encapsulation method known from the state of the art, in particular the support and the active element are shown in a section plane perpendicular to the front face;
- FIG. 2 is a representation of the assembly obtained at the end of step c1) according to a section plane perpendicular to the front face;
- Figure 3 is a representation of the assembly of Figure 2 after removal of the handle layer
- FIG. 4 is an image by acoustic microscopy (“SAM” or “Scanning Acoustic Microscopy” according to Anglo-Saxon terminology), seen from the rear face, of the assembly formed by the active element and the support, and revealing defects, especially bubbles, in filling;
- SAM acoustic microscopy
- FIGS. 5a, 5b, 5c, 5d, 5e, 5f and 5g are schematic representations of the various steps that can be implemented during the execution of the method according to the present invention.
- FIGS. 6a and 6b are schematic representations of steps capable of being implemented during the execution of the method according to the present invention, and notably involving the removal of a handle layer.
- the present invention relates to a method of encapsulation by a glue of an interconnection space interposed between an active element and a support to which said element is assembled.
- the present invention uses a first passivation layer formed, by a method other than a plasma process, at least on one contour of the active element so as to limit the wetting of said contour by the adhesive, and thus preventing the contour from being covered by a meniscus of adhesive forming near said contour.
- FIGS. 5a to 5g are schematic representations of the various steps of the manufacturing process according to the present invention.
- the method comprises in particular a step of providing an active element 100 which comprises two essentially parallel faces called, respectively, the front face 110 and the rear face 120 (FIG. 5a).
- the front face 110 and the rear face 120 are moreover connected by a contour 130.
- the active element may include an electronic device, or an optoelectronic device, or an optical device.
- the device in an example which will be detailed in the remainder of the statement, can comprise from its front face 110 towards its rear face 120 an active layer formed on a handle layer.
- the handle layer can comprise a semiconductor material, in particular silicon.
- the method also comprises a step b) of forming a first passivation layer 140 on the contour 130 and possibly on the rear face 120 (FIG. 5c).
- Step b) can begin with a masking 150 (FIG. 5b) of the front face 110 and end with a removal of said masking (FIG. 5d).
- the method also comprises a step c) of assembling the front face 110 with a main face 210 of a support (FIG. 5e).
- the support 200 may include, in projection with respect to the main face 210, interconnection pads 300.
- the active element 100 can comprise metal studs or metal bosses 310 (“UBM” or “under bump metallurgy” according to the English terminology), in projection with respect to the front face 110, and in correspondence with the studs d 'interconnection 300 (or other bosses) so that contact is established, during assembly, between each stud and the metal boss facing it.
- UBM metal studs or metal bosses 310
- the interconnection pads can comprise copper pillars, indium or indium alloy, tin or tin alloy balls, and micro tubes.
- 450,000 pads 300, 20 ⁇ m in height and at a pitch of 30 ⁇ m, are formed on a main face 210 of 4 cm 2 .
- the pads 300 include in particular a stack of copper, nickel and a tin silver alloy (SnAg).
- metal bosses 310 comprising an alloy of titanium and nickel as well as gold, are formed on a front face 110 of 4 cm 2 , and according to an arrangement making it possible to establish an electrical contact between pads. and bosses.
- the melting of the SnAg alloy of the pads 300 makes it possible to wet the metal bosses and to establish the electrical connections between each pad 300 and the boss 310 facing it.
- interconnection pads 300 and the metal bosses 310 projecting, respectively, relative to the main face 210 and the front face 110 provide an interconnection space 400 between said faces at the end of step c).
- This interconnection space 400 is then filled with an adhesive 500 (step e)).
- the glue 500 is in particular deposited, for example using a needle 600, near the contour 130, on the main face 210, and spreads by capillary action in the interconnection space between the interconnection pads 300 and the metal bosses 310.
- the first passivation layer 140 is made of a first compound making it possible to limit the wetting of the contour 130 by the adhesive 500 with regard to the front face 110 and the main face 210.
- an interface capable of being formed between the glue 500 and the first passivation layer has an interface energy greater than that of an interface capable of being formed between said glue 500 and the contour 130 without first passivation layer.
- the first passivation layer limits the coverage of the contour by the adhesive meniscus 500.
- the first passivation layer comprises a self-assembled single layer of the first compound.
- the first compound may comprise a linear aliphatic chain having at least 6 carbon atoms. This aliphatic chain can comprise one or more fluorine substituents.
- the aliphatic chain of the first compound can be terminated at one of these ends with a silane function.
- the silane function can comprise one, two or three chlorine substituents.
- the first compound comprises perfluorodecyltrichlorosilane (FDTS).
- first passivation layer and in particular of a layer made from FDTS, calls upon techniques known to those skilled in the art which are described in document [3] cited at the end of the description.
- thermally resistant layers are not affected by the heating that may be imposed during step c).
- the method according to the present invention can also comprise a step d), carried out before step e), of forming a second passivation layer 160 on the front face 110 and on the main face 210.
- the second passivation layer formed by a method other than a plasma process, is made of a second compound configured so that the interface energy between the glue 500 and the second passivation layer 160 is less than the energy interface between the adhesive 500 and the front 110 and main faces 210 devoid of said second passivation layer 160.
- the second passivation layer 160 makes it possible to improve the wetting by the glue of the front face 110 and of the main face 210, and consequently to promote the capillary flow of the glue 500 in the space of. interconnections 400.
- the implementation of the second passivation layer 160 also makes it possible to consider an active element 100 with a large surface area, and in particular having an area of between 1 cm 2 and 4 cm 2 , or even greater than 4 cm 2 .
- the second passivation layer 160 can be formed according to a vapor phase process after step c).
- the second passivation layer 160 may comprise a self-assembled monolayer of the second compound.
- the second compound can comprise a linear aliphatic chain terminated at one of these ends by an epoxy function if the adhesive is epoxy-based, by an amine function if the adhesive is amine-based.
- the other end of the aliphatic chain of the second compound can be terminated by a silane function.
- the second compound comprises epoxybutyltrimethoxysilane (EBTMOS).
- Such a compound makes it possible to considerably reduce the drop angle of the adhesive 500 on the front face and the main face, and therefore to improve the wettability of said surfaces by the adhesive 500.
- the table gives the drop angle (in "°") for different types of epoxy adhesives on a surface covered with a layer of EBTMOS, and on the same surface not. covered with a layer of EBTMOS.
- the wetting of the first passivation layer by the second element is very unfavorable so that no masking of the first layer is necessary during the formation of the second layer 160.
- the combined implementation of the first passivation layer 140 and of the second passivation layer 160 also makes it possible to simplify the manufacturing process according to the present invention.
- the active element 100 can comprise, from its front face 110 towards its rear face 120, an active layer 100a and a handle layer 100b intended to be removed during a step f), at the end of of step e), so as to expose the active layer 100a ( Figures 6a and 6b).
- the active layer 100a can comprise any type of device.
- the active layer 10a can comprise at least one of the elements chosen from: an electronic device, a micro-electronic device, an optoelectronic device, a micro electromechanical system (“MEMS” according to Anglo-Saxon terminology).
- MEMS micro electromechanical system
- the active layer 100a can comprise at least one electroluminescent structure.
- the electroluminescent structure can comprise nanowires or microwires such as those described in document [1] cited at the end of the description.
- the method according to the present invention makes it possible to prevent any topology induced by the meniscus at the end of the step of removing the handle layer 100b.
Landscapes
- Micromachines (AREA)
- Electroluminescent Light Sources (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1903041A FR3094561B1 (fr) | 2019-03-25 | 2019-03-25 | Procédé de fabrication d’une structure |
| PCT/FR2020/050531 WO2020193903A1 (fr) | 2019-03-25 | 2020-03-13 | Procede de fabrication d'une structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP3915139A1 true EP3915139A1 (fr) | 2021-12-01 |
Family
ID=67441395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP20726189.2A Pending EP3915139A1 (fr) | 2019-03-25 | 2020-03-13 | Procede de fabrication d'une structure |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US12107069B2 (fr) |
| EP (1) | EP3915139A1 (fr) |
| FR (1) | FR3094561B1 (fr) |
| TW (1) | TWI840537B (fr) |
| WO (1) | WO2020193903A1 (fr) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7952155B2 (en) * | 2007-02-20 | 2011-05-31 | Micron Technology, Inc. | Reduced edge effect from recesses in imagers |
| CN101960578B (zh) * | 2008-04-18 | 2013-01-02 | 松下电器产业株式会社 | 倒装芯片安装方法和倒装芯片安装装置及其所使用的工具保护膜 |
| US9064881B2 (en) | 2010-11-11 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting flip-chip package using pre-applied fillet |
| US8945983B2 (en) | 2012-12-28 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method to improve package and 3DIC yield in underfill process |
| CN106457758B (zh) * | 2014-04-09 | 2018-11-16 | 康宁股份有限公司 | 装置改性的基材制品及其制备方法 |
| JP6684273B2 (ja) * | 2014-06-19 | 2020-04-22 | インクロン オサケユキチュアInkron Oy | シロキサン粒子材料を用いたledランプ |
| CN106415826A (zh) * | 2014-06-26 | 2017-02-15 | 索尼公司 | 半导体器件和制造半导体器件的方法 |
| FR3047604B1 (fr) | 2016-02-04 | 2018-02-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Dispositif electronique hybride protege contre l'humidite et procede de protection contre l'humidite d'un dispositif electronique hybride |
| FR3053530B1 (fr) | 2016-06-30 | 2018-07-27 | Aledia | Dispositif optoelectronique a pixels a contraste et luminance ameliores |
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2019
- 2019-03-25 FR FR1903041A patent/FR3094561B1/fr active Active
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2020
- 2020-03-13 US US17/441,879 patent/US12107069B2/en active Active
- 2020-03-13 WO PCT/FR2020/050531 patent/WO2020193903A1/fr not_active Ceased
- 2020-03-13 EP EP20726189.2A patent/EP3915139A1/fr active Pending
- 2020-03-24 TW TW109109812A patent/TWI840537B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| FR3094561A1 (fr) | 2020-10-02 |
| WO2020193903A1 (fr) | 2020-10-01 |
| TW202040705A (zh) | 2020-11-01 |
| US12107069B2 (en) | 2024-10-01 |
| US20220189910A1 (en) | 2022-06-16 |
| TWI840537B (zh) | 2024-05-01 |
| FR3094561B1 (fr) | 2022-08-26 |
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