EP3881349A1 - Dépôt sélectif de siliciures métalliques et élimination sélective d'oxyde - Google Patents

Dépôt sélectif de siliciures métalliques et élimination sélective d'oxyde

Info

Publication number
EP3881349A1
EP3881349A1 EP19884016.7A EP19884016A EP3881349A1 EP 3881349 A1 EP3881349 A1 EP 3881349A1 EP 19884016 A EP19884016 A EP 19884016A EP 3881349 A1 EP3881349 A1 EP 3881349A1
Authority
EP
European Patent Office
Prior art keywords
substrate
exposing
dosage
precursor
mosi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19884016.7A
Other languages
German (de)
English (en)
Other versions
EP3881349A4 (fr
Inventor
Raymond Hung
Namsung Kim
Srinivas D. Nemani
Ellie Y. Yieh
Jong Choi
Christopher AHLES
Andrew Kummel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
University of California
Original Assignee
Applied Materials Inc
University of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/189,429 external-priority patent/US10586707B2/en
Application filed by Applied Materials Inc, University of California filed Critical Applied Materials Inc
Publication of EP3881349A1 publication Critical patent/EP3881349A1/fr
Publication of EP3881349A4 publication Critical patent/EP3881349A4/fr
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0209Pretreatment of the material to be coated by heating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0236Pretreatment of the material to be coated by cleaning or etching by etching with a reactive gas
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0245Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42Silicides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536Use of plasma, radiation or electromagnetic fields
    • C23C16/45542Plasma being used non-continuously during the ALD reactions
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45553Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • Embodiments of the present disclosure generally relate to methods for metal silicide deposition and selective native silicon oxide etching.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • native oxide materials are to be removed in order to expose underlying materials for selective deposition thereupon.
  • native oxide removal becomes increasingly complex and selectivity is difficult when other oxide materials in addition to native oxide materials exist on substrate.
  • a substrate processing method includes heating a substrate having a silicon containing surface to a first temperature, exposing the substrate to a plasma comprising hydrogen, exposing the substrate to a first dosage of a MoF 6 precursor, and exposing the substrate to a second dosage of a Si 2 H 6 precursor The exposing the substrate to a first dosage and the exposing the substrate to a second dosage is sequentially cycled and after the sequential cycling, the substrate is exposed to a third dosage of the Si 2 H 6 precursor.
  • a substrate processing method includes positioning a substrate on a heater in a reaction chamber having chamber walls, heating the substrate on the heater to a first temperature, maintaining the chamber walls at a second temperature less than the first temperature, and exposing a silicon containing surface of the substrate to hydrogen.
  • the substrate is exposed to a first dosage of a MoF 6 precursor, the substrate is exposed to a second dosage of a Si 2 H 6 precursor, the exposing the substrate to a first dosage and the exposing the substrate to a second dosage is sequentially cycled, and after the sequential cycling, the substrate is exposed to a third dosage of the Si 2 H 6 precursor.
  • a substrate processing method includes heating a substrate to a first temperature, exposing a silicon containing surface of the substrate to a hydrogen containing plasma, exposing the substrate to a first dosage of a MoF 6 precursor, and exposing the substrate to a second dosage of a Si 2 H 6 precursor.
  • the exposing the substrate to a first dosage and the exposing the substrate to a second dosage is sequentially cycled, after the sequential cycling, the substrate is exposed to a third dosage of the Si 2 H 6 precursor, and the substrate is annealed after the exposing the substrate to a third dosage at a second temperature of between about 500°C and about 550°C.
  • Figure 1A illustrates X-ray photoelectron spectroscopy (XPS) data of MoSi x film selectivity on a silicon substrate according to an embodiment described herein.
  • XPS X-ray photoelectron spectroscopy
  • Figure 1 B illustrate XPS data of MoSi x film selectivity on a silicon oxynitride substrate according to an embodiment described herein.
  • Figure 2A illustrates XPS oxidation state data of Si and Mo on a silicon substrate according to an embodiment described herein.
  • Figure 2B illustrates XPS oxidation state data of Si and Mo on a silicon substrate according to an embodiment described herein.
  • Figure 3A illustrates XPS chemical composition data of various elements present on different substrate types prior to ALD processing according to an embodiment described herein.
  • Figure 3B illustrates XPS chemical composition data of various elements present on different substrate types after 5 ALD cycles according to an embodiment described herein.
  • Figure 3C illustrates XPS chemical composition data of various elements present on different substrate types after additional ALD cycles according to an embodiment described herein.
  • Figure 4A illustrates XPS chemical composition data of various elements present on different substrate types prior to ALD processing according to an embodiment described herein.
  • Figure 4B illustrates XPS chemical composition data of various elements present on different substrate types after 5 ALD cycles according to an embodiment described herein.
  • Figure 4C illustrates XPS chemical composition data of the substrates of Figure 4B after an annealing process according to an embodiment described herein.
  • Figure 5A illustrates XPS depth profiling data of a MoSi x film after Ar sputtering according to an embodiment described herein.
  • Figure 5B illustrates XPS chemical composition data of the MoSi x film according to an embodiment described herein.
  • Figure 5C illustrates data representative of the chemical composition of the MoSi x film versus time according to an embodiment described herein.
  • Figure 6A illustrates XPS depth profiling data of a MoSi x film after Ar sputtering according to an embodiment described herein.
  • Figure 6B illustrates surface composition data of a MoSi x film according to an embodiment described herein.
  • Figure 6C illustrates bulk composition data of the MoSi x film of Figure 6B according to an embodiment described herein.
  • Figure 6D illustrates data representative of the chemical composition of the MoSi x film versus time according to an embodiment described herein.
  • Figure 7 is a cross-sectional tunneling electron micrograph (TEM) of a MoSi x film selectively deposited on silicon preferentially to other material present on the substrate according to an embodiment described herein.
  • TEM tunneling electron micrograph
  • Figure 8 is a graph illustrating selective etching of native silicon oxide to bulk silicon oxide according to an embodiment described herein.
  • Figure 9 is a cross-sectional schematic illustration of a portion of a contact structure according to an embodiment described herein.
  • Embodiments described herein include methods which utilize substrate-dependent reactivity of ALD precursors for area-selective deposition. More specifically, embodiments of the disclosure relate to selective deposition of MoSi x on Si preferentially to SiO 2 , SiON and SiNx using substrate selectivity of MoF 6 and Si 2 H 6 . To achieve a stoichiometric M0S12 film, additional Si incorporation into the film after the MoF 6 and Si 2 H 6 ALD cycles was performed by dosing Si 2 H 6 onto a Mo rich MoSi x film. Methods described herein also provide for selective native oxide removal which enables removal of native oxide material without etching bulk oxide materials.
  • X-Ray photoelectron spectroscopy revealed that 5 ALD cycles of MoF 6 and Si 2 H 6 selectively deposited a sub-stoichiometric M0S12 film on the Si substrate.
  • the MoF 6 and Si 2 H 6 precursors were sequentially cycled in a repeating manner with a purge between each successive precursor exposure. Additional Si 2 H 6 doses on the sub- stoichiometric MoSi 2 film incorporated more Si into the film without disturbing the deposition selectivity over SiO 2 and SiNx.
  • a bulk of the MoSi x film has a ratio of Si:Mo between about 1.7 and about 1.9 with less than about 10% F and 0 impurities.
  • Embodiments described herein are believed to be advantageous over conventional high pressure Si ALD cycles for the formation of silicide materials, for example, in the formation of source/drain contact structures.
  • SiON silicon oxynitride
  • S13N4 silicon oxynitride
  • the substrates were diced into 12 mm x 3 mm pieces and degreased with acetone, methanol, and deionized (Dl) H 2 O.
  • the native oxide on Si was removed by immersing the degreased substrates into a 0.5% HF(aq) solution for 30 seconds.
  • the SiO 2 , SiON, and patterned substrates were subjected to the same cleaning procedure.
  • the native oxide removal process is the SICONI® pre-clean process available from Applied Materials, Inc., Santa Clara, CA.
  • a plasma based native oxide removal process may be utilized.
  • an NF 3 /H2 and/or NF3/NH3 plasma cleaning process may be utilized to clean and hydrogen terminate a silicon containing surface of the substrates.
  • the NF 3 plasma treatment is believed to prevent or substantially reduce deposition selectivity loss by passivating active hydroxyl nucleation sites.
  • Figure 8 is a graph 800 illustrating selective etching rates of native silicon oxide and bulk silicon oxide thicknesses as a function of time during plasma processing.
  • Data 802 is representative of bulk silicon oxide thickness when exposed to an NF 3 /NH 3 plasma.
  • Data 804 is representative of native silicon oxide thickness when exposed to the NF 3 /NH 3 plasma.
  • Time 806 is representative of when the NF 3 /NH 3 plasma is turned on and time 808 is representative of when the NF 3 /NH 3 plasma is turned off.
  • the plasma for selective etching of the native silicon oxide selectively to the bulk silicon oxide is formed in-situ in a processing chamber.
  • the plasma for selective etching of the native silicon oxide selectively to the bulk silicon oxide is formed remotely, for example, by a remote plasma source, before delivery to the processing chamber.
  • Precursors utilized to form the plasma include NF 3 and NHs.
  • an inert carrier gas, such as Ar, is utilized to facilitate delivery of active species to the substrate for selective removal of the native silicon oxide.
  • a ratio of NF 3 :NH 3 is between about 1 :5 and about 1 :20, such as about 1 :10.
  • the Ar is provided in an amount greater than the NF 3 but less than the NH 3 .
  • a ratio of NF 3 :NH 3 :Ar is 1 :10:1.5.
  • a pressure of the process chamber environment within which the selective native oxide removal process is performed is between about 10 mTorr and about 1 ,000 mTorr, such as between about 100 mTorr and about 500 mTorr, for example, about 200 mTorr. In one embodiment, the pressure is about 190 mTorr.
  • a power utilized to generate the plasma is between about 10W and about 500 W, for example, between about SOW and about 250 W, such as about 100 W.
  • a temperature of the environment within which the native oxide removal process is performed is between about 30°C and about 70°C, such as between about 40°C and about 50°C, for example, about 45°C.
  • the plasma is initiated and the native silicon oxide 804 experiences a thickness reduction illustrated by a reduction in thickness of the native silicon oxide material.
  • the plasma process is performed for an amount of time less than one minute, for example, less than 40 seconds, such as between about 15 seconds and about 30 seconds.
  • the native silicon oxide 804 is etched while the bulk silicon oxide experiences substantially no thickness reduction, indicating a high degree of selectivity for removal of the native silicon oxide preferentially to the bulk silicon oxide.
  • the native oxide removal process is also selective to silicon nitride materials such that native silicon oxide is removed preferentially to silicon nitride.
  • Atomic force microscopy analysis of the substrate after selective removal of the native silicon oxide revealed that exposed silicon surfaces (where the native silicon oxide was removed from) exhibited sub-angstrom surface roughness. Such a roughness is consistent with no or substantially no etching of the underlying silicon material after native oxide removal, as etching of the silicon material would be expected to roughen the surface.
  • residual material such an (NH 4 ) 2 )SiF 6 salt may remain on the substrate after performing the selective native oxide removal process.
  • an optional annealing process is performed. In one embodiment, the annealing process is between about 80°C and about 160°C, such as between about 100°C and about 140°C, for example, about 120°C. The annealing is believed to remove the salt, for example by volatilizing the salt, from the surface, such as a silicon surface, of the substrate.
  • Figure 9 is a cross-sectional schematic illustration of a substrate 900 having a contact structure 910 formed thereon according to an embodiment described herein.
  • the substrate 900 includes a silicon material film 902 and a bulk silicon oxide material 904 formed on the silicon material film 902.
  • Contact structures 910 are formed on a surface 906 of the silicon material film 902.
  • the surface 906, prior to selective native oxide removal has a thin film of native oxide formed thereon. Utilizing the embodiments described above, the native oxide is removed from the surface 906 without substantially altering or removing the bulk silicon oxide 904 or the underlying silicon film material 902.
  • Contact structures 910 formed on the surface 906 include a gate 916 which is bounded by a gate oxide 914, spacers 918, and a cap 920.
  • the gate 916 is a metal containing material.
  • the spacers 918 and the cap 920 include a nitride containing material, such as a silicon nitride material. Utilizing the selective native oxide removal processes described herein, either before or after formation of the contact structure 910, enables preparation of the surface 906 for subsequent metal deposition. Metal deposition in a channel 912 formed between adjacent contact structures 910 extends from the surface 906 toward the cap 920. By selectively removing the native oxide from the surface 906, metal adhesion to the underlying silicon material film 902 is improved.
  • the substrates were blow-dried using high purity N2 gas.
  • the Si, SiO 2 , SiON, and patterned substrate were loaded together on a single substrate holder to expose the substrates to the same ALD conditions.
  • the substrates were loaded into a load lock chamber pumped by a turbo molecular pump and backed by a mechanical pump.
  • the base pressure of the load lock was about 2.0x10 -7 Torr.
  • the substrates were transferred in-situ to an ultra-high vacuum chamber with a base pressure of about 3.0x10 -10 Torr pumped by an ion pump and titanium sublimation pump.
  • the ultra-high vacuum chamber was equipped with a monochromatic XPS apparatus, a scanning tunneling microscope (STM), and annealing system using a pyrolytic boron nitride (PBN) heater.
  • STM scanning tunneling microscope
  • PBN pyrolytic boron nitride
  • the substrates were first annealed at 120°C in the ultra-high vacuum chamber and the chemical composition of the substrates were determined using XPS.
  • the substrates were transferred in-situ to a reaction chamber having a base pressure of about 5.0x10 -7 Torr.
  • MoSi x deposition MoF 6 (99% purity) and Si 2 H 6 (99.99% purity) precursors were employed.
  • a constant purge of N2 80 mTorr was used, and the pressure of this purge was controlled using a leak valve.
  • the MoF 6 and Si 2 H 6 doses were regulated using pneumatic valves.
  • An expansion volume was employed for the MoF 6 and Si 2 H 6 doses. Utilization of the expansion volume includes filling a secondary volume with MoF 6 or Si 2 H 6 and dosing the precursors from their respective secondary volumes.
  • the fill time for the MoF 6 was between about 10 ms and about 10 ms, such as about 40 ms.
  • the dose time for the MoF 6 was between about 10 ms and about 100 ms, such as about 50ms.
  • the fill time for the Si 2 H 6 was between about 1 ms and about 50 ms, such as about 18 ms.
  • the dose time for the Si 2 H 6 was between about 1 ms and about 50 ms, such as about 18 ms.
  • the doses were about 1.8 MegaL for MoF 6 and about 4.2 MegaL for Si 2 H 6 with a 2-minute wait time between the doses.
  • the substrates were heated using the PBN heater, and the temperature was maintained at a temperature of between about 100°C and about 150°C, such as about 120°C.
  • the chamber walls were maintained at a temperature of between about 65°C and about 85°C.
  • the MoF 6 doses were between about 1.0 MegaL and about 10 MegaL.
  • the Si 2 H 6 doses were between about 1.0 MegaL and about 10 MegaL.
  • the substrates were transferred in-situ to the ultra-high vacuum chamber for XPS and STM analysis.
  • the X-rays were generated by an Al Ka anode (1486.7 eV).
  • XPS data was acquired using constant analyzer-energy (CAE) with a step width of 0.1 eV and a pass energy of 50 eV.
  • CAE constant analyzer-energy
  • the XPS detector was positioned at 60° to the substrate normal (30° take-off angle from the substrate surface) with a detector-acceptance angle of 7°.
  • XPS spectra were analyzed after correcting each peak area with its respective relative sensitivity factor using a Casa XPS v.2.3 program. All of the chemical components in this work were normalized to the sum of all components. Scanning tunnel microscopy was performed with a substrate bias of -1.8 V and a constant current of 200 pA.
  • Figure 1A illustrates data of the XPS chemical composition of the HF cleaned Si surface before and after sequential doses of MoF 6 and Si 2 H 6 at 120°C.
  • Two sets of 5.4 MegaL MoF 6 were dosed on a HF cleaned Si substrate at 120°C.
  • XPS showed saturation of Mo at 16%.
  • 4.2 Si 2 H 6 MegaL and an additional 42 MegaL of Si 2 H 6 were dosed onto the MoF 6 - saturated Si surface at 120°C resulting in Si being saturated at 59%.
  • the MoF 6 was dosed between about 1 MegaL and about 10 MegaL.
  • the Si 2 H 6 was dosed between about 1 MegaL and about 10 MegaL.
  • the additional Si 2 H 6 dose was between about 20 MegaL and about 50 MegaL.
  • Sequential doses of 4.2 MegaL of Si 2 H 6 and 42 MegaL of Si 2 H 6 indicate that the Si 2 H 6 reaction also saturates on the MoFx covered Si surface. It is believed that with a thicker sub-stoichiometric MoSi 2 film, additional Si can be incorporated onto the surface. However, the Si 2 H 6 reacts in a self-limiting manner on a thinner (monolayer) film of Mo.
  • Figure 1 B illustrates XPS chemical composition data for the same series of MoF 6 and Si 2 H 6 saturation doses described above with regard to Figure 1A but on a SiON substrate. As illustrated, no reaction was observed. It should be noted that while the SiON substrate was nominally SiON, XPS showed only negligible amounts of N on the surface and so this substrate is mostly ion damaged SiOx. After the first 3 pulses of MoF 6 , 8% F and negligible Mo ( ⁇ 1 %) were observed. For the rest of the saturation doses, the
  • SiON surface remained unreactive to both MoF 6 and Si 2 H 6 . While the SiON used in this study is ion damaged, the Si is in oxidation states of +3 and +4 and the data is consistent with the strong Si-O, Si-N, SiO-H bonds, thus substantially precluding the Si from forming bonds to Mo.
  • Figures 2A and 2B illustrates XPS spectra of Si 2p and Mo 3d for the HF cleaned Si substrate are shown to compare the oxidation states at each experimental operation.
  • Figure 2A illustrates Si 2p peaks after sequential MoF 6 and S 2 H 6 doses show that Si remained in an oxidation state of 0 after the 10.8 MegaL of MoF 6 at 120°C (blue line) which is consistent with Mo-Si bond formation and no etching of Si by F.
  • the 4.2 MegaL Si 2 H 6 dose at 120°C red line
  • FIG. 2B illustrates Mo 3d peaks after sequential MoF 6 and S 2 H 6 doses shows that the Mo 3d peaks existed in multiple oxidation states after the saturation dose of MoF 6 (black and blue line). After a Si 2 H 6 dose (red line), all of the Mo was reduced and the peak was centered at 227.4 eV which is consistent with MoSi 2 formation.
  • FIG. 3A illustrates the chemical composition of a set of three substrates: HF cleaned Si, HF cleaned SiO 2 , and HF cleaned patterned substrate.
  • Figure 3B illustrates the chemical composition of each of the Figure 3A substrates after 5 ALD cycles of MoF 6 and Si 2 H 6 at 120°C. The data indicated that a Si-deficient MoSi x was selectively deposited on Si and not on SiO 2 . The Si 0 component of the patterned sample was also selectively attenuated by the MoSi x deposition.
  • Figure 3C illustrates the chemical composition of each of the Figure 3B substrates after an additional 25.2 MegaL (between 3 pulses and 10 pulses) of Si 2 H 6 .
  • the additional Si 2 H 6 incorporated Si onto the MoSi x surface.
  • Selectivity with respect to SiO 2 was maintained during the additional Si 2 H 6 pulses (SiO 2 had 0% Mo and 0% Si 0 throughout the ALD process).
  • the three substrates were loaded together on a single substrate holder to ensure that they were exposed to identical deposition conditions.
  • the Si and SiO 2 substrates allowed verification of selectivity during deposition on the patterned substrate.
  • the patterned substrate has SiO 2 layers sandwiched by SiNx on top of the Si substrate. It is noted that the SiNx on the patterned substrate was actually SiON since it was ion damaged and ashed in O2 during fabrication.
  • a 30 s HF clean removed the native oxide on Si.
  • the thermally grown SiO 2 was 300 nm thick and the 30 s of HF clean did not change the elemental composition or oxidation states of SiO 2 .
  • the HF cleaned patterned substrate was composed of a mixture of SiNx, SiOx and Si 0 .
  • XPS was performed after 5 ALD cycles of MoF 6 and Si 2 H 6 at 120°C as shown in Figure 3B.
  • XPS showed a surface composition of 32% Mo and 10% Si on the Si substrate which corresponds to highly Si-deficient MoSi x .
  • MoSi x deposition on the SiO 2 substrate consistent with highly selective ALD.
  • XPS showed that 5% Mo was deposited, and the Si 0 was attenuated to 1 %.
  • the fraction of N and O at the surface did not change significantly during ALD on the patterned substrate.
  • the data is consistent with Si-deficient MoSi x being deposited selectivity on the 6% of Si 0 on the patterned substrate.
  • Deposition selectivity on the pattern substrates is consistent with three aspects of embodiments described herein: (1 ) MoSi x deposition occurred on the Si substrate but not on the SiO 2 substrate. (2) After the MoSi x deposition, the Si 0 (not the higher oxidation state Si peaks from Si-N and Si- 0) was attenuated on the pattered substrate. (3) Numerically, about 4% Mo deposition on the patterned substrate with 6% Si 0 is proportional to having 32% Mo on the Si substrate with 54% Si 0 on the HF clean surface.
  • Figures 4A-4C illustrate XPS chemical composition data of selective MoSi x deposition on HF cleaned Si, SiO 2 , and SiON with a post deposition anneal.
  • Figure 4A illustrates XPS chemical composition of Si, SiO 2 , and SiON substrates after the HF clean.
  • Figure 4B illustrates XPS chemical composition data showing the MoSi x was selectively deposited only on Si after the 5 ALD cycles of MoSi x followed by the additional 6 pulses (25.2 MegaL) of Si 2 H 6 at 120°C.
  • Figure 4C illustrates XPS chemical composition data of the substrates with a post-deposition anneal (PDA) performed at 520°C for 3 mins. As illustrated, the PDA removed F from the MoSi x film and reduced the Mo to Mo 0 .
  • PDA post-deposition anneal
  • Figure 4A illustrates that the SiON surface is composed primarily of SiNx after the HF clean.
  • MoSi x ALD followed by an additional 25.2 MegaL of Si 2 H 6 .
  • the 520°C PDA also reduced the Mo to Mo 0 on the Si substrate and decreased the Si:Mo ratio from about 0.75 to about 0.5 at the surface. This is consistent with the desorption of surface F in the form of SiHF 3 or SiF 4 .
  • the XPS analysis of the PDA indicates that the F is removed from the film by the PDA which reduces the probability of F diffusion into adjacent MOSFET device structures.
  • Ex-situ AFM image data of the SiO 2 substrate surface after dosing 5 ALD cycles at 120°C followed by an in-situ 550°C anneal for 3 minutes in order to confirm the selectivity was performed by counting the number of nuclei on the substrate surface. The density of nuclei was about 9 nuclei/mm 2 which confirms the Si deposition preference over SiO 2 . It is believed that the high deposition selectivity of the embodiments described herein is further improved by controlling wall temperature of the reaction chamber and by using short high pressure Si 2 H 6 pulses and longer purge cycles to facilitate ALD and avoid a CVD deposition regime.
  • FIG. 5A illustrates XPS chemical composition data after Ar + sputtering on HF cleaned Si after the 5 cycles of MoF 6 and Si 2 H 6 at 120°C.
  • Figure 5B illustrates XPS peaks of Si 2p after sequential Ar + sputtering, the results of which show that the bulk of the MoSi x film consisted mostly of Si 0 .
  • Figure 5C illustrates chemical composition data of the deposited film plotted versus Ar + sputter time on Si after 5 cycles of MoF 6 and Si 2 H 6 at 120°C.
  • the XPS data shown in Figure 5A was derived from the MoSi x film deposited on a HF cleaned Si substrate at 120°C using 5 ALD cycles of MoF 6 and Si 2 H 6 without additional Si 2 H 6 incorporation. As the sputtering time increased, the MoSi x film became thinner until the underlying Si substrate was exposed. The first 10 mins of sputtering decreased the F from 35% to 8% while the Mo shifted from a mixture of oxidized Mo and Mo 0 to pure Mo 0 . The data is consistent with the surface F being bonded primarily to Mo.
  • the Si 0 to Mo 0 ratio was employed to distinguish the pure MoSi x phase because, in the pure MoSi x phase, both Mo and Si are bonded to each other and have an oxidation state of 0. After removal of the silicon oxide and MoFx species at the substrate surface, the percentage of Si 0 exceeded that of Mo 0 .
  • the Si 0 :Mo 0 ratio in the bulk of the MoSi x film was 1.41 which corresponds to a Si-deficient MoSi x film. It is noted that in the center of the film the Si:Mo ratio is 1.77 therefore, in the absence of background O 2 /H 2 O, it is possible the Si 0 :Mo 0 ratio would be closer to 2.
  • Figure 5B illustrates the raw XPS spectra of Si 2p corresponding to each XPS measurement of Figure 5A.
  • the Si peak at 99.2 eV increased and broadened to higher binding energy after the 4 th sputtering cycle.
  • the energy of the Mo peak corresponded to Mo 0 after each sputtering cycle.
  • the bulk MoSi x film is predominantly Si 0 and Mo 0 in the form of MoSi x while the top surface and the bottom interface was rich in SiOx.
  • the top SiOx is consistent with contamination from the chamber environment while the bottom interfacial oxide is consistent with the imperfect ex-situ HF clean.
  • FIG. 5C illustrates the percentages of the chemical components obtained from the XPS measurement in Figure 5A. After the second sputtering cycle (40 mins of total sputtering time), F decreased to below 3% and eventually reached 0%. 0 in the bulk of the film was ⁇ 10% but slowly increased to 15% at the MoSi x -Si interface which is consistent with the existence of an interfacial oxide layer.
  • Figures 6A-6D illustrate XPS profile data of the MoSi x film with after exposure to the additional Si 2 H 6 doses.
  • Figure 6A illustrates XPS chemical composition data after Ar + sputtering dry cleaned Si after 5 cycles of MoF 6 and Si 2 H 6 followed by additional 6 pulses (25.2 MegaL) of Si 2 H 6 at 120°C.
  • Figure 6B illustrates XPS surface composition data after 5 ALD cycles of MoF 6 and Si 2 H 6 with and without extra Si 2 H 6 pulses.
  • Si:Mo ratios were 0.33 for 5 ALD and 0.89 for 5ALD + 6xSi 2 H 6 which is consistent with Si incorporation on the surface.
  • Figure 6C illustrates XPS bulk composition data of MoSi x with and without extra Si 2 H 6 pulses after removing surface contaminations using the Ar + sputtering. Si:Mo ratios were 1.77 for 5 ALD and 1.96 for 5ALD + 6xSi 2 H 6 .
  • Figure 6D illustrates XPS chemical composition data of the MoSi x film is plotted versus Ar + sputter time on Si after 5 cycles of MoF 6 and Si 2 H 6 followed by additional Si 2 H 6 pulses at 120°C.
  • Figure 6A presents a series of depth-profile XPS after each operation performed on the dry cleaned substrate. After the 6xSi 2 H 6 /5ALD cycles, there was 28% F, 20% Si, and 28% Mo at the substrate surface. F on the surface was mostly removed after the 530°C anneal and the Mo was all reduced to Mo 0 which was consistent with the desorption of F from the surface as presented in Figure 4C. The Si:Mo ratio was 0.89 at this operation. By comparison, the Si:Mo ratio of the MoSi x film without the extra Si 2 H 6 doses was only 0.33 as illustrated in Figure 6B.
  • Figure 6D shows the XPS percentage of each chemical component in the function of the Ar + sputter time which is consistent with the MoSi x formation in bulk of the MoSi x film.
  • 4.2 MegaL of Si 2 H 6 was introduced to the reaction chamber over a duration of 6 seconds using a pneumatic valve.
  • the Si 2 H 6 process characteristics utilize an approximately 3 times larger Si 2 H 6 exposure over a dosing duration about 10 times shorter than conventional Si 2 H 6 dosing parameters.
  • embodiments described herein utilize a 30x higher partial pressure during the ALD dose when compared to conventional dosing regimes. The 30x higher instantaneous pressure during dosing is believed to enable a precursor mediated Si 2 H 6 chemisorption layer to remain on the surface long enough to react with the Mo to incorporate more Si into the MoSi x film.
  • the Si incorporation is also believed to be self-limiting which enables a growth rate of MoSi x of about 1.2 nm/cycle.
  • the resistance of the MoSi x film was measured using a 4-point probe measurement. For the electrical measurement, updoped Si (001 ) with >10000 ohm cm resistance was used as a substrate. For the electrical measurement, 10 cycles of MoSi x ALD at 120°C was deposited on an HF cleaned intrinsic (semi-insulating) Si substrate followed by an in-situ 550°C anneal for 3 minutes and a 900°C spike anneal in 5% H2 balanced in N2. Ni dots were deposited as a probe contact. The resistance was 1 10 Ohm and, using an infinite sheet approximation, the resistivity was calculated as:
  • FIG. 7 is a cross-sectional TEM image of the MoSi x /HF cleaned patterned substrate. On the HF cleaned patterned substrate, 5 cycles of MoSi x ALD followed by an additional 25.2 MegaL of Si 2 H 6 were dosed at 120°C. The elemental composition of this substrate at each deposition step is shown in Figures 3A-3C. The TEM image shows complete selectivity of MoSi x deposition on Si but not on SiNx nor SiO 2 .
  • the thickness of the MoSi x film deposited on Si was about 6.3 nm after the 5 ALD cycles followed by an additional 25.2 MegaL which achieved a growth rate of about 1.2 nm/cycle. Due to the growth rate per cycle of MoSi x ALD, 5 ALD cycles is believed to be sufficient for contact materials and contact device structures.
  • the surface of the MoSi x film after 5 ALD cycles showed a highly Si- deficient MoSi x surface with Si:Mo ratio of 0.33 and this Si:Mo ratio at the surface is improved to 0.89 by pulsing extra Si 2 H 6 .
  • the cross-sectional TEM imaging shows that the selectivity is retained on the nanoscale and that MoSi x can be selectively deposited on Si without substrate consumption.
  • the MoSi x film growth rate of about 1.2 nm/cycle enables less than 10 ALD cycles, such as 5 ALD cycles, to be sufficient for utilization of the
  • MoSi x film as a contact material. Accordingly, process throughput is increased by utilizing the embodiments described herein when compared to conventional ALD processes. It is believed the selective MoSi x deposition eliminates or substantially reduces reliance on lithography processes for complicated 3D MOSFET structures ( e.g FinFETs). The selectivity for Si-H bonds vs SiO-H bonds exceeds 10 6 . Thus, high selectivity is possible on the nanoscale even without the use additional passivation layers The embodiments described herein also illustrate that ALD of silicide versus metal could readily be switched while retaining selectivity by changing the partial pressure during the ALD pulse of the reductant.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Electromagnetism (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Des modes de réalisation de l'invention concernent des procédés de dépôt sélectif de siliciure métallique. Selon un mode de réalisation, un substrat ayant une surface contenant du silicium est chauffé et la surface contenant du silicium comporte une terminaison hydrogène. Le substrat est exposé à des cycles séquentiels d'un précurseur MoF6 et d'un précurseur Si2H6, qui sont suivis d'une exposition supplémentaire à une surdose de Si2H6 pour déposer sélectivement un matériau MoSix comprenant MoSi2 sur la surface contenant du silicium du substrat. Les procédés décrits ici assurent également une élimination sélective d'oxyde natif qui permet l'élimination de matériau d'oxyde natif sans graver des matériaux d'oxyde bruts.
EP19884016.7A 2018-11-13 2019-09-25 Dépôt sélectif de siliciures métalliques et élimination sélective d'oxyde Pending EP3881349A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/189,429 US10586707B2 (en) 2017-05-26 2018-11-13 Selective deposition of metal silicides
PCT/US2019/052967 WO2020101806A1 (fr) 2018-11-13 2019-09-25 Dépôt sélectif de siliciures métalliques et élimination sélective d'oxyde

Publications (2)

Publication Number Publication Date
EP3881349A1 true EP3881349A1 (fr) 2021-09-22
EP3881349A4 EP3881349A4 (fr) 2022-08-24

Family

ID=70731667

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19884016.7A Pending EP3881349A4 (fr) 2018-11-13 2019-09-25 Dépôt sélectif de siliciures métalliques et élimination sélective d'oxyde

Country Status (6)

Country Link
EP (1) EP3881349A4 (fr)
JP (1) JP7503547B2 (fr)
KR (1) KR20210076166A (fr)
CN (1) CN113348532A (fr)
TW (1) TWI833831B (fr)
WO (1) WO2020101806A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115739190B (zh) * 2022-11-14 2024-02-13 江南大学 一种植酸金属络合物催化剂及其制备方法与应用

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61128521A (ja) * 1984-11-27 1986-06-16 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPH07283168A (ja) * 1994-04-15 1995-10-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
US9051641B2 (en) * 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US20040102033A1 (en) * 2002-11-21 2004-05-27 Texas Instruments, Incorporated Method for forming a ternary diffusion barrier layer
US7780793B2 (en) * 2004-02-26 2010-08-24 Applied Materials, Inc. Passivation layer formation by plasma clean process to reduce native oxide growth
TW200746268A (en) * 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
US8455352B1 (en) * 2012-05-24 2013-06-04 Applied Materials, Inc. Method for removing native oxide and associated residue from a substrate
US9875907B2 (en) * 2015-11-20 2018-01-23 Applied Materials, Inc. Self-aligned shielding of silicon oxide
TWI716511B (zh) * 2015-12-19 2021-01-21 美商應用材料股份有限公司 用於鎢原子層沉積製程作為成核層之正形非晶矽
US10468263B2 (en) * 2015-12-19 2019-11-05 Applied Materials, Inc. Tungsten deposition without barrier layer
US9803277B1 (en) * 2016-06-08 2017-10-31 Asm Ip Holding B.V. Reaction chamber passivation and selective deposition of metallic films
US9805974B1 (en) * 2016-06-08 2017-10-31 Asm Ip Holding B.V. Selective deposition of metallic films

Also Published As

Publication number Publication date
JP7503547B2 (ja) 2024-06-20
EP3881349A4 (fr) 2022-08-24
TWI833831B (zh) 2024-03-01
TW202035759A (zh) 2020-10-01
JP2022506677A (ja) 2022-01-17
KR20210076166A (ko) 2021-06-23
CN113348532A (zh) 2021-09-03
WO2020101806A1 (fr) 2020-05-22

Similar Documents

Publication Publication Date Title
TWI842531B (zh) 氧化矽之拓撲選擇性膜形成之方法
EP3424070B1 (fr) Monocouche auto-assemblée améliorée de blocage par exposition intermittente air-eau
US20160276208A1 (en) Selective formation of metallic films on metallic surfaces
KR100871006B1 (ko) 얇은 텅스텐 실리사이드층 증착 및 게이트 금속 집적화
US9478460B2 (en) Cobalt selectivity improvement in selective cobalt process sequence
US10475655B2 (en) Selective deposition of metal silicides
US10373824B2 (en) CVD silicon monolayer formation method and gate oxide ALD formation on semiconductor materials
US20180308685A1 (en) Low temperature selective epitaxial silicon deposition
US10586707B2 (en) Selective deposition of metal silicides
Choi et al. Selective pulsed chemical vapor deposition of water-free HfOx on Si in preference to SiCOH and passivated SiO2
WO2020101806A1 (fr) Dépôt sélectif de siliciures métalliques et élimination sélective d&#39;oxyde
US10262858B2 (en) Surface functionalization and passivation with a control layer
Sim et al. Method to enhance atomic-layer deposition of tungsten–nitride diffusion barrier for Cu interconnect
TWI780157B (zh) 金屬矽化物的選擇性沉積
US20170040158A1 (en) Low temperature ald on semiconductor and metallic surfaces
TWI856173B (zh) Peald氮化物膜
Choi Area-selective Atomic Layer Deposition of Silicide and Oxides Using Inherent Substrate Dependent Processes
Sato et al. In situ vapor phase surface activation of SiO 2

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20210512

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20220725

RIC1 Information provided on ipc code assigned before grant

Ipc: C23C 16/455 20060101ALI20220719BHEP

Ipc: C23C 16/42 20060101ALI20220719BHEP

Ipc: C23C 16/46 20060101ALI20220719BHEP

Ipc: H01L 21/324 20060101ALI20220719BHEP

Ipc: H01L 21/311 20060101ALI20220719BHEP

Ipc: H01L 21/285 20060101AFI20220719BHEP