EP3843074B1

EP3843074B1 - Drd type display panel and organic light emitting display device using same

Info

Publication number: EP3843074B1
Application number: EP20214549.6A
Authority: EP
Inventors: Hyung-Seok Seo; Young-Hoon Kim
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2019-12-26
Filing date: 2020-12-16
Publication date: 2022-08-10
Anticipated expiration: 2040-12-16
Also published as: CN118379962A; US11705073B2; KR20210082713A; CN113053962B; CN113053962A; EP3843074A1; US20210201829A1

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a DRD (double rate driving) type display panel and an organic light emitting display device, and more specifically, to an organic light emitting display device using DRD in which openings are disposed on the left and right of a driving circuit.

Discussion of the Related Art

An organic light emitting display device has a structure in which an emission layer is formed between a cathode for electron injection and an anode for hole injection and uses the principle that, when electrons generated in the cathode and holes generated in the anode are injected into the emission layer, the injected electrons and holes are combined to generate excitons and transition of the generated excitons from an excited state to a ground state causes light emission.
Such an organic light emitting display device includes a transistor as a switching element. Transistors are classified into a bottom gate structure in which a gate electrode is positioned under an active layer and a top gate structure in which a gate electrode is positioned on an active layer.
Such an organic light emitting display device includes a scan driver for driving gate lines and a data driver for driving data lines, and the number of drive ICs required increases as the size and resolution of the organic light emitting display device increase.
However, since the drive IC is considerably expensive compared to other elements, various methods for reducing the number of drive ICs to decrease the manufacturing cost of the organic light emitting display device have recently been researched and developed. Among these methods, a double rate driving (DRD) method halves the number of data lines while doubling the number of gate lines, compared to conventional organic light emitting display devices, to realize resolution equivalent to those of the conventional organic light emitting display devices while halving the number of drive ICs required.
A data line through which an operating voltage is supplied to two subpixels is superposed on a reference voltage line through which a reference voltage is supplied to each pixel. This leads to a problem that a reference voltage signal is affected by a data signal due to DRD characteristics so that images are displayed dark due to ripple effect. KR 2019 0048569 A describes an organic light emitting display device comprising: first to fourth pixels provided on a substrate and including a capacitor region; a first data line transferring a data signal to the first and second pixels; a second data line transferring the data signal to the third and fourth pixels; a first scan line transferring a scan signal to the second and third pixels; and a second scan line transferring the scan signal to the first and fourth pixels. The first and second data lines include a data line hole formed for supplying data voltage to each pixel. The first and second scan lines are located between the data line hole and the capacitor region. KR 2019 0048356 A describes an organic light emitting display device comprising: first to fourth pixels provided on a substrate; a first data line transferring a data signal to the first and second pixels; a second data line transferring the data signal to the third and fourth pixels; a first scan line transferring a scan signal to the first and fourth pixels; a second scan line transferring the scan signal to the second and third pixels; and first to fourth capacitors individually provided at the first to fourth pixels and storing the signal from the first or second data line. The first to fourth capacitors are located between the first scan line and the second scan line.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a display panel and an organic light emitting display device using the same which can increase an aperture ratio.
Another object of the present invention is to provide a display panel having a structure in which a reference voltage line is not superposed on a data line and an organic light emitting display device using the same.
These objects are solved by the subject-matter of the independent claim. Further advantageous embodiments and refinements are described in the respective dependent claims.
The display panel and the organic light emitting display device using the same according to the present invention has a structure in which left and right openings are provided such that a reference voltage line is not superposed on a data line. Accordingly, an aperture ratio can he maximized

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing a configuration of an organic light emitting display device according to the present invention.
FIG. 2 illustrates a configuration of a display panel according to the present invention.
FIG. 3 illustrates an equivalent circuit of the display panel of FIG. 2.
FIG. 4 shows voltages and signals supplied to elements of each pixel driver.

DETAILED DESCRIPTION OF THE INVENTION

For embodiments of the present invention disclosed in the description, specific structural and functional descriptions are exemplified for the purpose of describing embodiments of the present invention, and embodiments of the present invention can be implemented in various forms and are not to be considered as a limitation of the invention.
While terms, such as "first", "second", etc., may be used to describe various components, such components must not be limited by the above terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component and the second component may be referred to as the first component without departing from the scope of the present invention.
When an element is "coupled" or "connected" to another element, it should be understood that a third element may be present between the two elements although the element may be directly coupled or connected to the other element. When an element is "directly coupled" or "directly connected" to another element, it should be understood that no element is present between the two elements. Other representations for describing a relationship between elements, that is, "between", "immediately between", "in proximity to", "in direct proximity to" and the like should be interpreted in the same manner.
The terms used in the specification of the present invention are merely used in order to describe particular embodiments, and are not intended to limit the scope of the present invention. An element described in the singular form is intended to include a plurality of elements unless the context clearly indicates otherwise. In the specification of the present invention, it will be further understood that the terms "comprise" and "include" specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations.
Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Meanwhile, when a certain embodiment can be implemented in a different manner, a function or an operation specified in a specific block may be performed in a different sequence from that specified in a flowchart. For example, two consecutive blocks may be simultaneously executed or reversely executed according to related function or operation.
In the following description, a pixel circuit and a gate driving circuit formed on a substrate of a display panel may be implemented by n-type or p-type transistors. For example, a transistor may be implemented by a MOSFET (metal oxide semiconductor field effect transistor). The transistor is a three-electrode element including a gate, a source and a drain. The source is an electrode that provides carriers to the transistor. Carriers flow from the source in the transistor. The drain is an electrode through which carriers are emitted in the transistor. For example, carriers flow from the source to the drain in the transistor. In the case of the n-type transistor, carriers are electrons and thus a source voltage is lower than a drain voltage such that the electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type transistor, current flows from the drain to the source. In the case of the p-type transistor, carriers are holes and thus a source voltage is higher than a drain voltage such that the holes can flow from the source to the drain. Since holes flow from the source to the drain in the p-type transistor, current flows from the source to the drain. The source and the drain of a transistor are not fixed and may be interchanged according to voltages applied thereto.
A gate on voltage may be a voltage of a gate signal at which a transistor can be turned on. A gate off voltage may be a voltage at which a transistor can be turned off. A gate on voltage of the p-type transistor may be a logic low voltage VL and a gate off voltage thereof may be a logic high voltage VH A gate on voltage of the n-type transistor may be a logic high voltage and a gate off voltage thereof may be a logic low voltage.
Hereinafter, configurations and operation of a display panel and an organic light emitting display device using the same according to the present invention will be described with reference to the attached drawings.
FIG. 1 is a block diagram schematically showing a configuration of an organic light emitting display device according to the present invention. In the organic light emitting display device according to the present invention, a panel 100 uses double rate driving (hereinafter simply referred to as "DRD"). That is, as shown in FIG. 1, d/2 data lines DL1 to DLd/2 and 2g gate lines GL1 to GL2g are arranged in a matrix in an intersecting manner such that d×g pixels are formed in a DRD type.
The organic light emitting display device includes the display panel 100 in which a pixel electrode is formed at each pixel, a gate driver 200 which sequentially supplies a scan pulse signal to the gate lines GL1 to GL2g, a data driver 300 which supplies data voltages to the data lines DL1 to DLd/2, and a timing controller 400 which controls driving timings of the gate driver 200 and the data driver 300 through DRD.
DRD is a method for reducing the number of data drivers 300 or the number of data lines DL of the display device. In a panel using DRD, the number of gate lines GL is doubled whereas the number of data lines DL is halved, compared to conventional display devices. That is, DRD can realize the same resolution as conventional display devices while halving the required number of drivers 300 or the required number of data lines DL.
That is, in the display device using DRD according to the present invention, d pixels arranged in a single horizontal line of the display panel 100 can be driven using two gate lines GL and d/2 data lines DL arranged above and below the horizontal line.
The timing controller 400 outputs a gate control signal GCS for controlling the gate driver 200 and a data control signal DCS for controlling the data driver 300 using vertical/horizontal synchronization signals and a clock signal supplied from an external system (not shown).
Further, the timing controller 400 samples input image data input from the external system, rearranges the sampled input image data and provides the rearranged digital image data RGB to the data driver 300.
The timing controller 400 generates the gate control signal GCS for controlling the gate driver 200 and the data control signal DCS for controlling the data driver 300 using a clock signal, a horizontal synchronization signal H Sync, a vertical synchronization signal V_Sync, and a data enable signal DE supplied from the external system and transmits the gate control signal GCS and the data control signal DCS to the gate driver 200 and the data driver 300.
The timing controller 400 may include a receiver for receiving input image data and various signals from the external system, an image data processor for rearranging input image data from among signals received through the receiver such that the input image data is suited to the display panel to generate rearranged digital image data, a control signal generator for generating the gate control signal GCS and the data control signal DCS for controlling the gate driver 200 and the data driver 300 using signals received through the receiver, and a transmitter for outputting image data generated by the image data processor and control signals to the data driver 300 and the gate driver 200.
The data driver 300 converts image data input from the timing controller 400 into an analog data voltage and supplies a data voltage corresponding to one horizontal line to the data lines for each horizontal period in which a gate pulse signal is supplied to the gate lines. That is, the data driver 300 converts image data into a data voltage using gamma voltages supplied from a gamma voltage generator (not shown) and then outputs the data voltage to the data lines.
The data driver 300 shifts a source start pulse signal SSP from the timing controller 400 according to a source shift clock signal SSC to generate a sampling signal. In addition, the data driver 300 latches pixel data RGB (image data) input according to the source shift clock signal SSC using the sampling signal, converts the pixel data RGB into a data voltage, and then supplies the data voltage to the data lines in units of a horizontal line in response to a source output enable signal SOE. To this end, the data driver 300 may include a shift register, a latch, a digital-to-analog converter, and an output buffer.
The gate driver 200 sequentially supplies a scan pulse signal to the gate lines GL1 to GL2g of the display panel 100 in response to the gate control signal GCS input from the timing controller 400. Accordingly, switching transistors formed in respective pixels of a corresponding horizontal line to which the scan pulse signal is applied are turned on so that an image can be output to the pixels.
That is, the gate driver 200 shifts a gate start pulse signal GSP supplied from the timing controller 400 according to a gate shift clock signal GSC and sequentially supplies a scan pulse signal having a gate on voltage Von to gate lines GL1 to GL2g. Further, the gate driver 200 supplies a gate off voltage V off to the gate lines GL1 to GL2g in a period in which the scan pulse signal at the gate on voltage Von is not supplied.
Although the gate driver 200 may be formed independently of the display panel 100 and electrically connected to the display panel in various manners, the gate driver 200 may be configured in the form of a gate in panel (GIP) mounted in the display panel 100. In this case, gate control signals for controlling the gate driver 200 may include a start signal VST and a gate clock signal GCLK.
Although the data driver 300, the gate driver 200 and the timing controller 400 are independently configured in the above description, at least one of the data driver 300 and the gate driver 200 may be integrated with the timing controller 400.
A specific structure of a pixel formed in the display panel 100 using DRD will be described in detail below with reference to FIGS. 2 and 3.
FIG. 2 illustrates a configuration of a pixel of the display device according to the present invention and FIG. 3 illustrates an equivalent circuit of the display panel of FIG. 2. Although a pixel is composed of an n-type transistor in the present embodiment, the pixel may be composed of a p-type transistor or composed of both the n-type transistor and the p-type transistor.
As shown in FIG. 2, a pixel has a QUAD structure including four subpixels P1 to P4 in the display device according to an embodiment of the present invention. Here, the first to fourth subpixels can be configured using organic light-emitting diodes (OLEDs) capable of representing R, G, B and W. This is merely an embodiment for describing the present invention and the subpixels may be configured using OLEDs capable of representing R, G and B. The first to fourth subpixels P1 to P4 may constitute a unit pixel.
As shown in FIG. 2, the unit pixel includes first and second gate lines GL1 and GL2 arranged in a first direction, first and second power lines VL1 and VL2 which intersect the first and second gate lines GL1 and GL2 and are arranged in a second direction, first and second data lines DL1 and DL2, a reference voltage line V_ref, and first to fourth pixel drivers. The first to fourth pixel drivers are arranged such that pairs of the pixel drivers are symmetrically disposed on the basis of the reference voltage line V_ref.
The first and second subpixels P1 and P2 are formed between the first power line VL1 and the reference voltage line V_ref and the third and fourth subpixels P3 and P4 are formed between the reference voltage line V_ref and the second power line VL2.
The first to fourth pixel drivers composed of a plurality of transistors and capacitors are arranged such that they are symmetrical on the basis of the reference voltage line V_ref. The first to fourth drivers are arranged between the data lines DL1 and DL2 and the reference voltage line V_ref.
The first pixel driver for driving the first subpixel P1 and the second pixel driver for driving the second subpixel P2 are arranged between the first data line DL1 and the reference voltage line V_ref. The third pixel driver for driving the third subpixel P3 and the fourth pixel driver for driving the fourth subpixel P4 are arranged between the reference voltage line V_ref and the second data line DL2.
A data voltage is supplied to the first pixel driver for driving the first subpixel P1 and the second pixel driver for driving the second subpixel P2 through the first data line DL1. A data voltage is supplied to the third pixel driver for driving the third subpixel P3 and the fourth pixel driver for driving the fourth subpixel P4 through the second data line DL2.
A scan pulse signal is supplied to a scan transistor formed in the first pixel driver of the first subpixel P1 and a scan transistor formed in the second pixel driver of the second subpixel P2 through the first gate line GL1. A scan pulse signal is supplied to a scan transistor formed in the third pixel driver of the third subpixel P3 and a scan transistor formed in the fourth pixel driver of the fourth subpixel P4 through the second gate line GL2.
The subpixels P1 to P4 of each unit pixel include the first to fourth pixel drivers each including a plurality of transistors T1, T2 and DT, a capacitor Cst, and an OLED, as shown in FIG. 3.
Each pixel driver includes a driving transistor DT which causes an OLED to emit light, a switching transistor T1 which controls light emission of the OLED according to a signal from a gate line, and a sensing transistor T2 which performs control such that a threshold voltage of the driving transistor DT is sensed according to a signal from the gate line.
A first driving transistor DT_R of the first pixel driver includes a first source electrode connected to the first power line VL1, a first drain electrode connected to the OLED, and a first gate electrode to which a driving signal from the first data line DL1 is applied and supplies a driving current necessary to operate the OLED of the first pixel driver. The first source electrode of the first driving transistor DT_R is connected to the first power line VL1 through a contact hole CH1 and a contact hole CH8. A semiconductor compound layer between the first source electrode and the first drain electrode of the first driving transistor DT_R is connected through a contact hole CH7 and the contact hole CH8.
A first switching transistor TI_R of the first pixel driver includes a second source electrode connected to the first data line DL1, a second drain electrode connected to the first gate electrode of the first driving transistor DT_R, and a second gate electrode connected to the first gate line GL1 and transfers a data voltage to the first gate electrode of the first driving transistor DT_R.
The second source electrode of the first switching transistor T1_R is connected to the first data line DL1 through a contact hole CH2. The second drain electrode of the first switching transistor T1_R is connected to the first gate electrode of the first driving transistor DT_R through a contact hole CH6. The second gate electrode of the first switching transistor T1_R is connected to the first gate line GL1.
The storage capacitor Cst of the first pixel driver is provided in a capacitor region between the first drain electrode of the first driving transistor DT_R and the second drain electrode of the first switching transistor T1_R and stores a data voltage supplied through the first data line DL1. One terminal of the storage capacitor C_st of the first pixel driver is connected to the first drain electrode of the first driving transistor DT_R through the contact hole CH6 and the other terminal thereof is connected to the second drain electrode of the first switching transistor T1_R and the first gate electrode of the first driving transistor DT_R.
A first sensing transistor T2_R of the first pixel driver includes a third source electrode connected to the storage capacitor C_st, a third drain electrode connected to the reference voltage line V_ref, and a third gate electrode connected to the first gate line GL1 and senses a threshold voltage of the first driving transistor DT_R according to a signal provided through the first gate line GL1. The third source electrode of the first sensing transistor T2_R is connected to the reference voltage line V_ref through a contact hole CH3. A semiconductor compound layer between the third source electrode and the third drain electrode of the first sensing transistor T2_R is connected through the contact hole CH3 and a contact hole CH4. The third drain electrode of the first sensing transistor T2_R is connected to the capacitor Cst through the contact hole CH4 and a contact hole CH5 and connected to the first drain electrode of the first driving transistor DT_R through the contact hole CH4 and the contact hole CH7.
A second driving transistor DT_B of the second pixel driver has a configuration similar to that of the first driving transistor DT_R of the first pixel driver and supplies a driving current necessary to operate the OLED of the second pixel driver.
The first source electrode of the second driving transistor DT_B is connected to the first power line VL1 through the contact hole CH1 and the contact hole CH8. A semiconductor compound layer between the first source electrode and the first drain electrode of the second driving transistor DT_B is connected through the contact hole CH7 and the contact hole CH8.
A second switching transistor T1_B of the second pixel driver includes a second source electrode connected to the first data line DL1, a second drain electrode connected to the first gate electrode of the second driving transistor DT_B, and a second gate electrode connected to the second gate line GL2 and transfers a data voltage supplied through the first data line DL1 to the first gate electrode of the second driving transistor DT_B. The second source electrode of the second switching transistor T1_B is connected to the first data line DL1 through the contact hole CH2. The second drain electrode of the second switching transistor T1_B is connected to the first gate electrode of the second driving transistor DT_B through the contact hole CH6. The second gate electrode of the second switching transistor T1_B is connected to the first gate line GL1.
A second sensing transistor T2_B of the second pixel driver includes a third source electrode connected to the storage capacitor Cst of the second pixel driver, a third drain electrode connected to the reference voltage line V_ref, and a third gate electrode connected to the second gate line GL2 and senses a threshold voltage of the second driving transistor DT_B according to a signal provided through the second gate line GL2. A semiconductor compound layer between the third source electrode and the third drain electrode of the second sensing transistor T2_B is connected through the contact hole CH3 and the contact hole CH4. The third drain electrode of the second sensing transistor T2_B is connected to the capacitor Cst through the contact hole CH4 and the contact hole CH5 and connected to the first drain electrode of the second driving transistor DT_B through the contact hole CH4 and the contact hole CH6.
A third driving transistor DT_G of the third pixel driver includes a first source electrode connected to the second power line VL2, a first drain electrode connected to the OLED, and a first gate electrode to which a driving signal from the second data line DL2 is applied and supplies a driving current necessary to operate the OLED of the third pixel driver. The first source electrode of the third driving transistor DT_G is connected to the second power line VL2 through the contact hole CH1 and the contact hole CH8. A semiconductor compound layer between the first source electrode and the first drain electrode of the third driving transistor DT_G is connected through the contact hole CH7 and the contact hole CH8.
A third switching transistor T1_G of the third pixel driver includes a second source electrode connected to the second data line DL2, a second drain electrode connected to the first gate electrode of the third driving transistor DT_G, and a second gate electrode connected to the first gate line GL1 and transfers a data voltage supplied through the first data line DL1 to the first gate electrode of the third driving transistor DT_G. The second source electrode of the third switching transistor T1_G is connected to the second data line DL2 through the contact hole CH2. The second drain electrode of the third switching transistor T1_G is connected to the first gate electrode of the third driving transistor DT_G through the contact hole CH6. The second gate electrode of the third switching transistor T1_G is connected to the second gate line GL2.
A third sensing transistor T2_G of the third pixel driver includes a third source electrode connected to the storage capacitor Cst of the third pixel driver, a third drain electrode connected to the reference voltage line V_ref, and a third gate electrode connected to the first gate line GL1 and senses a threshold voltage of the third driving transistor DT_G according to a signal provided through the first gate line GL1. A semiconductor compound layer between the third source electrode and the third drain electrode of the third sensing transistor T2_G is connected through the contact hole CH3 and a contact hole CH4. The third drain electrode of the third sensing transistor T2_G is connected to the capacitor Cst through the contact hole CH4 and the contact hole CH5 and is connected to the first drain electrode of the third driving transistor DT_G through the contact hole CH4 and the contact hole CH7.
A fourth driving transistor DTw of the fourth pixel driver includes a first source electrode connected to the second power line VL2, a first drain electrode connected to the OLED, and a first gate electrode to which a driving signal from the second data line DL2 is applied and supplies a driving current necessary to operate the OLED of the fourth pixel driver. The first source electrode of the fourth driving transistor DTw is connected to the second power line VL2 through the contact hole CH1 and the contact hole CH8. A semiconductor compound layer between the first source electrode and the first drain electrode of the fourth driving transistor DTw is connected through the contact hole CH7 and the contact hole CH8.
A fourth switching transistor T1_W of the fourth pixel driver includes a second source electrode connected to the second data line DL2, a second drain electrode connected to the first gate electrode of the fourth driving transistor DTw, and a second gate electrode connected to the second gate line GL2 and transfers a data voltage supplied through the second data line DL2 to the first gate electrode of the fourth driving transistor DTw. The second source electrode of the fourth switching transistor T1_W is connected to the second data line DL2 through the contact hole CH2. The second drain electrode of the fourth switching transistor T1_W is connected to the first gate electrode of the fourth driving transistor DT_W through the contact hole CH6. The second gate electrode of the fourth switching transistor T1_W is connected to the second gate line GL2.
A fourth sensing transistor T2w of the fourth pixel driver includes a third source electrode connected to the storage capacitor Cst of the fourth pixel driver, a third drain electrode connected to the reference voltage line V_ref, and a third gate electrode connected to the second gate line GL2 and senses a threshold voltage of the fourth driving transistor DT_W according to a signal provided through the second gate line GL2. A semiconductor compound layer between the third source electrode and the third drain electrode of the fourth sensing transistor T2_W is connected through the contact hole CH3 and a contact hole CH4. The third drain electrode of the fourth sensing transistor T2w is connected to the capacitor Cst through the contact hole CH4 and the contact hole CH5 and is connected to the first drain electrode of the fourth driving transistor DTw through the contact hole CH4 and the contact hole CH7.
The first and second data lines DL1 and DL2 include a data line hole CH2 formed to supply a data voltage to each pixel and the first and second gate lines GL1 and GL2 are positioned between the data line hole CH2 and a capacitor region Cap.
The first to fourth pixel drivers included in the display panel according to the present invention have a 1SCAN structure, that is, a configuration in which a switching transistor and a sensing transistor simultaneously operate. Here, voltages and signals supplied to elements of each pixel driver are as shown in FIG. 4. For example, a sampling signal is not supplied for a period in which a data voltage is supplied through a data line among periods in which a first scan pulse signal is provided. Accordingly, a scan transistor is turned on but a sampling transistor is turned off. A data voltage supplied through a data line is blocked and the sampling signal is supplied in another period among the periods in which the first scan signal is provided. Accordingly, the scan transistor is turned off but the sampling transistor is turned on.
Accordingly, the first gate line GL1 carries the same scan pulse signal to the gate electrodes of the first and third switching transistors T1_R and T1_G and the gate electrodes of the first and third sensing transistors T2_R and T2_G of the first and third pixel drivers P1 and P3 and the second gate line GL2 carries the same scan pulse signal to the gate electrodes of the second and fourth switching transistors T1_B and T1_W and the gate electrodes of the second and fourth sensing transistors T2_B and T2_W of the second and fourth pixel drivers P2 and P4.
A data voltage is supplied through the first data line DL1 to the source electrodes of the first and second switching transistors T1_R and T1_B of the first and second pixel drivers P1 and P2, and a data voltage is supplied through the second data line DL2 to the source electrodes of the third and fourth switching transistors T1_G and T1_W of the third and fourth pixel drivers P3 and P4.
The source electrodes of the first to fourth sensing transistors T2_R, T2_B, T2_G and T2w receive a sampling signal through the reference voltage line V_ref.

Claims

A display panel (100) configured to operate in a double rate driving (DRD) manner, comprising:
first to fourth subpixels (P1-P4) each provided on a substrate and including a capacitor region, wherein the first to fourth subpixels constitute a unit pixel;

a first data line (DL1) configured to transmit a data signal to the first and second subpixels (P1, P2);

a second data line (DL2) configured to transmit a data signal to the third and fourth subpixels (P3, P4);

a first gate line (GL1) configured to transmit a scan signal to the first and third subpixels (P1, P3);

a second gate line (GL2) configured to transmit a scan signal to the second and fourth subpixels (P2, P4);

a reference voltage line (V_ref) disposed between the first data line (DL1) and the second data line (DL2);

a first power line (VL1) positioned at a side of the first data line (DL1) facing away from the reference voltage line (V_ref) and configured to supply driving power to the first and second subpixels (P1, P2);

a second power line (VL2) positioned at a side of the second data line (DL2) facing away from the reference voltage line (V_ref) and supplying driving power to the third and fourth subpixels (P3, P4); and

first to fourth driving circuits respectively provided in the first to fourth subpixels (P1-P4), characterized in that the first to fourth driving circuits are disposed between the data lines (DL1, DL2) and the reference voltage line (V_ref);

and in that the unit pixel has a QUAD structure.
The display panel of claim 1, wherein the reference voltage line (V_ref) and the first and second data lines (DL1, DL2) extend in parallel to each other along a first direction, and
wherein the first and second gate lines (GL1, GL2) extend in parallel to each other along a second direction perpendicular to the first direction.
The display panel of any one of the preceding claims, wherein the first and second subpixels (P1, P2) are formed between the first power line (VL1) and the reference voltage line (V_ref) and the third and fourth subpixels (P3, P4) are formed between the reference voltage line (V_ref) and the second power line (VL2).
The display panel of any one of the preceding claims, further comprising data line holes (CH2) connecting the first and second data lines (DL1, DL2) to the first to fourth subpixels (P1-P4) and wherein the first and second gate lines (GL1, GL2) are positioned between the data line holes (CH2) and the capacitor regions (Cap).
The display panel of claim 4, wherein the first gate line (GL1) is positioned between the data line hole (CH2) connecting the first data line (DL1) to the capacitor region of the first subpixel (P1) and the data line hole (CH2) connecting the second data line (DL2) to the capacitor region of the third subpixel (P3), and/or
wherein the second gate line (GL2) is positioned between the data line hole (CH2) connecting the first data line (DL1) to the capacitor region of the second subpixel (P2) and the data line hole (CH2) connecting the second data line (DL2) to the capacitor region of the fourth subpixel (P4).
The display panel of claim 4 or 5, wherein the data line holes (CH2) are arranged between the reference voltage line (V_ref) and the respective data line (DL1, DL2).
The display panel of claim 1, wherein the first driving circuit of the first subpixel (P1) is disposed between the first data line (DL1) and the reference voltage line (V_ref), and the second driving circuit of the second subpixel (P2) is disposed between the first data line (DL1) and the reference voltage line (V_ref), and
wherein the third driving circuit of the third subpixel (P3) is disposed between the second data line (DL2) and the reference voltage line (V_ref), and the fourth driving circuit of the fourth subpixel (P4) is disposed between the second data line (DL2) and the reference voltage line (V_ref).
The display panel of any one of the preceding claims, wherein the first to fourth driving circuits are arranged such that pairs of the first to fourth driving circuits are symmetrically disposed on the basis of the reference voltage line (V_ref).
The display panel of any one of the preceding claims, wherein the first driving circuit of the first subpixel (P1) and the second driving circuit of the second subpixel (P2) are symmetrically disposed on the basis of the reference voltage line (V_ref), and
wherein the third driving circuit of the third subpixel (P3) and the fourth driving circuit of the fourth subpixel (P4) are symmetrically disposed on the basis of the reference voltage line (V_ref).
The display panel of any one of the preceding claims, wherein each of the first to fourth driving circuits includes:
a driving transistor (DT) including a first source electrode connected to the first or second power line (VL1, VL2), a first drain electrode connected to the OLED, and a first gate electrode configured to receive a signal from the first or second data line (DL1, DL2) to cause the OLED to emit light;

a switching transistor (T1) including a second source electrode connected to the first or second data line (DL1), a second drain electrode connected to the first gate electrode, and a second gate electrode connected to the first or second gate line (GL1, GL2) for controlling light emission of the OLED;

a storage capacitor (C_st) provided in the capacitor region between the first drain electrode and the second drain electrode and storing the signal from the first or second data line (DL1, DL2); and

a sensing transistor (T2) including a third source electrode connected to the storage capacitor (C_st), a third drain electrode connected to the reference voltage line (V_ref), and a third gate electrode connected to the first or second gate line (GL1, GL2) for detecting a threshold voltage of the driving transistor (DT) according to a signal from the first or second gate line (GL1, GL2).
An organic light emitting display device configured to operate in a double rate driving (DRD) manner, comprising:
the display panel (100) according to any one of the preceding claims;

a gate driver for (200) configured to sequentially supply a scan pulse signal to gate lines (GL1, GL2) of the display panel (100);

a data driver (300) configured to supply data voltages to the data lines (DL1, DL2) of the display panel (100); and

a timing controller (400) configured to supply control signals to the gate driver (200) and the data driver (300) in a double rate driving (DRD) manner.