KR101755440B1 - inverter and display device including the same - Google Patents

Abstract

According to the present invention, there is provided a semiconductor device comprising: an input terminal to which an input signal is transmitted; a reset terminal to which a reset signal is transmitted; an output terminal to which an output signal is outputted; first to fourth transistors; Wherein the first transistor and the second transistor are connected in series between the first power source and the second power source, and the third transistor and the fourth transistor are serially connected between the first power source and the second power source, A source electrode of the first transistor is connected to a source electrode of the third transistor, a drain electrode of the first transistor is connected to the output terminal and a source electrode of the second transistor, Wherein the gate electrode of the second transistor is connected to the input terminal and the gate electrode of the third transistor, The gate electrode of the second transistor is connected to the drain electrode of the third transistor and the source electrode of the fourth transistor, the gate electrode of the fourth transistor is connected to the reset terminal, And an A node is formed between the drain electrode of the third transistor and the source electrode of the fourth transistor, connected to the gate electrode of the second transistor.

Description

[0001] The present invention relates to an inverter and a display device including the inverter,

The present invention relates to an inverter, and more particularly, to an inverter and a display device including the inverter.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying images have been increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

These flat panel display devices may include a display panel and various driving circuit portions. Further, by configuring an inverter in the display panel and the driving circuit section, driving can be performed more efficiently.

Here, the inverter is an electronic logic gate manufactured by an integrated circuit that inverts a signal to be received, that is, an input signal. Specifically, logic 1 (true) is logic 0 (false) and vice versa. That is, a logical NOT operation is performed.

Further, inverters are generally composed of inverted type transistors (that is, an N-type transistor and a P-type transistor) connected in common to the same input terminal and connected in series.

1 is a circuit diagram showing a conventional inverter.

1, a conventional inverter includes a P-type transistor P and an N-type transistor N connected in series between a first power supply Vdd and a second power supply Vss, (In).

The inverter inverts the input signal Vin input to the input terminal In and outputs the inverted input signal Vin to the output terminal Out.

To this end, the P-type transistor P turned on in response to the low level input signal Vin is connected between the high level first power supply Vdd and the output terminal Out, The N-type transistor N which is turned on in response to the input signal Vin is connected between the second power supply Vss and the output terminal Out of the low level.

However, since the conventional inverter has to form the transistors P and N of the opposite type, the increase of the mask and the increase of the manufacturing cost such as the addition of the processing step are caused. In addition, the process efficiency is deteriorated.

The present invention relates to an inverter and a flat panel display including the same, and has a problem in that output signals are output stably using a single type of transistor.

According to an aspect of the present invention, there is provided a semiconductor memory device including an input terminal to which an input signal is transmitted, a reset terminal to which a reset signal is transmitted, an output terminal to which an output signal is output, 1. An inverter including a first power source and a second power source, wherein the first transistor and the second transistor are connected in series between the first power source and the second power source, and the third transistor and the fourth transistor are connected in series Wherein a source electrode of the first transistor is connected to a source electrode of the third transistor, and a drain electrode of the first transistor is connected to the output terminal and the source of the second transistor, Wherein the gate electrode of the first transistor is connected to the input terminal and the gate electrode of the third transistor, The drain electrode of the fourth transistor is connected to the drain electrode of the fourth transistor, the gate electrode of the second transistor is connected to the drain electrode of the third transistor and the source electrode of the fourth transistor, An electrode is connected to the reset terminal and is connected to the gate electrode of the second transistor and an A node is formed between the drain electrode of the third transistor and the source electrode of the fourth transistor.

Wherein the on period of the input signal is a period during which the first transistor and the third transistor are turned on and a period during which the input signal is off, Turn on.

The reset signal is turned on after the first time after the turning off of the input signal.

The first to fourth transistors are P or N type transistors.

A flat panel display comprising a display panel for displaying an image, comprising: an input terminal to which an input signal is transmitted; a reset terminal to which a reset signal is transmitted; an output terminal to which an output signal is outputted; Wherein the first transistor and the second transistor are connected in series between the first power source and the second power source, the third transistor and the fourth transistor are connected in series between the first power source and the second power source, Wherein a source electrode of the first transistor is connected to a source electrode of the third transistor, a drain electrode of the first transistor is connected to the source electrode of the second transistor, A gate electrode of the first transistor is connected to the input terminal and a gate electrode of the third transistor, The drain electrode of the fourth transistor is connected to the drain electrode of the fourth transistor, the gate electrode of the second transistor is connected to the drain electrode of the third transistor and the source electrode of the fourth transistor, And an inverter connected to the reset terminal and connected to the gate electrode of the second transistor and having the node A between the drain electrode of the third transistor and the source electrode of the fourth transistor.

Wherein the on period of the input signal is a period during which the first transistor and the third transistor are turned on and a period during which the input signal is off, Turn on.

The reset signal is turned on after the first time after the turning off of the input signal.

The first to fourth transistors are P or N type transistors.

The inverter according to the present invention and the flat panel display including the same have the effect of stably outputting an output signal using a single type of transistor.

Further, the duty of the output signal can be adjusted by adjusting the timing of the reset signal.

1 is a circuit diagram of a conventional inverter.
2 is a schematic view of a flat panel display according to an embodiment of the present invention.
3 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
4 is a circuit diagram of an inverter according to an embodiment of the present invention;
5 and 6 are waveform diagrams of an input signal, a reset signal, and an output signal according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a schematic view of a flat panel display according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

First, for convenience of explanation, the organic light emitting display 100 of the flat panel display device 100 will be described as an example.

3, the organic light emitting display 100 includes a display panel 200 and a driving circuit unit 300. The display panel 200 includes a display panel 200 and a driving circuit unit 300.

In the display panel 200, a plurality of gate lines GL extend in the row direction in the first direction, for example. A plurality of data lines DL extend in a second direction that crosses the first direction, for example, in the column direction. The plurality of gate lines GL and the plurality of data lines DL intersecting each other define a plurality of pixels P arranged in a matrix form.

3, a switching transistor TS, a driving transistor TD, an organic light emitting diode OD, and a capacitor C may be formed in each pixel P of the display panel 200 .

The switching transistor TS is connected to the corresponding gate wiring and data lines GL and DL. The driving transistor TD is connected to the switching transistor TS. For example, the gate electrode of the driving transistor TD is connected to the drain electrode of the switching transistor TS.

The organic light emitting diode OD is connected to the driving transistor TD. For example, the first electrode of the organic light emitting diode OD, for example, an anode, is connected to the drain electrode of the driving transistor TD. The second driving voltage VSS is applied to the second electrode of the organic light emitting diode OD, for example, the cathode. For example, the second electrode of the organic light emitting diode OD may be grounded. On the other hand, an organic light-emitting layer including an organic light-emitting material for emitting light is formed between the first and second electrodes.

The organic light emitting layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL).

The capacitor C is connected between the gate electrode and the source electrode of the driving transistor TD. On the other hand, the source electrode of the driving transistor TD receives the first driving voltage VDD.

When the gate line GL is scanned and a gate signal having a turn-on voltage, for example, a gate high voltage, is applied to the pixel P having the above configuration, the switching transistor TS is turned on. Thus, the input data voltage passes through the switching transistor TS and is applied to the gate electrode of the driving transistor TD. Thus, a current is supplied to the organic light emitting diode (OD) through the driving transistor (TD) to emit light having the corresponding color.

The driving circuit unit 300 for driving the display panel 200 includes a timing control unit 310, a gate driving unit 320, a data driving unit 330, a gamma voltage supply unit 340, a power generation unit 350, . ≪ / RTI >

Here, the timing controller 310 receives a video data signal RGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data enable signal from an external system such as a TV system or a video card And receives a control signal TCS such as a signal DE. Meanwhile, although not shown, such signals may be input through an interface configured in the timing controller 310.

The timing controller 310 receives the gate control signal GCS for controlling the gate driver 330 and the data control signal DCS for controlling the data driver 340 using the input control signal TCS. Lt; / RTI >

In addition, the timing controller 310 receives the image data signals RGB from the external system, aligns them, and transmits the image data signals to the data driver 330.

The gate driver 320 can sequentially select the gate line GL in response to the gate control signal GCS supplied from the timing controller 310. [ For the selected gate wiring GL, a gate signal having a turn-on voltage is outputted. Thus, the switching transistor TS of the pixel P connected to the selected gate line GL is turned on. In synchronism with this, the data voltage is output to the data line DL and input to the pixel P.

The data driver 330 generates a data voltage corresponding to the video data signal RGB in response to the data control signal DCS supplied from the timing controller 310. [ Further, the generated data voltage is outputted to the corresponding data line DL.

Therefore, the data driver 330 can output the gradation voltage corresponding to the gradation level of the input image data signal RGB in the digital format as the data voltage using the gamma voltage Vgamma . In this way, the data driver 330 outputs the image data signal RGB in the digital format as image data in an analog format. The data voltage thus outputted is applied to the corresponding data line DL and input to the corresponding pixel P.

The gamma voltage supplier 340 generates the gamma voltage Vgamma. The gamma voltage Vgamma thus generated is supplied to the data driver 330 and used to generate a data voltage corresponding to the video data signal RGB.

The power generating unit 350 generates various driving voltages necessary for driving the organic light emitting display device 100. For example, a power supply voltage supplied to the timing controller 310, the data driver 330 and the gate driver 320, a gate high voltage and a gate low voltage supplied to the gate driver 330 are generated.

In the flat panel display device 100, a plurality of inverters may be used in the display panel 200, the driving circuit unit 300, and the like.

Hereinafter, the inverter according to the embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5. FIG.

4 is an inverter circuit diagram according to an embodiment of the present invention.

Referring to FIG. 4, the inverter according to the embodiment of the present invention may include a plurality of transistors, for example, first to fourth transistors T1 to T4.

Here, as the first to fourth transistors T1 to T4, a P-type transistor is used as an example. On the other hand, it is apparent to those skilled in the art that N-type transistors can be used as the first to fourth transistors T1 to T4. In this case, the signal applied to the inverter and the signal outputted from the inverter can be inverted with the signal of the inverter using the P type transistor as the signal.

The inverter includes an input terminal In receiving the input signal Vin, an output terminal Out for outputting the output signal Vout, a reset terminal Rin receiving the reset signal RSin, .

First, the first transistor T1 and the second transistor T2 are connected in series between the first power source Vdd and the second power source Vss. The third transistor T3 and the fourth transistor T4 are connected in series between the first power source Vdd and the second power source Vss.

The first power source Vdd is a high level voltage source and the second power source Vss is a low level voltage source having a voltage level lower than the first power source Vdd. For example, the second power supply Vss may be set to the ground power supply GND.

More specifically, for example, the source electrode of the first transistor T1 is connected to the first power source Vdd and the source electrode of the third transistor T3, and the drain of the first transistor T1 drain electrode is connected to the output terminal Out and the source electrode of the second transistor T2.

The gate electrode of the first transistor T1 is connected to the gate electrode of the third transistor T3 and the input terminal In.

The source electrode of the second transistor T2 is connected to the output terminal Out. That is, the output terminal Out is connected between the drain electrode of the first transistor T1 and the source electrode of the second transistor T2. The drain electrode of the second transistor T2 is connected to the second power source Vss and the drain electrode of the fourth transistor T4.

The gate electrode of the second transistor T2 is connected to the drain electrode of the third transistor T3 and the source electrode of the fourth transistor T4. That is, the gate electrode of the second transistor T2 is connected between the drain electrode of the third transistor T3 and the source electrode of the fourth transistor T4.

The source electrode of the third transistor T3 is connected to the first power source Vdd and the source electrode of the first transistor T1 while the drain electrode thereof is connected to the gate electrode of the second transistor T2 and the source electrode of the fourth transistor T4. And is connected to the source electrode.

The gate electrode of the third transistor T3 is connected to the input terminal In.

The source electrode of the fourth transistor T4 is connected to the gate electrode of the second transistor T2 and the drain electrode of the third transistor T3 while the drain electrode of the fourth transistor T4 is connected to the drain electrode of the second transistor T2, Vss).

The gate electrode of the fourth transistor T4 is connected to the reset terminal Rin.

Hereinafter, the operation of the inverter according to the embodiment of the present invention will be described with reference to FIG.

5 is a waveform diagram showing waveforms of an input signal Vin, a reset signal RSin, and an output signal Vout of the inverter according to the embodiment of the present invention.

At this time, as described above, in the embodiment of the present invention, a P-type transistor is used as an example.

First, the first transistor T1 and the second transistor T2 are driven in opposite phases.

For example, when the first transistor T1 is turned on, the second transistor T2 is turned off so that the first power source Vdd passes through the first transistor T1 And output to the output terminal Out. On the other hand, when the second transistor T2 is turned on, the first transistor T1 is turned off so that the second power source Vss passes through the second transistor T2 and is output to the output terminal Out.

This will be described in more detail below.

5, in the first section I, an off signal, for example, an input signal Vin of a high level voltage is applied to the input terminal In, and a reset signal is applied to the reset terminal Rin The reset signal RSin of the high level voltage is applied and the output signal Vout of the low level voltage is outputted from the output terminal Out.

More specifically, the input signal Vin of the high level voltage is applied to the input terminal In so that the third transistor T3 and the first transistor T1 connected to the input terminal In are turned off.

Also, the reset signal RSin of the high level voltage is applied to the reset terminal Rin, so that the fourth transistor T4 connected to the reset terminal Rin is turned off.

Thus, the output signal Vout of the low level voltage is outputted from the output terminal Out of the inverter. That is, the low level voltage of the third section III is maintained.

The third transistor T3 and the first transistor T1 are turned on by applying an on signal such as a low level voltage input signal Vin to the input terminal In in the second section II, The output signal Vout of the output terminal Out becomes a high level voltage. That is, the first power supply Vdd is outputted as the output signal Vout.

At this time, an off signal, for example, a reset signal RSin of a high level voltage is held at the reset terminal Rin, so that the fourth transistor T4 and the second transistor T2 are turned off.

Specifically, the fourth transistor T4 is turned off by applying a reset signal RSin of a high level voltage. At this time, the third transistor T3 is turned on, so that a high level voltage source, that is, the first power source Vdd is applied to the A node A, and thus the A node A becomes the high level voltage source. The A node A controls the second transistor T2, and the second transistor T2 is turned off according to the high level voltage of the A node A. [

More specifically, the input signal Vin of the low level voltage is applied to the input terminal In so that the third transistor T3 connected to the input terminal In and the gate electrode of the first transistor T1 are turned on .

Thus, the first power supply Vdd passes through the first transistor T1 and is output to the output terminal Out. That is, the high level voltage is output as the output signal Vout.

When the third transistor T3 is turned on, the first power source Vdd is applied to the node A through the third transistor T3.

The second transistor T2 is turned off by the high level voltage of the node A because the high level voltage source is applied to the node A as described above. That is, the first transistor T1 operates in a reverse phase.

That is, since the gate electrodes of the second transistor T2 and the fourth transistor T4 are turned off, the first power supply Vdd is held at the node A.

Here, although not shown, by further configuring a storage capacitor at the node A, the voltage applied to the node A can be stably maintained until the next frame, for example. Thus, not only can the output signal Vout of the output terminal Out be stably output, but also the power consumption is reduced.

Specifically, for example, the storage capacitor may be located between the A-node A and the gate electrode of the second transistor T2.

In the third section III, an on signal, for example, a reset signal RSin of a low level voltage is applied to the reset terminal Rin, so that the output signal Vout of the output terminal Out becomes a low level voltage. That is, the second power supply Vss is output as the output signal Vout.

At this time, an off signal, for example, an input signal Vin of a high level voltage is applied to the input terminal Vin, so that the gate electrodes of the first transistor T1 and the third transistor T3 are maintained in a turned off state.

More specifically, the fourth transistor T4 and the second transistor T2, which are connected to the reset terminal Rin, are turned on by applying an on signal, for example, a reset signal RSin of a low level voltage to the reset terminal Rin Turn on.

Specifically, when the reset signal RSin of the low level voltage is applied to the reset terminal Rin, the gate electrode of the fourth transistor T4 is turned on. Accordingly, the second power source Vss passes through the fourth transistor T4, and a low-level voltage source, that is, the second power source Vss is applied to the A node A. Thus, the second transistor T2 Turn on.

Also, the second power source Vss passes through the turned-on second transistor T2 and is output to the output terminal Out.

In the first period I after the third period III, the second power source Vss which is the low level voltage is held in the A node A, the second transistor T2 maintains the on state, And the output signal Vout of the low level voltage is outputted from the output terminal Out of the inverter. That is, the low level voltage of the third section III is maintained.

The inverter according to the embodiment of the present invention can change the duty of the output signal Vout by adjusting the on / off timing of the reset signal RSin.

Hereinafter, the operation of the inverter for adjusting the duty of the output signal Vout will be described in more detail with reference to FIG.

6 is a signal waveform diagram for an inverter operation according to another embodiment of the present invention.

At this time, the description of the portion corresponding to Fig. 5 is omitted.

6, in the second-first period (II-1), an on signal, for example, a low level voltage input signal Vin is applied to the input terminal In, The output signal Vout becomes a high level voltage. That is, the first power supply Vdd is outputted as the output signal Vout.

At this time, an OFF signal, for example, a reset signal RSin of a high level voltage is held at the reset terminal Rin, so that the fourth transistor T4 is turned off. As described above, the second transistor T2 is turned off by applying the first power source Vdd to the A node A, which is the high level voltage.

The first transistor T1 and the third transistor T3 are turned off by applying an off signal, for example, an input signal Vin of a high level voltage to the input terminal In in the (2-2) Off.

At this time, an off signal, for example, a reset signal RSin of a high level voltage is held at the reset terminal Rin, so that the fourth transistor T4 is turned off. Further, as described above, the second transistor T2 is turned off by applying the first power supply Vdd to the A node A, which is the high level voltage. Accordingly, all of the first to fourth transistors T1 to T4 are turned off.

Accordingly, the output signal Vout is maintained at the first power source Vdd of the high level voltage output in the (2-1) -th section II-1.

At this time, when the output voltage Vout of the (2-1) -th section II-1 is the second power source Vss which is the low level voltage, the second power source Vss is connected to the -2 as the output signal Vout.

In the third section III, an on signal, for example, a reset signal RSin of a low level voltage is applied to the reset terminal Rin, so that the output signal Vout of the output terminal Out becomes a low level voltage do. That is, the second power supply Vss is output as the output signal Vout.

At this time, an off signal, for example, an input signal Vin of a high level voltage is applied to the input terminal Vin so that the first transistor T1 and the third transistor T3 are maintained in a turned off state.

Here, after the input signal Vin of the low level voltage is applied to the input terminal In, the reset signal RSin of the low level voltage is applied to the reset terminal Rin with the time difference t, The output signal Vout of the high level voltage of the output terminal Out can be further maintained by the time difference t.

Thus, the time of the output signal Vout of the output terminal Out can be adjusted. That is, the ratio of the output signal Vout of the high level voltage to the total output time of the output signal Vout can be adjusted.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: Flat panel display device 200: Display panel
Vin: Input signal Vout:: Output signal RSin: Reset signal
In: Input terminal Out: Output terminal Rin: Reset terminal

Claims (9)

A reset terminal to which an input signal is transmitted, a reset terminal to which a reset signal is transmitted, an output terminal to which an output signal is output, first to fourth transistors, a storage capacitor, an inverter including a first power source and a second power source In this case,
Wherein the first transistor and the second transistor are serially connected between the first power supply and the second power supply,
Wherein the third transistor and the fourth transistor are serially connected between the first power source and the second power source,
A source electrode of the first transistor is connected to a source electrode of the third transistor, a drain electrode of the first transistor is connected to the output terminal and a source electrode of the second transistor, A second transistor connected between the input terminal and the gate electrode of the third transistor,
A drain electrode of the second transistor is connected to a drain electrode of the fourth transistor, a gate electrode of the second transistor is connected to one electrode of the storage capacitor,
The drain electrode of the third transistor is connected to the other electrode of the storage capacitor and the source electrode of the fourth transistor,
And a gate electrode of the fourth transistor is connected to the reset terminal
inverter.
The method according to claim 1,
The first transistor and the third transistor are turned on during an on period of the input signal,
Wherein when the input signal is turned off, an on period of the reset signal is turned on and the fourth transistor is turned on
inverter.
The method according to claim 1,
The first transistor and the third transistor are turned on during an on period of the input signal,
After the input signal is turned off, the reset signal is turned on after the first time
inverter.
The method according to claim 1,
The first to fourth transistors are P or N type transistors
inverter.
A flat panel display comprising a display panel for displaying an image,
A first transistor, a storage capacitor, a first power source, and a second power source, wherein the first power source and the second power source are connected to each other,
Wherein the first transistor and the second transistor are serially connected between the first power supply and the second power supply,
Wherein the third transistor and the fourth transistor are serially connected between the first power source and the second power source,
A source electrode of the first transistor is connected to a source electrode of the third transistor, a drain electrode of the first transistor is connected to the output terminal and a source electrode of the second transistor, A second transistor connected between the input terminal and the gate electrode of the third transistor,
A drain electrode of the second transistor is connected to a drain electrode of the fourth transistor, a gate electrode of the second transistor is connected to one electrode of the storage capacitor,
The drain electrode of the third transistor is connected to the other electrode of the storage capacitor and the source electrode of the fourth transistor,
And a gate electrode of the fourth transistor is connected to the reset terminal
A flat panel display comprising an inverter.
6. The method of claim 5,
The first transistor and the third transistor are turned on during an on period of the input signal,
Wherein when the input signal is turned off, an ON period of the reset signal is turned on and the fourth transistor is turned on
A flat panel display comprising an inverter.
6. The method of claim 5,
The first transistor and the third transistor are turned on during an on period of the input signal,
After the input signal is turned off, the reset signal is turned on after the first time
A flat panel display comprising an inverter.
6. The method of claim 5,
The first to fourth transistors are P or N type transistors
A flat panel display comprising an inverter. The method according to claim 1,
The output signal has a high level voltage in a period from a time point when the input signal is turned on to a point in time when the reset signal is turned on and has a low level voltage in the remaining period
inverter.

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