EP3743857A4 - Neural network circuits having non-volatile synapse arrays - Google Patents
Neural network circuits having non-volatile synapse arrays Download PDFInfo
- Publication number
- EP3743857A4 EP3743857A4 EP19744289.0A EP19744289A EP3743857A4 EP 3743857 A4 EP3743857 A4 EP 3743857A4 EP 19744289 A EP19744289 A EP 19744289A EP 3743857 A4 EP3743857 A4 EP 3743857A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- neural network
- network circuits
- synapse arrays
- volatile synapse
- volatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/048—Activation functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5614—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Health & Medical Sciences (AREA)
- Biophysics (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Artificial Intelligence (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Neurology (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862620947P | 2018-01-23 | 2018-01-23 | |
US201862655074P | 2018-04-09 | 2018-04-09 | |
US16/196,617 US11361215B2 (en) | 2017-11-29 | 2018-11-20 | Neural network circuits having non-volatile synapse arrays |
US16/252,640 US11361216B2 (en) | 2017-11-29 | 2019-01-20 | Neural network circuits having non-volatile synapse arrays |
PCT/US2019/014442 WO2019147522A2 (en) | 2018-01-23 | 2019-01-22 | Neural network circuits having non-volatile synapse arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3743857A2 EP3743857A2 (en) | 2020-12-02 |
EP3743857A4 true EP3743857A4 (en) | 2021-12-29 |
Family
ID=67395562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19744289.0A Pending EP3743857A4 (en) | 2018-01-23 | 2019-01-22 | Neural network circuits having non-volatile synapse arrays |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP3743857A4 (en) |
KR (1) | KR102567160B1 (en) |
CN (1) | CN111656371B (en) |
TW (1) | TWI751403B (en) |
WO (1) | WO2019147522A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11694751B2 (en) | 2019-11-30 | 2023-07-04 | Semibrain Inc. | Logic compatible flash memory programming with a pulse width control scheme |
US11636322B2 (en) * | 2020-01-03 | 2023-04-25 | Silicon Storage Technology, Inc. | Precise data tuning method and apparatus for analog neural memory in an artificial neural network |
US11475946B2 (en) * | 2020-01-16 | 2022-10-18 | International Business Machines Corporation | Synapse weight update compensation |
US11663455B2 (en) * | 2020-02-12 | 2023-05-30 | Ememory Technology Inc. | Resistive random-access memory cell and associated cell array structure |
CN112465128B (en) * | 2020-11-30 | 2024-05-24 | 光华临港工程应用技术研发(上海)有限公司 | Neuronal network element |
CN113655993A (en) * | 2021-03-17 | 2021-11-16 | 神盾股份有限公司 | Product-sum computation device |
CN113793631A (en) * | 2021-08-03 | 2021-12-14 | 特忆智能科技 | Apparatus for controlling RRAM device using feedback circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0644597A1 (en) * | 1992-06-03 | 1995-03-22 | SHIBATA, Tadashi | Semiconductor device |
US20030183871A1 (en) * | 2002-03-22 | 2003-10-02 | Dugger Jeffery Don | Floating-gate analog circuit |
US7167392B1 (en) * | 2005-07-15 | 2007-01-23 | National Semiconductor Corporation | Non-volatile memory cell with improved programming technique |
US20160048755A1 (en) * | 2014-08-14 | 2016-02-18 | The Regents Of The University Of Michigan | Floating-gate transistor array for performing weighted sum computation |
WO2017078886A1 (en) * | 2015-11-05 | 2017-05-11 | Qualcomm Incorporated | Generic mapping for tracking target object in video sequence |
EP3718055A1 (en) * | 2017-11-29 | 2020-10-07 | Anaflash Inc. | Neural network circuits having non-volatile synapse arrays |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277871A (en) * | 1988-06-14 | 1990-03-16 | Mitsubishi Electric Corp | Neural network |
US4956564A (en) * | 1989-07-13 | 1990-09-11 | Intel Corporation | Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network |
US5353382A (en) * | 1990-10-15 | 1994-10-04 | California Institute Of Technology | Programmable synapse for neural network applications |
US5336937A (en) * | 1992-08-28 | 1994-08-09 | State University Of New York | Programmable analog synapse and neural networks incorporating same |
US5721704A (en) * | 1996-08-23 | 1998-02-24 | Motorola, Inc. | Control gate driver circuit for a non-volatile memory and memory using same |
US10478115B2 (en) * | 2004-10-04 | 2019-11-19 | Spirofriend Technology Aps | Handheld home monitoring sensors network device |
US7656710B1 (en) * | 2005-07-14 | 2010-02-02 | Sau Ching Wong | Adaptive operations for nonvolatile memories |
US8515885B2 (en) * | 2010-10-29 | 2013-08-20 | International Business Machines Corporation | Neuromorphic and synaptronic spiking neural network with synaptic weights learned using simulation |
WO2013108299A1 (en) * | 2012-01-20 | 2013-07-25 | パナソニック株式会社 | Learning method for neural network circuit |
KR20130133111A (en) * | 2012-05-28 | 2013-12-06 | 송승환 | Pure logic compatible flash memory |
JP6276296B2 (en) * | 2013-03-14 | 2018-02-07 | マイクロン テクノロジー, インク. | Memory system and method including training, data reconstruction and / or shadowing |
CN104240753B (en) * | 2013-06-10 | 2018-08-28 | 三星电子株式会社 | Cynapse array, pulse shaper and neuromorphic system |
FR3016724B1 (en) * | 2014-01-22 | 2016-02-05 | Commissariat Energie Atomique | NON-VOLATILE MULTIPORT MEMORY |
US9934831B2 (en) * | 2014-04-07 | 2018-04-03 | Micron Technology, Inc. | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters |
GB201419355D0 (en) * | 2014-10-30 | 2014-12-17 | Ibm | Neuromorphic synapses |
US9881253B2 (en) * | 2014-11-07 | 2018-01-30 | International Business Machines Corporation | Synaptic neural network core based sensor system |
US9715916B1 (en) * | 2016-03-24 | 2017-07-25 | Intel Corporation | Supply-switched dual cell memory bitcell |
KR20170117863A (en) * | 2016-04-14 | 2017-10-24 | 에스케이하이닉스 주식회사 | Neuromorphic Device Including Synapses Having Fixed Resistance |
WO2017200883A1 (en) * | 2016-05-17 | 2017-11-23 | Silicon Storage Technology, Inc. | Deep learning neural network classifier using non-volatile memory array |
-
2019
- 2019-01-22 EP EP19744289.0A patent/EP3743857A4/en active Pending
- 2019-01-22 CN CN201980009706.5A patent/CN111656371B/en active Active
- 2019-01-22 KR KR1020207024195A patent/KR102567160B1/en active IP Right Grant
- 2019-01-22 WO PCT/US2019/014442 patent/WO2019147522A2/en unknown
- 2019-01-23 TW TW108102597A patent/TWI751403B/en active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0644597A1 (en) * | 1992-06-03 | 1995-03-22 | SHIBATA, Tadashi | Semiconductor device |
US20030183871A1 (en) * | 2002-03-22 | 2003-10-02 | Dugger Jeffery Don | Floating-gate analog circuit |
US7167392B1 (en) * | 2005-07-15 | 2007-01-23 | National Semiconductor Corporation | Non-volatile memory cell with improved programming technique |
US20160048755A1 (en) * | 2014-08-14 | 2016-02-18 | The Regents Of The University Of Michigan | Floating-gate transistor array for performing weighted sum computation |
WO2017078886A1 (en) * | 2015-11-05 | 2017-05-11 | Qualcomm Incorporated | Generic mapping for tracking target object in video sequence |
EP3718055A1 (en) * | 2017-11-29 | 2020-10-07 | Anaflash Inc. | Neural network circuits having non-volatile synapse arrays |
Also Published As
Publication number | Publication date |
---|---|
WO2019147522A3 (en) | 2020-04-09 |
KR102567160B1 (en) | 2023-08-16 |
TW201937413A (en) | 2019-09-16 |
CN111656371A (en) | 2020-09-11 |
CN111656371B (en) | 2024-06-04 |
EP3743857A2 (en) | 2020-12-02 |
KR20200110701A (en) | 2020-09-24 |
WO2019147522A2 (en) | 2019-08-01 |
TWI751403B (en) | 2022-01-01 |
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