EP3743857A4 - Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays - Google Patents

Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays Download PDF

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Publication number
EP3743857A4
EP3743857A4 EP19744289.0A EP19744289A EP3743857A4 EP 3743857 A4 EP3743857 A4 EP 3743857A4 EP 19744289 A EP19744289 A EP 19744289A EP 3743857 A4 EP3743857 A4 EP 3743857A4
Authority
EP
European Patent Office
Prior art keywords
neural network
network circuits
synapse arrays
volatile synapse
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19744289.0A
Other languages
English (en)
French (fr)
Other versions
EP3743857A2 (de
Inventor
Seung-Hwan Song
Ji Hye Hur
Sang-Soo Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anaflash Inc
Original Assignee
Anaflash Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/196,617 external-priority patent/US11361215B2/en
Application filed by Anaflash Inc filed Critical Anaflash Inc
Publication of EP3743857A2 publication Critical patent/EP3743857A2/de
Publication of EP3743857A4 publication Critical patent/EP3743857A4/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5614—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
EP19744289.0A 2018-01-23 2019-01-22 Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays Pending EP3743857A4 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862620947P 2018-01-23 2018-01-23
US201862655074P 2018-04-09 2018-04-09
US16/196,617 US11361215B2 (en) 2017-11-29 2018-11-20 Neural network circuits having non-volatile synapse arrays
US16/252,640 US11361216B2 (en) 2017-11-29 2019-01-20 Neural network circuits having non-volatile synapse arrays
PCT/US2019/014442 WO2019147522A2 (en) 2018-01-23 2019-01-22 Neural network circuits having non-volatile synapse arrays

Publications (2)

Publication Number Publication Date
EP3743857A2 EP3743857A2 (de) 2020-12-02
EP3743857A4 true EP3743857A4 (de) 2021-12-29

Family

ID=67395562

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19744289.0A Pending EP3743857A4 (de) 2018-01-23 2019-01-22 Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays

Country Status (4)

Country Link
EP (1) EP3743857A4 (de)
KR (1) KR102567160B1 (de)
TW (1) TWI751403B (de)
WO (1) WO2019147522A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11694751B2 (en) 2019-11-30 2023-07-04 Semibrain Inc. Logic compatible flash memory programming with a pulse width control scheme
US11636322B2 (en) * 2020-01-03 2023-04-25 Silicon Storage Technology, Inc. Precise data tuning method and apparatus for analog neural memory in an artificial neural network
US11475946B2 (en) * 2020-01-16 2022-10-18 International Business Machines Corporation Synapse weight update compensation
US11663455B2 (en) * 2020-02-12 2023-05-30 Ememory Technology Inc. Resistive random-access memory cell and associated cell array structure
CN113655993A (zh) * 2021-03-17 2021-11-16 神盾股份有限公司 乘积和运算装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644597A1 (de) * 1992-06-03 1995-03-22 SHIBATA, Tadashi Halbleitervorrichtung.
US20030183871A1 (en) * 2002-03-22 2003-10-02 Dugger Jeffery Don Floating-gate analog circuit
US7167392B1 (en) * 2005-07-15 2007-01-23 National Semiconductor Corporation Non-volatile memory cell with improved programming technique
US20160048755A1 (en) * 2014-08-14 2016-02-18 The Regents Of The University Of Michigan Floating-gate transistor array for performing weighted sum computation
WO2017078886A1 (en) * 2015-11-05 2017-05-11 Qualcomm Incorporated Generic mapping for tracking target object in video sequence
EP3718055A1 (de) * 2017-11-29 2020-10-07 Anaflash Inc. Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956564A (en) * 1989-07-13 1990-09-11 Intel Corporation Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network
US5353382A (en) * 1990-10-15 1994-10-04 California Institute Of Technology Programmable synapse for neural network applications
US5336937A (en) * 1992-08-28 1994-08-09 State University Of New York Programmable analog synapse and neural networks incorporating same
US10478115B2 (en) * 2004-10-04 2019-11-19 Spirofriend Technology Aps Handheld home monitoring sensors network device
US7656710B1 (en) * 2005-07-14 2010-02-02 Sau Ching Wong Adaptive operations for nonvolatile memories
KR20130133111A (ko) * 2012-05-28 2013-12-06 송승환 순수 로직 트랜지스터로 구성된 플래시 메모리
KR101752583B1 (ko) * 2013-03-14 2017-07-11 마이크론 테크놀로지, 인크. 트레이닝, 데이터 조직, 및/또는 섀도잉을 포함하는 메모리 시스템들 및 방법들
FR3016724B1 (fr) * 2014-01-22 2016-02-05 Commissariat Energie Atomique Memoire non volatile multiport
US9934831B2 (en) * 2014-04-07 2018-04-03 Micron Technology, Inc. Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters
US9715916B1 (en) * 2016-03-24 2017-07-25 Intel Corporation Supply-switched dual cell memory bitcell
KR20170117863A (ko) * 2016-04-14 2017-10-24 에스케이하이닉스 주식회사 고정된 저항 값들을 갖는 시냅스들을 포함하는 뉴로모픽 소자
KR102182583B1 (ko) * 2016-05-17 2020-11-24 실리콘 스토리지 테크놀로지 인크 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644597A1 (de) * 1992-06-03 1995-03-22 SHIBATA, Tadashi Halbleitervorrichtung.
US20030183871A1 (en) * 2002-03-22 2003-10-02 Dugger Jeffery Don Floating-gate analog circuit
US7167392B1 (en) * 2005-07-15 2007-01-23 National Semiconductor Corporation Non-volatile memory cell with improved programming technique
US20160048755A1 (en) * 2014-08-14 2016-02-18 The Regents Of The University Of Michigan Floating-gate transistor array for performing weighted sum computation
WO2017078886A1 (en) * 2015-11-05 2017-05-11 Qualcomm Incorporated Generic mapping for tracking target object in video sequence
EP3718055A1 (de) * 2017-11-29 2020-10-07 Anaflash Inc. Schaltungen neuronaler netze mit nichtflüchtigen synapsenarrays

Also Published As

Publication number Publication date
EP3743857A2 (de) 2020-12-02
WO2019147522A3 (en) 2020-04-09
TWI751403B (zh) 2022-01-01
KR102567160B1 (ko) 2023-08-16
WO2019147522A2 (en) 2019-08-01
CN111656371A (zh) 2020-09-11
KR20200110701A (ko) 2020-09-24
TW201937413A (zh) 2019-09-16

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