KR102567160B1 - Neural network circuit with non-volatile synaptic array - Google Patents

Abstract

The present invention discloses a synaptic circuit of a non-volatile neural network. A synapse is a reference signal line and an input signal line; a reference signal line; Cells for generating output lines and output signals. The cell includes an upper select transistor having a gate electrically connected to the input signal line; and a resistance change element having one end connected in series to the upper select transistor and the other end electrically connected to the reference signal line and the reference signal line. The value of the resistance change element can be programmed to change the magnitude of the output signal of the upper selection transistor. A drain of the upper select transistor is electrically connected to the first output line.

Description

Neural network circuit with non-volatile synaptic array

The present invention relates to a neural network circuit, and more particularly to a neural network circuit having non-volatile synaptic arrays using analog values.

An Artificial Neural Network (ANN) is a neural network that mimics the computational model of the human brain. A neural network can be described as many neurons connected to each other through synapses between them. The strength of the connection or the weight parameter of each synapse is a trainable parameter and can be adjusted through a learning process. Recently, artificial intelligence (AI) using ANNs has been applied to various fields such as visual and voice detection/recognition, language translation, games, medical decision-making, financial or weather forecasting, drones, and autonomous vehicles.

Traditionally, computation of neural networks requires high-performance cloud servers with multiple Central Processing Units (CPUs) and/or Graphics Processing Units (GPUs). This is because computational complexity prohibits running AI programs locally due to the limited power and computational resources of mobile devices. Other existing application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) approaches that speed up the computation of neural networks with dedicated CMOS (Complementary Metal-O × ide-Semiconductor) logic are conventional CPU- and GPU-based approaches. It can be power efficient compared to the method. However, it still wastes unnecessary power and latency to transmit and receive data to and from a separate off-chip non-volatile memory (NVM) in which the trained weight parameters are stored. Thus, there is a need for neural network circuits that consume significantly less computational resources.

According to another embodiment of the present invention, a synaptic circuit of a non-volatile neural network includes an input signal line, a reference signal line, an output line, and a cell for generating an output signal. The cell includes an upper select converter having a gate electrically connected to the input signal line, and a resistive change element having one end connected in series to the upper select transistor and the other end electrically connected to the reference signal line. The value of the resistive change element can be programmed to change the magnitude of the output signal. The drain of the upper select transistor is electrically connected to the output line.

According to another embodiment of the present invention, a synapse circuit includes first and second input signal lines, a reference signal line, first and second output signal lines, first and second cells, and a cross-coupled latch circuit. The cross-coupled latch circuit includes first and second inverters and first and second signal nodes. The input terminal of the first inverter is connected to the output terminal of the second inverter at the first signal node and the input terminal of the second inverter is connected to the output terminal of the first inverter at the second signal node. Each cell includes a first upper select transistor electrically connected at a gate to the first input signal line, and a second upper select transistor connected to the second input signal line. Source terminals of the first and second upper select transistors are connected to a common node. In the first cell, drain terminals of the first and second upper select transistors are respectively connected to the first and second output signal lines. In the second cell, the drain terminal is inverted with the first upper select transistor connected to the second output line and the second upper select transistor connected to the first output line. The common node of the first cell is connected to the first signal node of the cross-coupled latch circuit and the common node of the second cell is connected to the second signal node of the cross-coupled latch circuit. Reference signal line. coupled to first and second inverters of a cross-coupled latch circuit.

This privacy-enhanced neural network in an embodiment may be used in creative personal devices. For example, according to one embodiment of the present invention, a new personal task, question or answer may be generated by interaction in a portable educational device or smart toy using an on-chip non-volatile neural network. An embodiment of the present invention may be useful for identifying individuals through image or sound recognition while restricting off-chip access. In particular, home care or child care devices may not require very complex neural network models due to the limited number of people who need to recognize voices. However, these devices may require a high degree of personalization and may have stringent requirements for privacy. In addition, since the core neural network layer for this type of application can be executed without off-chip communication of critical information, an on-chip non-volatile neural network according to an embodiment of the present invention will improve the security of military devices or network firewalls. can

In another aspect of the present invention, the proposed on-chip non-volatile neural network system can be used in a secure personalized vision/motion/voice recognition device by storing and calculating personalization information on-chip. For example, since all neural network calculations are performed on-chip, the device can recognize a specific person's gesture or voice without sending personally trained neural network parameters off-chip. Such visual/motion/voice recognition neural network devices can replace bulky user interface devices (eg, PC keyboards or mice, TV remote controllers). For example, a keyboard touch display could be replaced with a neural network engine capable of recognizing the device owner's hand gestures for each text character. By storing personalized information in an on-chip non-volatile neural network, only specific people can interact with the device.

In addition, the proposed on-chip non-volatile neural network can be utilized to improve the performance and reliability of other SoC building blocks such as CPU, memory and sensor. Due to various operating conditions, such as temperature or aging effects of transistors, the operating voltage and frequency need to be adaptively controlled over the lifetime of the SoC. Manual tuning of these parameters is a difficult task for neural networks to optimize. However, off-chip neural network accelerators may not meet performance requirements and require excessive additional power. Non-volatile neural networks can be used to optimize these parameters of different components of its own chip for given performance and power requirements.

Reference will be made to embodiments of the present invention, examples of which may be shown in the accompanying drawings. These drawings are intended to be illustrative rather than restrictive. Although the present invention has been generally described with respect to these embodiments, it should be understood that the scope of the present invention is not intended to be limited to these specific embodiments.
1 shows a schematic diagram of a neural network according to an embodiment of the present invention.
2 shows a schematic diagram of a synapse array according to an embodiment of the present invention.
3 shows a schematic diagram of a synapse according to an embodiment of the present invention.
4 shows a schematic diagram of another synapse according to an embodiment of the present invention.
5 shows a schematic diagram of another synapse according to an embodiment of the present invention.
6 shows a schematic diagram of another synapse according to an embodiment of the present invention.
7 shows a schematic diagram of another synapse according to an embodiment of the present invention.
8 shows a schematic diagram of another synapse according to an embodiment of the present invention.
9A to 9B show a comparison between a conventional method for programming the threshold voltage (VTH) and a method according to an embodiment of the present invention.
10A to 10B show another method for programming the threshold voltage (VTH) of a floating gate node according to an embodiment of the present invention.
11 shows a flow diagram of an exemplary process for programming the threshold voltage (VTH) of a floating gate node in accordance with an embodiment of the present invention.
12a to 12c illustrate differential signaling according to an embodiment of the present invention.
13 shows a schematic diagram of a chip containing a neural network according to an embodiment of the present invention.
14 shows a schematic diagram of a neural network including a non-volatile synapse array according to an embodiment of the present invention.
15 shows a schematic diagram of another synapse according to an embodiment of the present invention.
FIG. 16 tabulates signals of the input and output lines shown in FIG. 15 for performing binary multiplication according to an embodiment of the present invention.
17 shows a schematic diagram of another synapse according to an embodiment of the present invention.
18 shows a schematic diagram of another synapse according to an embodiment of the present invention.
19 shows a schematic diagram of another synapse according to an embodiment of the present invention.
20 shows a schematic diagram of another synapse according to an embodiment of the present invention.
21 shows a schematic diagram of another synapse according to an embodiment of the present invention.
22 shows a schematic diagram of another synapse according to an embodiment of the present invention.
23 shows a schematic diagram of a neural network system according to the prior art.
24 shows a schematic diagram of a layered neural network computing system composed of an SoC including an on-chip non-volatile neural network and an external neural network accelerator device according to an embodiment of the present invention.
25 shows a schematic diagram of a distributed neural network system composed of multiple SoCs according to an embodiment of the present invention.
26 shows a schematic diagram of a logic-friendly NVM integrated neural network system according to an embodiment of the present invention.
27 shows a schematic diagram of another logic-friendly NVM integrated neural network system according to an embodiment of the present invention.

In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these details. Those skilled in the art will recognize that the embodiments of the invention described below can be carried out in a variety of ways and using a variety of means. Those skilled in the art will also recognize that additional modifications, applications and embodiments are within its scope, as well as additional areas in which the present invention may provide utility. Accordingly, the following examples are intended to illustrate specific embodiments of the invention and to avoid obscuring the invention.

Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrases “in one embodiment,” “in an embodiment,” and the like in various places in this specification are not all referring to the same embodiment.

1 shows a schematic diagram of a neural network 100 in accordance with embodiments of the present invention (like reference numbers throughout the specification indicate like elements). As shown, the neural network 100 includes five neuron array layers (or simply neuron layers) (110, 130, 150, 170, 190), and synapse array layers (or simply synapse layers) (120, 140, 160, 180) may be included. Each of the neuronal layers (eg, 110) may include any suitable number of neurons. In Figure 1, only 5 neuronal layers and 4 synaptic layers are shown. However, it will be apparent to those skilled in the art that neural network 100 may include any other suitable number of neuronal layers and that a synaptic layer may be disposed between two adjacent neuronal layers.

Each neuron (eg, 112a) in the neuron layer (eg, 110) is connected to one of the following neuron array layers (eg, 130) through m synapses of the synaptic layer (eg, 120). It may be connected to more than one neuron (eg, 132a to 132m). For example, if each neuron of the neuron layer 110 is electrically connected to all neurons of the neuron layer 130, the synapse layer 120 may include n×m synapses. In an embodiment, each synapse may have a trainable weight parameter (w) representing the strength of a connection between two neurons.

In an embodiment, the relationship between the input neuron signal Ain and the output neuron signal Aout may be expressed as an activation function of the following equation.

[Equation 1]

Aout=f(W × Ain + Bias)

Here, Ain and Aout are matrices representing the input signal to and output signals from the synaptic layer, respectively, W is a matrix representing the weight of the synaptic layer, and Bias is a matrix representing the bias signal for Aout. In embodiments, W and Bias may be trainable parameters and may be stored in logic friendly non-volatile memory (NVM). For example, a training/machine learning process can be used with known data to determine W and Bias. In embodiments, function f may be a non-linear function such as sigmoid, tanh, ReLU, leaky ReLU, and the like. In embodiments, Aout may be activated when (W x Ain + Bias) is greater than a certain threshold.

As an example, the relationship shown in Equation 1 can be described as a neuron layer 110 having two neurons, a synapse layer 120 and a neuron layer 130 having three neurons. In this example, Ain representing the output signal from the neuron array layer 110 can be expressed as a matrix of 2 rows × 1 column, and Aout representing the output signal from the synaptic layer 120 is a matrix of 3 rows × 1 column. W, which represents the weight of the synapse layer 120, can be expressed as a matrix of 3 rows × 2 columns with 6 weights, and Bias, which represents the bias value added to the neuron layer 130, is 3 rows × 2 columns. It can be expressed as a matrix of one column. The nonlinear function f applied to each element of (W × Ain + Bias) in Equation 1 may determine the final value of each element of Aout. As another example, the neuron array layer 110 may receive input signals from sensors, and the neuron array layer 190 may display a response signal.

In an embodiment, there may be numerous neurons and synapses in neural network 100, and matrix multiplication and summation in Equation 1 may be a process that may consume a large amount of computing resources. In conventional in-memory processing computing approaches, a computing device performs matrix multiplication within an NVM cell array using analog electrical values rather than using digital logic and arithmetic components. These conventional designs aim to reduce the computational load and reduce power requirements by reducing communication between CMOS logic and NVM components. However, these conventional approaches tend to have a large change in the current input signal for each synapse because the resistance component to the current input signal path is large in a large-scale NVM cell array. In addition, leakage current through half-selected cells in a large array changes the programmed resistance value, causing unwanted program perturbation and degradation of neural network calculation accuracy.

Unlike conventional approaches, in embodiments, a power efficient neural network may be based on a logic-friendly non-volatile synapse with a differential structure, where the differential structure may include a select transistor and a logic-friendly NVM. In embodiments, a fully differential synaptic structure can broaden the operating range of a synaptic circuit as a multiplier. Compared to conventional structures, in embodiments a slight multiplication error can be beneficial to compensate for a certain level of quantization noise of a trained weight parameter.

As will be described later, in embodiments, an input signal to each synapse of the synaptic layers 120, 140, 160, and 180 is directed to a gate terminal of a select transistor of the synapse, so that multiplication noise can be suppressed. In embodiments, the multiplier current may be approximately the product of the gate terminal voltage and the resistance level of the variable resistor or NVM.

2 shows a schematic diagram of a synapse array 200 according to embodiments of the present invention. As shown, the synapse array 200 includes non-volatile synapses 210 arranged in rows and columns, positive output current lines 266 electrically connected to the column selection transistor 263, respectively; It may include negative output current lines (Bit Line Bar lines) 267 electrically connected to the column selection transistor 268, respectively. In embodiments, the drain terminal of the column selection transistor 263 may be electrically connected to the positive current port 241 of the sensing circuit 250, and the drain terminal of the column selection transistor 268 may be connected to the positive current port 241 of the sensing circuit 250. It may be electrically connected to the negative current port 242 .

In embodiments, each non-volatile synapse 210 may store one positive weight and one negative weight. In embodiments, each non-volatile synapse 210 includes a signal line (or equivalently a reference signal line) (e.g., SL1) 264 for receiving a reference voltage input 201 and a signal voltage input A word line (or equally input signal line) (e.g., WL1) 265 for receiving 202 and a positive output line (e.g., BL1) for outputting the positive current output 203 ( 266) and a negative output line (eg, BLB1) 267 for outputting the negative current output 204.

In embodiments, each of the signal voltage input 202 and the reference voltage input 201 may be associated with both positive and negative weights, and the positive current output 203 may be associated with a positive weight, and the negative current output ( 204) may be associated with a negative weight.

In embodiments, a positive (or negative) weight stored in each non-volatile synapse 210 may be expressed as a reciprocal of a variable resistance value, and the values of the signal voltage input 202 and the reference voltage input 201 are electrical can be a voltage value. In embodiments, the value of positive current output 203 can be the result of multiplying the positive weight value by the signal voltage input 202, and the value of negative current output 204 can be the result of multiplying the negative weight value by the signal voltage input 202. may be the result of multiplying

As shown in Figure 2, each row of the non-volatile synapse array 200 may share a reference voltage line (SL, 264) and a signal voltage line (WL, 265), where each SL corresponds to one row It is possible to provide a reference voltage input 201 to non-volatile synapses of a row, and each WL provides a signal voltage input 202 to a corresponding row of non-volatile synapses, so that a row of non-volatile synapses is substantially It is possible to receive the same signal voltage input and the same reference voltage input.

As described above, each column of the non-volatile synapse array 200 may share a positive output current line (BL) 266 and a negative output current line (BL-Bar) 267. That is, each positive current output 203 of a row of synapses can be collected by a corresponding BL 266, and each negative current output 204 of a row of synapses is connected to a corresponding BL-Bar line 267. can be collected by Thus, the electrical current on BL line 266 can be the sum of the positive electrical output currents 203 from a row of synapses. Similarly, in an embodiment, the electrical current value on BL-Bar line 267 may be the sum of the negative electrical output currents 204 from a row of synapses.

In embodiments, each positive output current line (BL-Bar) 266 may be electrically connected to a source terminal of a corresponding column select transistor 263, and each negative output current line (BL-Bar) 267 may be electrically connected to the source terminal of the corresponding column selection transistor 268 . In embodiments, the column selection transistors of the pair of BL and BL-Bar lines 263 and 268 may receive the same column selection signal at their gate terminals from an external column selection circuit (not shown in FIG. 2). . In embodiments, the line of the drain terminal of the column selection transistor 263 may be electrically connected to the positive current input 241 of the sensing circuit 250 . In embodiments, the line of the drain terminal of the column select transistor 268 may be electrically connected to the negative current input 242.

In embodiments, the electrical current value IBL 261 of the positive current port 241 may be the value of the positive output current BL 266 receiving the column select signal on each column select transistor 263 . Similarly, the electrical current value (IBL-bar) 262 of the negative current input 242 may be the negative output current line BL-Bar 267 receiving the column selection signal on each column selection transistor 268.

In embodiments, one or more rows of synapses 210 may have fixed input signal voltages on WLs 265, and synapses in that row may store bias values for that column. In embodiments, the array of synapses may implement matrix multiplication of Equation 1.

W × Ain + Bias

Here, W may be a synapse array, and the Ain matrix represents the WL input.

In embodiments, each non-volatile synapse 210 may have two circuits (or equivalent cells) that store negative and positive weights. In embodiments, as described above, the weights may be expressed as reciprocal values of variable resistors, l/Rn = W_neg and l / Rp = W_pos, respectively. Each row of the synapses of the array 200 may receive an input signal as an electric voltage, Ain. In response to an input signal, each synapse of the array 200 may generate a positive output current through the BL (e.g., BL0 266) and a negative output current through the BLB (e.g., 267); , where the value of the positive output current BLc can be expressed as BLc = Ain × W_pos and the negative output current BLBc can be expressed as BLBc = Ain × W_neg.

In embodiments, the weight W for each synaptic layer of the neural network 100 may be determined (calculated and adjusted) in a separate training step. Then, during the inference step, the input signals Ain may be applied to the neural network 100, where predetermined weights may be used to generate output values. In embodiments, weights that may be determined during the training phase may not change during the inference phase.

In embodiments, as described above, BL (eg, BLi) may be electrically connected to all of the output lines of synapses in one column of the synapse array 200, and the BL-bar line (eg, BLBi) may be electrically connected to all of the output lines of the synapses of the synapse array 200. This configuration can make the current value on each BL 266 (or BLB 267) be the sum of the individually calculated current values of the corresponding row of synapses in the array 200. In embodiments, the output current of the BLn line and the BLBn line can be expressed as:

[Equation 2a]

BLn = ∑(W_pos-row × Ain-row), for corresponding rows of n-column

[Equation 2b]

BLBn = ∑(W_neg-row × Ain-row), for corresponding rows of n-column

In embodiments, one or more rows of the array 200 may have a fixed input signal voltage, and synapses of the corresponding rows may store bias values for the corresponding columns. In this case, the total electric current on BLn and BLBn can be expressed as

[Equation 3a]

BLn = ∑(W_pos-row × Ain-row) + bias_pos

[Equation 3b]

BLBn = ∑(W_neg-row × Ain-row) + bias_neg

In embodiments, the current input signal (ISig = IBL (261) or IBLB (262)) from the synaptic array in the sensing circuit 250 is converted to a voltage signal (Vsig) using a CTIA (Capacitive Trans Impedance Amplifier). It can be further processed to generate a digital signal using an analog digital converter (ADC). In embodiments, the ADC may have a single-slope column ADC architecture using an offset cancellation column comparator and counter. This structure can use a minimum area and minimum power loss compared to other ADC structures such as pipeline or successive approximation ADCs.

In embodiments, each synaptic layer (eg, 120) of the neural network 100 may be electrically connected to the BL 266 and the BLB 267, and may electrically process the output current on the BL and BLB lines. electrical components (not shown in FIG. 2). For example, an electrical component may provide differential sensing, convert an output current signal to a voltage signal, further convert it to a digital signal, and sum the digital signals in an accumulator. In another example, the electrical components can implement the activation function for Aout of Equation 1 by performing various other processing operations such as normalization and activation on the summed value. In embodiments, the final Aout may be stored in a data buffer and used in neural network 100 to generate an input signal for the next neural array layer.

In embodiments, a separate circuit (not shown in FIG. 2 ) provides auxiliary functions such as: (1) a router that maps the logical neuron-synapse structure of the neural network 100 to the physical address mapping of the synapse array 200; /controller, (2) a drive circuit that drives the input signal to an appropriate row of synapses according to the configuration, (3) a selection circuit that provides column selection for a sensing circuit that shares one or more columns of synapses, (4) synapses A voltage generator for generating a reference voltage used for selection, and (5) a storage device for storing configurations for the router controller and sensing circuit 250 - may be included in the neural network 100 to perform.

3 shows a schematic diagram of a synapse 300 according to embodiments of the present invention. In embodiments, synapse 300 may be used as synapse 210 of FIG. 2 . As shown, the synapse 300 includes a pair of input transistors 311 and 312 and a pair of non-volatile resistance change elements (R_p 313 and R_n 314) (hereinafter referred to as "non-volatile resistance change elements"). The terms “and” “resistance” are used interchangeably). In other words, the synapse 300 may have a pair of 1T-1R (1-transistor 1-resistance) structure. In embodiments, resistors R_p (313) and R_n (314) may be logic-friendly non-volatile resistance change elements. In embodiments, the synapse 300 may have two cells 332 and 334, where each cell has one input transistor 311 (or 312) and a resistor R_p (312) (or R_n (314)). ) can have.

In embodiments, the logic-friendly non-volatile resistive element R_p (313) (or R_n (314)) may be associated with a positive (or negative) weight parameter that the synapse 300 may store/store. In embodiments, each resistor may be electrically connected to a source terminal of an input transistor (eg, 311) and a reference signal line 264 may apply a reference signal to the resistor. In some embodiments, the word line (WL) 265 may apply an input signal voltage to the gate terminal of the input transistor (eg, 311).

In embodiments, the resistance value R (= R_p or R_n) may be programmed into the resistance change element in the training step. When a synaptic input signal is applied to WL 265, the synaptic output current can be approximated by multiplying the input Ain from the previous neuron by a weight (expressed as 1/R), where Ain is the voltage on WL 265. can be represented as

In embodiments, the neural network parameters stored in synapse array 200 may have approximately similar numbers of positive and negative weight parameters. Resistance elements not used in the array 200 may be programmed to have a higher resistance value than a preset value. The electrical current through each unused resistive element must be substantially zero, so that the output current of the cell does not substantially add to the output current on the cell's BL (or BLB). Therefore, the influence of unused resistance elements on calculation is minimized and power consumption is reduced. The trained weight parameters can be quantized and programmed into the resistive change element without significantly deteriorating the accuracy of the neural network calculation. When the resistance value R of resistance R_p (313) (or R_n (314)) is programmed in the training phase and the scaled synaptic input signals WL are applied through WL (265), BL (266) (or BLB (267)) The synaptic output current IC of the phase can be expressed by Equations 4 and 5.

[Equation 4]

dIC/dWL = ~ gm / (1 + gm*R) = ~ l/R (when R is sufficiently greater than l/gm)

Here, gm is the conductance of the input transistor.

[Equation 5]

IC = ~ WL / R = ~ w Ain (where w = l/R and Ain = WL)

Here, w and Ain can approximate IC as a result of multiplying them.

As shown in Equation 5, the output current IC can be approximated by multiplying the input signal (input voltage Ain) and the weight w. Unlike conventional systems, the analog multiplication operation of Equation 5 occurring in the synapse 300 does not require the use of complex digital logic gates, significantly reducing the complexity of the synapse structure and the amount of computational resources.

In embodiments, the input signal Ain may be an output signal from a previous neuron (as shown in FIG. 1 ) and may be directed to the gate of the input transistor 311 (or 312 ). Inducing the input signal Ain to the gate can minimize noise generated by the resistance component of the large synapse array. This is because static current does not flow to the gate of the selection transistor. In contrast, in the conventional system, the input signal is driven by a synaptic selector or resistance change element, which causes a large change in the current input signal for each synapse due to the large resistive component in the large array and the static current flow during operation. easy to do.

In conventional systems, when programming a resistive change element, leakage current through half-selected cells in a large array can change a pre-programmed resistance value, causing undesirable program failure. In contrast, in embodiments, input transistor 311 (or 312) may be activated with a program pulse driven only by resistors 313 (or 314) selected from a large array. Thus, in embodiments, unselected synapses may not perturb programming of selected synapses, where selected synapses may be programmed by applying a suitable bias condition to BL (or BLB) and SL nodes.

As a non-limiting example, the array of synapses 200 may be located in the synapse layer 120, where the output signal from the previous neuron (eg, 112a) of the neuron array layer 110 is the synapse array 200. ) Can be input to the synapse 300 and the output signals of the BL 266 and BLB 267 can be input to one or more of the following neurons (eg, 132a to 132m) in the neuron array layer 130 .

In embodiments, resistor 313 (or 314) can be implemented in various circuits (or memories), such as non-volatile MRAM, RRAM, or PRAM or single poly embedded flash memory, where the circuit is expressed as the reciprocal of resistance. It can be programmed to memorize (store) associated parameters that can be In embodiments, multiplication operations may be completed intra-synapse with analog values without using digital logic and arithmetic circuitry.

4 shows a schematic diagram of another synapse 400 according to embodiments of the present invention. In embodiments, synapse 400 may represent an example implementation of resistors 313 and 314 of FIG. 3 . In other words, in embodiments, resistor 313 may be implemented by components within box 452 of FIG. 4 .

As shown in FIG. 4, the synapse 400 includes a pair of logic-compatible built-in flash memory cells 432 and 434, where the floating gate nodes (FG_p, FG_n) in the flash memory cell are connected to the synapse ( 400) may be associated with each of the positive and negative weight parameters that are memorized/stored.

In embodiments, the synaptic input signal on WL 420 may be shared between the two branches, which may induce differential synaptic output currents (IBL, IBLB) on BL 406 and BLB 407. In embodiments, a program wordline (or simply program line, PWL) 418, a write word line (or simply write line, WWL) 416 and an erase word line (or simply erase line, EWL) 414 are It can be used to provide additional control signals for program, write, and erase operations of the logic-compatible embedded flash memory cells 432 and 434.

In embodiments, memory cells 432 and 434 may include logic transistors that avoid additional process overhead beyond a standard logic process. In embodiments, coupling transistors 422 (and 423) coupled directly to PWL 418 are extended for higher coupling of floating gate nodes FG_p and FG_n to the control signal provided through PWL 418 ( can be upsized. In embodiments, coupling transistor 422 (or 423 ) directly coupled to PWL 418 may be relatively larger than write transistor 424 (or 425 ). When a high program voltage is induced to the PWL 418 and WWL 416, the memory cell 432 (or 434) applies 0V to the BL 406 (or BLB 407) and injects electrons into FG_p. , can be selected and programmed. On the other hand, the unselected cell 434 (or 432) applies VDD to the BLB 407 (or BL 406) and applies VDD to the WL 420 so that the unselected cell 434 (or 432) The program can be inhibited by turning off the selection transistor of . Hereinafter, the term selection transistor refers to a transistor having a gate electrically connected to the BL 406 or the BLB 407.

In embodiments, when a high erase voltage is induced in only WWL 416, the selected WL may be erased by emitting electrons from FG. Unselected WLs may not be driven to a voltage higher than VDD during program and erase operations. Therefore, there is no perturbation in unselected WLs. In embodiments, the FG node voltage may be a function of the PWL 418, WWL 416 and signals on the number of electrons stored in the FG node. The conductance of the read transistor (e.g., 462) electrically connected to FG can be programmed by controlling the voltages at PWL 418 and WWL 416 and the electrical charge stored at the FG node.

In embodiments, when the threshold voltage of the embedded flash cell 432 (or 434) is programmed and the scaled synaptic input signal is provided through the WL 420, Equation 5 can be approximately satisfied. There may be a specific threshold voltage range. Here, the cell output current (=IBL, IBLB) is proportional to the input signal as well as the programmed weighting parameter.

In embodiments, neural network 100 may be robust to random errors or small changes in weight parameters. In embodiments, when the pretrained weight parameter W is quantized during computation of the neural network 100, the neural network performance or inference accuracy will be optimized with some multiplication error in Equation 5 as long as the multiplication error is within a certain range. can Also, a slight multiplication error from the proposed approximate multiplier can compensate for the quantization noise of the trained weight parameters of neural network 100. Nevertheless, in order to avoid a serious cell retention error due to a large cell threshold voltage shift after repetitive training of the neural network, an intentional self-healing current may be applied through the WWL 416. This is because the intentional self-healing current can heal damaged gate oxides of devices electrically connected to the WWL 416 of the embedded flash memory cells 432 and 434. In embodiments, applying the self-healing current may not be necessary for all training or inference and thus has minimal impact on performance or power consumption.

In embodiments, each cell (eg, 432) includes a coupling transistor 422, a write transistor 424 and an upper select transistor (or first select transistor) 460, a read transistor 462 ) and a lower select transistor 464. The single-poly built-in flash memory in the synapse 400 can be used as a resistance change element, and the conductance of a read transistor (eg 462) electrically connected to the floating gate (FG) of the flash is the resistance change can act as an element. In embodiments, the conductance of the read transistor (eg, 462 ) may be determined by a threshold voltage VTH of each of the FG nodes (FG_p or FG_n). The VTH of the FG nodes (FG_p or FG_n) can be roughly programmed first using a balanced step-pulse programming method, and then a subsequent constant-pulse programming method with reduced voltage (constant pulse programming) can fine-tune the VTH value to accurately program the weight to be stored in the synapse 400. The programming steps are described with respect to FIGS. 10A-10B.

5 shows a schematic diagram of a synapse 500 according to embodiments of the present invention. In embodiments, synapse 500 may be used as synapse 210 of FIG. 2 . As shown, synapse 500 may have three pairs of 1T-1R, where three wordlines (WLa, WLb, and WLc) may be electrically connected to the gates of six transistors. Synapse 500 may have word lines electrically coupled to the input transistors as well as any other suitable number of input transistors and resistors. For example, in embodiments, synapse 500 may be modified such that components of wordline WLa and 1T-1R units 550 and 551 may be removed. That is, each cell can have two pairs of 1T-1R. As another example, in embodiments, the synapse 500 may be modified so that each cell has 4 pairs of lT-1R and 4 word lines (input signal lines) (WL).

In embodiments, SL, BL and BLB of synapse 500 may have a similar function as SL, BL and BLB of synapse 300 of synapse 300 . The difference between the synapse 300 and the synapse 500 is that the synapse 500 can receive input signals from previous neurons through three word lines WLa, WLb, and WLc. More specifically, a signal from each WL can be guided to the gate terminal of the corresponding input transistor.

Each synapse 500 may be electrically connected to three word lines WLa, WLb, and WLc, whereas each synapse 210 in FIG. 2 is shown connected to one word line 265. Thus, each word line 265 in FIG. 2 collectively refers to at least one word line electrically connected to a synapse including one or more input transistors.

In an embodiment, synapse 500 may have two cells 532, 534, where each cell may have three pairs of 1T-1R (one transistor-one resistor), each 1T-1R The pair can be electrically connected to WL and SL.

Each resistance of the synapse 500 may be implemented by various circuits (or memories) such as non-volatile MRAM, RRAM, or PRAM or single-poly embedded flash memory, where the circuit has a related parameter that can be expressed as a resistance. It can be programmed to remember (store). In embodiments, each resistance of synapse 500 may be implemented by the components of box 452 of FIG. 4 . Here, each synapse 500 may be electrically connected to PWL, WWL and EWL in a manner similar to the synapse 400.

6 shows a schematic diagram of another synapse 600 according to embodiments of the present invention. In embodiments, synapse 600 may be used as synapse 210 of FIG. 2 . As shown, each cell 632, 634 has two transistors (eg, 602, 606) and a resistor (eg, 613), and two input signals (or words) electrically connected thereto. ) line (word line WL and word line bar WLB), and one reference signal line SL. Although each synapse 600 may be electrically connected to two wordlines, each synapse 210 in FIG. 2 is shown connected to one wordline 265 . Thus, each word line 265 in FIG. 2 collectively refers to one or more word lines electrically connected to a synapse including one or more input transistors.

In embodiments, the synaptic resistances (R_p (613), R_n (614)), the reference signal line (SL), and the output current lines (BL, BLB) function similar to the corresponding components of the synapse 230 of FIG. can have For example, the input selection transistors 602 and 604 electrically connected to WL and the resistors R_p 613 and R_n 614 may correspond to the input selection transistors 211 and 212, respectively.

Compared to the synapse 300 of FIG. 3 , the synapse 600 may be electrically connected to another input signal line WLB, where the WLB may provide a differential input signal voltage to the WL. In embodiments, additional input select transistors 606 and 608 may be electrically connected to the WLB through their gate terminals. In embodiments, source terminals of the input selection transistors 606 and 608 may be electrically connected to resistors R_p (613) and R_n (614), respectively. In embodiments, the drain terminal of transistor 602 may be electrically connected to BL and the drain terminal of transistor 606 may be electrically connected to BLB. Similarly, the drain terminal of transistor 604 can be electrically connected to BLB and the drain terminal of transistor 608 can be electrically connected to BL.

In embodiments, synapse 600 may receive a differential input signal, where WL provides a positive input signal voltage (common mode reference) and a_pos, and WLB provides a negative input signal voltage (common mode reference) and a_neg provides In embodiments, R_p 613 may store the positive weight w_pos and R_n 614 may store the negative weight w_neg. Thus, in embodiments, the output signal current BLo on BL may be the sum of the two output signals from the two cells 532 and 534.

[Equation 6]

BLo = a_pos × w_pos + a_neg × w_neg

Similarly, the output signal current BLBo on BLB may be the sum of the two output signals from the two cells 532 and 534.

[Equation 7]

BLBo = a_pos × w_neg + a_neg × w_pos

Thus, as shown, some embodiments with differential signaling for WL and WLB, other embodiments with single-ended signaling for WL of synapse 300 shown in FIG. Compared to BL and BLB, it can have a larger range of output current. Also, as shown, embodiments with differential input signals can suppress transistor offset noise as well as common mode noise from changes in supply voltage or temperature.

Each resistance of synapse 600 may be implemented by various circuits (or memories) such as non-volatile MRAM, RRAM, or PRAM or single-poly embedded flash memory, where the circuit is programmed to store (store) relevant parameters. It can be. 7 shows a schematic diagram of another synapse 700 according to embodiments of the present invention. In embodiments, synapse 700 may represent an example implementation of resistors 613 and 614 of FIG. 6 . In other words, the components of box 752 may correspond to resistor 613 in FIG. 6 .

As shown in FIG. 7 , synapse 700 may include two cells 732 and 734 . In embodiments, cell 732 (or 734) may be similar to cell 432 (or 434) of synapse 400, and cell 732 (or 734) may include an additional upper select transistor (or upper select transistor). 720 (or 722)) and an additional input signal line (WLB). In embodiments, the gate of transistor 720 (or 722) may be electrically connected to the input signal line (WLB) and the drain of transistor 720 (or 722) may be electrically connected to the output signal line (BLB). there is.

8 shows a schematic diagram of another synapse 800 according to embodiments of the present invention. In embodiments, synapse 800 may be used as synapse 210 of FIG. 2 . As shown, synapse 800 may include two cells 832 and 834. Here, each cell may include 3 resistors and 6 transistors. The synapse 800 may have a 2T-1R structure. That is, each cell may include three sets of 2T-1R units 802. The synapse 800 may be electrically connected to six input signal lines—three word lines (WLa, WLb, and WLc) and three word line bars (WLaB, WLbB, and WLcB). Each cell of synapse 800 may contain any other suitable number of 2T-1R units 802 . In embodiments, each pair of WL and WLB (eg, WLa and WLaB) may provide a differential input signal to cells 832 and 834.

In embodiments, the reference signal line SL may provide a reference signal to the cells 832 and 834. In embodiments, each of the output signal lines BL and BLB may collect output signals from drain terminals of three transistors of cell 832 and drain terminals of three transistors of cell 834 . In embodiments, synapse 800 may receive a differential input signal. Here, each WLi provides a positive input signal voltage (a_pos_i), and each WLBj provides a negative input signal voltage (a_neg_j). In embodiments, each R_p may store a positive weight (w_pos_i) and each R_n may store a negative weight (w_neg_j). In embodiments, the output signal current BLo on BL may be the sum of six output signals from two cells 832 and 834.

[Equation 8]

BLo = ∑(a_pos_i × w_pos_i) + ∑(a_neg_j × w_neg_j)

Similarly, the output signal current BLBo on BLB may be the sum of the six output signals from the two cells 832 and 834.

[Equation 9]

BLBo = ∑(a_pos_i × w_neg_j) + ∑(a_neg_j × w_pos_i)

Each resistance of synapse 800 may be implemented by various circuits (or memories) such as non-volatile MRAM, RRAM, or PRAM or single-poly embedded flash memory, where the circuit is programmed to store (store) relevant parameters. It can be. In embodiments, each resistance of synapse 800 may be implemented by components of box 752 of FIG. 7 . Here, each synapse 800 may be electrically connected to PWL, WWL and EWL in a manner similar to the synapse 700.

In general, the conductance of the read transistor (eg 462) can be changed by injecting electrons into the floating gate. 9A-9B show a comparison of two conventional methods for programming the threshold voltage (VTH) of a floating gate node (columns 910 and 914) and a method according to embodiments (column 912). 9A shows a table 900 including voltage heights and widths of signals applied to the PWL and WWL terminals during the program operation of the floating gate cell 432. To this end, electrons may be injected into the floating gate. As shown, table 900 includes three columns 910, 912, and 914 each corresponding to three approaches for applying voltage signals, respectively.

Column 910 represents a conventional incremental-step-pulse programming (ISPP) method in which each subsequent program step increases the program voltage by a delta with a constant pulse width (T_pulse) over the previous step. . Column 912 is a balanced-step-pulse programming in which the first step has a longer programming pulse width by a certain design parameter m compared to the programming method of column 910 according to an embodiment. indicate the way Column 914 represents a conventional constant-pulse programming method in which all steps have the same program voltage and program pulse width.

FIG. 9B displays VTH 950 of the floating gate cell 432 or 434 according to the three methods of FIG. 9A. In Figure 9B, the three marks 960, 962, and 964 correspond to each of the three methods 910, 912, and 914, and each mark in Figure 9B represents a floating gate cell 432 after each step of the corresponding method in Figure 9A. or 434).

Based on indication 950, a balance-step-pulse programming method according to embodiments of the present invention may be preferred of these three methods. Since each step increases VTH by approximately the same amount (delta), VTH can be programmed accurately, resulting in tighter VTH fluctuations than other methods.

10A-10B show another method for programming the threshold voltage (VTH) of a floating gate cell 432 or 434 according to embodiments of the present invention. 10A shows a table 1000 including voltage heights and widths of signals applied to PWL and WWL terminals during a program operation of a floating gate cell 432 or 434. To this end, electrons may be injected into the floating gate. Figure 10B shows an indication 1050 of the VTH stored in the floating gate cell 432 or 434 at each stage of Figure 10B.

As shown, for some initial steps (here, up to step 4), the balance-step-pulse programming method (referred to in conjunction with Figs. 9A and 9B) approximates the cell VTH to a value that does not exceed the target VTH. can be used for programming. In some embodiments, the target VTH can be achieved at these early stages (up to stage 4) with an acceptable margin. In some other embodiments, more precise programming of the target VTH may be required. In such embodiments, the difference between the current VTH and the target VTH may be less than a possible increment of VTH at each step (delta in FIG. 10B). Then, further subsequent constant-pulse programming steps are applied to correctly program VTH.

In embodiments, subsequent constant-pulse programming steps use a reduced programming pulse height (by alpha in FIG. 10A) to set the target VTH but an increased pulse width (T_pulse * n, n 1.0 or higher). As a result, the programming schemes of FIGS. 10A to 10B can control the final programmed cell threshold voltage below a possible voltage step (=delta) generated from the target VTH and the on-chip voltage reference. .

11 shows a flow diagram 1100 of an exemplary process for programming the threshold voltage (VTH) of a floating gate node in accordance with embodiments of the present invention. In step 1102, a voltage pulse (eg, step 1 in FIG. 10A) having a first height (eg, VPGM) and a first width (T_pulse * m, where m is greater than or equal to 1.0) is applied to the floating gate cell 432 or 434) may be applied to the PWL and WWL terminals. For this purpose, electrons may be injected into the floating gate. In step 1104, the first voltage pulse sequence (eg, steps 2 to 4 in FIG. 10A) is applied to the PWL and WWL terminals while increasing the height of each pulse by a preset value (eg, delta) from the previous pulse. can be authorized

At step 1106, it may be determined whether the target VTH has been reached after the first pulse sequence is applied. If the answer to the decision is affirmative, the process proceeds to step 1108. At step 1108, the process is stopped. Otherwise, in step 1110, a second voltage pulse sequence (such as steps 5 to 19 in Fig. 10A) may be applied to the PWL and WWL terminals. In embodiments, each pulse of the second pulse sequence may have a width (T_pulse * n, where n is greater than or equal to 1.0) that is not narrower than the pulse (T_pulse) in the previous step. In embodiments, the second pulse sequence has a height (VPGM - alpha) lower than the first height, and the second pulse sequence has a width (T_pulse * n) that is not narrower than the second width (T_pulse). In embodiments, by way of example, the values may be m=9.0, n=5.0, alpha=0.8V, delta=0.1V, and VPGM=7.2V.

The methods for programming VTH of the floating gate node of FIGS. 9A-11 can be applied to cells 732 and 734. More specifically, the method associated with column 912 of FIG. 9A and/or the method described in conjunction with FIGS. 10A-10B may be used to program the VTH of cells 732 and 734.

Each synapse of FIGS. 3 to 8 may generate two output signals through two output signal lines BL and BLB. Here, a differential signal technique may be applied to generate two output signals. Differential signaling can reduce sensitivity to transistor offset and common mode noise due to supply voltage and temperature changes that can cause significant errors in output current in conventional synapse or device designs for weighted sum computation. there is.

12A-12C illustrate differential signaling in accordance with embodiments of the present invention. As shown in Figure 12A. The IBL line 1212 and the IeL-Bar line 1214 may be output currents through synaptic output signal lines (BL (eg, 106) and BLB (eg, 107)), respectively. As an example, each output current may range from a minimum of 0.5 (A.U.) to a maximum of 1.5 (A.U.) depending on the resistance values of R_p and R_n. In embodiments, IBL line 1212 can be the sum of first current signal 1224 and offset current signal 1220, while IBL line 1214 is offset current 1220 and second current signal 1226. can be the sum of As shown, offset current 1220 may include transistor offset and common mode noise.

As shown in Figure 12B. By applying the differential signal technique to the two output signal lines 1212 and 1214, the offset current 1220 can be canceled, and the values of the output current signals 1224 and 1226 can be obtained. As an example, output current signals 1224 and 1226 may range from 0.0 (A.U.) to 1.0 (A.U.).

Also, in an embodiment, the first current signal 1224 may have a polarity opposite to that of the second current signal 1226. As shown in FIG. 12C, by using differential signaling of the two output signals, the difference between the two signals (IBL-IBL-Bar) 1216 can range from a minimum of -1.0 to a maximum of +1.0. there is. That is, the range of the combined signal can be twice the range of a single output.

13 shows a schematic diagram of a chip 1300 including a neural network according to embodiments of the present invention. As shown, the chip 1300 may have a system-on-chip structure, a non-volatile neural network 1316, a CPU 1312 for controlling elements on the chip 1300, and a non-volatile neural network 1316 ) may include a sensor 1314 for providing an input signal and a memory 1318. In embodiments, neural network 1316 may be similar to neural network 100 of FIG. 1 . In embodiments, chip 1300 may be a silicon chip and components 1312 - 1318 may be integrated on chip 1300 .

14 shows a schematic diagram of a system 1400 for operating a non-volatile synapse array according to embodiments of the present invention. As shown, the system 1400 includes a non-volatile synapse array 1410, a reference generator 1402, a configuration storage device 1404, and a row for selecting a synapse row from among the non-volatile synapse array 1410. A (row) driver 1406, a router/controller 1408, a column selector 1412 for selecting a synapse row from the non-volatile synapse array 1410, a detection circuit 1414, and a non-volatile synapse array 1410. An accumulator 1416 for collecting output values from the volatile synapse array 1410, a normalization/activation/pooling function block 1418, and a data buffer 1420 for buffer data from the non-volatile synapse array 1410 can include In embodiments, the non-volatile synapse array 1410 may be similar to the non-volatile synapse array 200 and the sensing circuitry 1414 may be similar to the sensing circuitry 250 of FIG. 2 .

Reference generator 1402 includes the reference signals used by row driver 1406 (e.g., SL of FIGS. 2-8) and input signal lines (e.g., WL of FIGS. 2-8). It provides the voltage level required for Configuration storage 1404 includes data about the finite state machines used by router/controller 1408, physical mapping of weight parameters to synaptic locations in synapse array 200, and other configurations for the sensing circuitry. save the parameters In embodiments, the configuration storage may be implemented as an on-chip, non-volatile memory. Router/controller 1408 implements a finite state machine to control row selection sequences via row driver 1406. Sensing circuit 1414 includes a voltage regulator and an analog-to-digital converter to convert the output current signal from the selected column to a voltage signal and further to a digital value. The results from the sensing circuit are summed in accumulator 1416. The normalization/activation/pooling function block 1418 performs any necessary signal processing operations on the accumulator value. Multiple dedicated DSPs or embedded CPU cores may be included to perform these numerical operations in parallel.

In some embodiments, the neural network design may binarize the values of the weights and input parameters to 1 or -1. In such an embodiment, synapse 600 may be modified such that a cross-coupled latch circuit may be used in place of a pair of non-volatile resistive change elements. 15 shows a schematic diagram of another synapse 1500 according to embodiments of the present invention. As shown, the synapse 1500 may include a cross-coupled latch circuit 1510, wherein the cross-coupled latch circuit 1510 has an input terminal electrically coupled to an output terminal of a second inverter 1518 (inverter ( 1514) and vice versa. According to an embodiment, the cross-coupled latch may store a digital signal at an S node located between the output of 1518 and the input of 1514 and at an SB node located between the output of 1514 and the input of 1518. According to an embodiment, when the S node has an electrical signal value, the SB node may have a complementary signal value, and vice versa due to inverter coupling.

As shown in FIG. 15, each of the cells 1532 and 1534 of the synapse 1500 has two input signal (or word) lines, two inputs electrically connected to a word line (WL) and a word line bar (WLB). and select transistors (eg, 1502 and 1506), at the gate terminals. The source terminal of the input select transistor may be electrically coupled to a common node that is further electrically coupled to the node of cross-coupled latch circuit 1510. Cell 1532 may be electrically coupled to the SB node of cross coupling latch 1510 . Cell 1534 is electrically connected to the S node of 1510.

In an embodiment, the drain terminal of transistor 1502 can be electrically connected to output line BL and the drain terminal of transistor 1506 can be electrically connected to output line BLB. Similarly, the drain terminals of transistors 1504 and 1508 can be electrically connected to BLB and BL, respectively.

In embodiments, the reference signal line SL may be electrically connected to each of the inverters 1514 and 1518 of the cross-coupled latch 1510, and the reference voltage input signal 201 may be connected to the inverters 1514 and 1518. can be provided.

The cross-coupled latch 1510 is implemented by various circuits (or memories) such as non-volatile components, but may also be implemented by volatile memory components when a power source (eg, a battery) is available.

16 shows a table showing the relationship between input voltage values of WL and WLB, weight values represented by voltage signals of nodes S and SB, and outputs represented by current values of lines BL and BLB. For an entry in the table, (WL = High, WLB = Low) can be 1 and (WL = Low, WLB = High) can be -1. For the weights in the table, (SB = High, S = Low) can be 1 and (SB = Low, S = High) can be -1. The "low" voltage values for the inputs and weights in the table are the lower voltage values than the "high" voltage values. For the output of the table, (BL = Low, BLB = High) can be 1 and (BL = High, BLB = Low) can be -1. In the output of the table, the "Low" current value is the current value lower than the "High" current value.

In the table, the output of BL and BLB can represent the multiplication of inputs (WL, WLB) and weights (SB, S), where 1×1 = 1, 1×-1 = -1, -1×1 = - 1, and -1×-1 = 1. Therefore, the multiplication operation between the binarized input and the weight can produce arithmetically correct results.

17, 18 and 19 show schematic diagrams of synapses 1700, 1800 and 1900, respectively, according to an embodiment of the present invention. As shown in FIG. 17 , synapse 1700 may include only cells 1732 that may correspond to cells 632 in synapse 600 shown in FIG. 6 . Similarly, FIG. 18 shows a synapse 1800 that includes only cells 1832 that may correspond to cells 732 of synapse 700 shown in FIG. 7 . The synapse 1900 shown in FIG. 19 may include only a cell 1932 that may correspond to the cell 832 of the synapse 800 of FIG. 8 . The negative weight w_neg at synapses 1700, 1800 and 1900 may be equal to zero. That is, the negative weight may be removed from each of the synapses 600, 700, and 800. The BLB line can be maintained because the WLB signal can provide a negative input signal to the BLB line.

In an embodiment, the output signal current BLBo for synapses 1700 and 1800 may be:

[Equation 10]

BLBo = a_neg × w_pos

Similarly, the output current signal BLBo for synapse 1900 may be:

[Equation 11]

BLBo = ∑(a_neg_j × w_pos_i)

20 shows a schematic diagram of a synapse 2000 according to embodiments of the present invention. As shown, the synapse 2000 may be similar to the synapse 300, the difference being that only the positive weight of the cell 2032 (which may correspond to the cell 332 in FIG. 3) is at the synapse 2000. included, and cells 334 and BLB line 267 in FIG. 3 can be removed.

21 shows a schematic diagram of a synapse 2100 according to embodiments of the invention. As shown, synapse 2100 may be similar to synapse 400, except that only cell 2132 (which may correspond to cell 432 in FIG. 4) is used and cell 434 in FIG. The BLB output line is that it can be removed.

22 shows a schematic diagram of a synapse 2200 according to an embodiment of the present invention. As shown, synapse 2200 may be similar to synapse 500 of FIG. 5 , with the difference that only cell 2232 (corresponding to cell 532 of FIG. 5 ) is used and cell 534 of FIG. 5 and the BLB output. The line is something that can be removed.

17 to 22 disclose synapses arranged in a two-dimensional array format as shown in FIG. That is, the synapse of FIGS. 17 to 22 may correspond to the synapse 210 .

According to the present invention, logic friendly NVM in an embodiment means a non-volatile memory component (with zero standby power) that can be created in fewer processing steps than conventional NVM components such as split gate flash memory or EEPROM. Since the NVM of an embodiment requires only a few additional processing steps compared to the logical components of a CPU or neural network computation engine, it is possible to embed the NVM of an embodiment on the same chip as the CPU or neural network engine. Conversely, embedding existing NVM components on the same chip as a CPU or neural network engine is not feasible due to the excessive extra processing required to create such a chip.

Examples of logic-friendly NVMs used in the embodiments include STT-MRAM, RRAM, PRAM, or FeFET components that require fewer processing steps than logic components. Another example of a logic friendly NVM in an embodiment is a single poly embedded flash memory. Single-poly flash memory requires no additional processing compared to logic components and is particularly suitable for embedding on the same chip as a CPU or neural network engine. Like conventional NVMs, logic-friendly NVMs can retain stored data when powered off.

In the conventional neural network system shown in FIG. 23, an external NVM chip 2319 integrates various circuit blocks such as a CPU 1312, a sensor 1314, and a neural network computing engine 2320 connected through a system bus 2330. It is separately attached to a System-on-Chip (SoC) 2310 that

CPU 1312 and sensor 1314 are numbered similarly to the components of FIG. 13 . Neural network weight parameters are stored in the external NVM chip 2319 when the system is powered off. Accessing the external NVM chip 2319 is slow because the performance of the system bus 2330 is limited by the pin count of the SoC 2310.

Accessing the external NVM consumes a large amount of power due to external wire capacitance. In addition, security becomes an issue when privacy-related neural network parameters are transmitted between the SoC 2310 and the external NVM 2319.

24 shows a layered system for a neural network according to the present invention composed of the SoC 1300 shown in FIG. 13 and an external neural network accelerator 2470. In an embodiment, the on-chip non-volatile neural network module 1316 is integrated with the CPU 1312, sensors 1314, and memory 1318 blocks within the SoC 1300 via a high-performance system bus.

In an embodiment, the width of the high-performance system bus 2430 is not limited by the pin count of the SoC 1300. Thus, communication over the high-performance system bus 2430 is much faster than communication with the prior art system bus 2330 shown in FIG. The external neural network accelerator device 2470 can be connected via an off-chip interconnect 2480 that can be wired locally or accessed remotely. Local wired approaches may include TSV, 3D-stacking, wire bonding or access via PCB. Remote access methods may include LAN, Wi-Fi, and Bluetooth. The external neural network accelerator device may include its own CPU and high-density memory (DRAM, Flash Memory, SCM, etc.) and may be located in a cloud server.

In an embodiment, by dividing the entire neural network into SoC 1300 and external neural network accelerator device 2470, certain critical layers can be executed within SoC 1300 using non-volatile neural network module 1316 while other remaining layers The external neural network accelerator device 2470 may use low-cost and high-density memory such as 3D-NAND. For example, the initial layer of the neural network can be processed on-chip and the remaining layers can be processed by the external neural network accelerator device 2470 . This is because features extracted or coded only in the on-chip non-volatile neural network are communicated off-chip, and the amount of externally communicated data can be reduced compared to the case where there is no neural network module in the SoC. The intermediate results of the on-chip neural network may provide low-latency partial results that may be useful for early prediction of the final result because the parameters required for execution are stored in the on-chip non-volatile neural network 1316. By off-chip communication using coded information only between the SoC 1300 and the external neural network accelerator device 2470, the problem of personal information is significantly reduced.

25 illustrates a distributed neural network system comprised of multiple die of SoC 1300a and 1300b in accordance with the present invention. In an embodiment, SoCs 1300a and 1300b are similar to SoC 1300 described in FIGS. 13 and 24 . Off-chip interconnection 2480 is similar to that of FIG. 24 . By splitting the entire neural network into multiple SoC units, neural network calculations can be performed in parallel to improve performance. For example, some initial layers can be handled by one SoC's on-chip neural network module, while others can be handled by another SoC. Only functions extracted or coded in the first SoC are passed off the chip. The intermediate results of the first SoC can provide low-latency partial results that can be useful for early prediction of the final result because the parameters required for execution are stored in each on-chip non-volatile neural network 1316. By communicating off-chip with coded information only between the SoCs 1300a and 1300b, the privacy problem is significantly reduced.

26 shows that a logic friendly NVM 2619 is integrated into SoC 2600 along with other circuit blocks such as CPU 1312, sensors 1314 and neural network computing engine 2320 and high performance system bus 2430 according to the present invention. Shows the system-on-chip connected via Similarly numbered components indicate corresponding components in FIG. 23 . Energy dissipation, delay overhead can also be improved compared to the prior art design of FIG. It also reduces security issues caused by external NVM access. The single logic chip solution of the embodiment is economical and attractive for IoT applications featuring a logic compatible embedded flash that securely stores neural network parameters.

In an embodiment, the bus width is not limited by the number of pins available on the chip. Thus, the wide I/O and low-latency memory interface can be used for communication between the logic-friendly NVM of SoC 2600 and other blocks. Thus, the neural network computing engine 2320 can access data in the logic-friendly NVM 2619 faster than prior art systems using external flash memory.

27 shows a neural network system of the present invention in which a logic friendly NVM 2719 is integrated into SoC 2700 within neural network engine 2720. The neural network computing engine 2720 is similar to the neural network computing engine 2620 of FIG. 26 . The neural network computing engine 2720 can access the logic-friendly NVM 2719 without CPU intervention with improved performance and power efficiency compared to the prior art of FIG. 26 .

The proposed configuration of the present invention with on-chip non-volatile neural networks described in FIGS. 24-27 has various advantages over the prior art, such as lower power consumption and higher performance. In addition, privacy concerns are significantly reduced by restricting off-chip access when private user data is used to run neural networks in an embodiment.

This privacy-enhanced neural network in an embodiment may be used in creative personal devices. For example, according to one embodiment of the present invention, a new personal task, question or answer may be generated by interaction in a portable educational device or smart toy using an on-chip non-volatile neural network. An embodiment of the present invention may be useful for identifying individuals through image or sound recognition while restricting off-chip access. In particular, home care or child care devices may not require very complex neural network models due to the limited number of people who need to recognize voices. However, these devices may require a high degree of personalization and may have stringent requirements for privacy. In addition, since the core neural network layer for this type of application can be executed without off-chip communication of critical information, an on-chip non-volatile neural network according to an embodiment of the present invention will improve the security of military devices or network firewalls. can

In another aspect of the present invention, the proposed on-chip non-volatile neural network system can be used in a secure personalized vision/motion/voice recognition device by storing and calculating personalization information on-chip. For example, since all neural network calculations are performed on-chip, the device can recognize a specific person's gesture or voice without sending personally trained neural network parameters off-chip. Such visual/motion/voice recognition neural network devices can replace bulky user interface devices (eg, PC keyboards or mice, TV remote controllers). For example, a keyboard touch display could be replaced with a neural network engine capable of recognizing the device owner's hand gestures for each text character. By storing personalized information in an on-chip non-volatile neural network, only specific people can interact with the device.

In addition, the proposed on-chip non-volatile neural network can be utilized to improve the performance and reliability of other SoC building blocks such as CPU, memory and sensor. Due to various operating conditions, such as temperature or aging effects of transistors, the operating voltage and frequency need to be adaptively controlled over the lifetime of the SoC. Manual tuning of these parameters is a difficult task for neural networks to optimize. However, off-chip neural network accelerators may not meet performance requirements and require excessive additional power. Non-volatile neural networks can be used to optimize these parameters of different components of its own chip for given performance and power requirements.

Although this invention is capable of many modifications and alternative forms, specific examples are shown in the drawings and described in detail herein. However, it is to be understood that the present invention is not limited to the particular forms disclosed, but on the contrary, the present invention includes all modifications, equivalents and alternatives falling within the scope of the appended claims.

Claims (17)

a first input signal line for providing a first signal;
a second input signal line for providing a second signal;
a reference signal line providing a reference signal;
a first output line for conveying an output signal; and
A cell for generating the output signal;
the cell,
a first upper select transistor having a gate electrically connected to the first input signal line;
a second upper select transistor having a gate electrically connected to the second input signal line;
a first resistive change element having one end connected in series to the first upper select transistor and the other end electrically connected to the reference signal line, wherein a value of the first resistive change element is programmable to change a magnitude of an output signal;
A second resistance change element having one end connected in series to the second upper select transistor and the other end electrically connected to the reference signal line, the value of the second resistance change element being programmable to change the magnitude of an output signal. include,
A non-volatile synapse circuit, characterized in that the drain of the first upper select transistor and the drain of the second upper select transistor of the cell are electrically connected to the first output line.
According to claim 1,
program lines for providing programming signals;
a write line for providing a write signal; and
an erase line for providing an erase signal;
Including more,
The first resistance change element includes a coupling transistor and a write transistor provided to have a floating gate node, wherein the coupling transistor is electrically connected to the program line and the write transistor is electrically connected to the write line; A read transistor and a lower select transistor provided in series with the upper select transistor, the lower select transistor having a source electrically connected to the reference signal line and a gate electrically connected to the erase line, and the read transistor electrically connected to the floating gate node Having a gate connected to - A non-volatile synaptic circuit comprising a. delete a first input signal line for providing a first signal;
a second input signal line for providing a second signal;
a reference signal line providing a reference signal;
a first output line for conveying an output signal; and
A cell for generating the output signal;
the cell,
a first upper select transistor having a gate electrically connected to the first input signal line;
a second upper select transistor having a gate electrically connected to the second input signal line; and
a first resistive change element having one end connected in series to the first upper select transistor and the other end electrically connected to the reference signal line, wherein a value of the first resistive change element is programmable to change a magnitude of an output signal; including,
The second upper selection transistor has a source electrically connected to the first resistance change element;
A source of the first upper select transistor and a source of the second upper select transistor are directly connected to a first common node;
A drain of a first upper select transistor of the cell is electrically connected to the first output line;
A non-volatile synaptic circuit, characterized in that the drain of the second upper selection transistor of the cell is electrically connected to the second output line.
According to claim 4,
program lines for providing programming signals;
a write line for providing a write signal; and
an erase line for providing an erase signal;
Including more,
The first resistance change element includes a coupling transistor and a write transistor provided to have a floating gate node, wherein the coupling transistor is electrically connected to the program line and the write transistor is electrically connected to the write line, and a series A read transistor and a lower select transistor provided with - the lower select transistor has a source electrically connected to the reference signal line and a gate electrically connected to the erase line, wherein the read transistor has a gate electrically connected to the floating gate node and the gate electrically connected to the erase line. Having a source directly connected to the first common node. A non-volatile synaptic circuit comprising:
According to claim 4,
a third input signal line for providing a third input signal; and
a fourth input signal line for providing a fourth input signal;
Including more,
the cell,
a third upper select transistor having a gate electrically connected to the third input signal line;
A fourth upper select transistor having a gate electrically connected to the fourth input signal line;
A source of the third upper select transistor and a source of the fourth upper select transistor are directly connected to a second common node;
The second resistance change element has one end connected to the second common node and the other end electrically connected to the reference signal line, and a value of the second resistance change element is programmable to change the magnitude of an output signal;
A drain of the third upper select transistor of the cell is electrically connected to the first output line;
A non-volatile synapse circuit, characterized in that the drain of the fourth upper selection transistor of the cell is electrically connected to the second output line.
a first input signal line for providing a first input signal;
2 input signal lines for providing a second input signal;
a reference signal line for providing a reference signal;
first and second output lines for conveying first and second output signals;
A cross-coupled latch circuit for storing electrical signals;
First and second inverters having input and output terminals, respectively, an input terminal of the first inverter connected to the output terminal of the second inverter at a first signal node, and an output terminal of the first inverter at a second signal node An input terminal of a second inverter connected to and first and second cells for generating first and second output signals, respectively;
Each first and second cell:
a first upper select transistor having a gate electrically connected to the first input signal line;
a second upper select transistor having a gate electrically connected to the second input signal line; and
a source of a first upper select transistor and a source of a second upper select transistor that are directly connected to a common node;
the common node of the first cell is electrically coupled to the first signal node of the cross-coupled latch circuit and the common node of the second cell is electrically coupled to the second signal node of the cross-coupled latch circuit;
here :
The drain of the first upper select transistor of the first cell is electrically connected to the first output line and the drain of the first upper select transistor of the second cell is electrically connected to the second output line;
The drain of the second upper select transistor of the first cell is electrically connected to the second output line and the drain of the second upper select transistor of the second cell is electrically connected to the first output line;
The first and second inverters of the cross-coupled latch circuit are electrically coupled to the reference signal line.
According to claim 7,
The cross-coupled latch circuit is a synapse circuit, characterized in that implemented as a non-volatile memory circuit.
a central processing unit for controlling the elements of the chip;
a non-volatile neural network unit;
a sensor providing an input signal to the non-volatile neural network; and
a memory unit,
The central processing unit, sensor, memory unit and non-volatile neural network unit are electrically coupled,
The non-volatile neural network unit,
Synapse array including a plurality of non-volatile synapses;
low driver;
criteria generator; and
a sensing circuit;
The synapse array, row driver, reference generator and sensing circuit are electrically coupled;
Each non-volatile synapse,
a first input signal line providing a first input signal from a row driver, wherein the reference generator provides a desired voltage level to the row driver;
a reference signal line for providing a reference signal from the row driver, wherein the reference generator provides the required voltage level to the row driver;
a first output line for conveying an output signal, the output signal being processed by the sensing circuit; and
a first cell for generating an output signal;
each cell,
a first upper select transistor having a gate electrically connected to the first input signal line; and
and a first resistive change element having one end connected in series to the first upper select transistor and the other end electrically connected to the reference signal line, wherein a value of the first resistive change element is programmed to change a magnitude of an output signal. possible-
Here, the neural network chip, characterized in that the drain of the first upper select transistor of the first cell is electrically connected to the first output line.
According to claim 9,
Each non-volatile synapse of the synapse array,
A program line-reference generator for providing programming signals from the row drivers provides the required voltage levels for the row drivers;
A write line-reference generator for providing a write signal from the row driver provides the required voltage level to the row driver; and
an erase line providing an erase signal from the row driver;
The first resistance change element,
a coupling and write transistor arranged to have a floating gate node, wherein the coupling transistor is electrically coupled to the program line and the write transistor is electrically coupled to the write line; and
A read transistor and a lower select transistor arranged in series with the upper select transistor - the lower select transistor has a source electrically connected to the reference signal line and a gate electrically connected to the erase line, the read transistor having a floating gate electrically coupled to the gate node Having - A neural network chip comprising a.
According to claim 9,
Each non-volatile synapse of the synapse array,
a second input signal line providing a second input signal from the row driver;
the cell,
a second upper select transistor having a gate electrically connected to the second input signal line;
A second resistive change element having one end connected in series to the second upper select transistor and the other end electrically connected to the reference signal line, wherein a value of the second resistive change element is programmable to change a magnitude of an output signal;
wherein the drain of the second upper select transistor of the cell is electrically coupled to the first output line.
According to claim 9,
Each non-volatile synapse of the synapse array,
a second input signal line reference generator for providing a second input signal from the row driver to provide a desired voltage level to the row driver; and
a second output signal line providing a second output signal;
The output signal is processed by the sensing circuit to deliver an output signal;
the cell,
a second upper select transistor having a gate electrically coupled to the second input signal line; and
a source of the second upper selection transistor electrically coupled to the first resistance change element, wherein a source of the first upper selection transistor and a source of the second upper selection transistor are directly connected to a first common node;
A neural network chip, wherein the drain of the second upper select transistor of the first cell is electrically coupled to the second output line.
According to claim 12,
Each non-volatile synapse of the synapse array,
a program line for providing a programming signal from the row driver, the reference generator providing the desired voltage level to the row driver;
Write line to provide the write signal from the row driver - the reference generator provides the required voltage level to the row driver -;
Erase line for providing an erase signal from the row driver - the reference generator provides the required voltage level to the row driver; including,
The first resistance change element,
A coupling transistor and a write transistor provided to have a floating gate node, wherein the coupling transistor is electrically connected to the program line, and the write transistor is electrically connected to the write line, and the first upper select transistor is in series with A read transistor and a lower selection transistor are provided, wherein the lower selection transistor has a source electrically connected to the reference signal line and a gate electrically connected to the erase line, and the read transistor has a gate electrically connected to the floating gate node. A neural network chip comprising a.
According to claim 12,
Each non-volatile synapse in the synapse array,
a third input signal line for providing a third input signal from the row driver, wherein a reference generator provides the desired voltage level to the row driver; and
a fourth input signal line for providing a fourth input signal from the row driver, wherein the reference generator provides the required voltage level to the row driver; Including more,
the cells,
a third upper select transistor having a gate electrically connected to the third input signal line; and
A fourth upper select transistor having a gate electrically connected to the fourth input signal line - a source of the third upper select transistor and a source of the fourth upper select transistor are directly connected to a second common node, and a second resistance change The element has one end connected to the second common node and the other end electrically coupled to the reference signal line, and the value of the second resistance change element is programmable to change the magnitude of an output signal; Including more,
A drain of a third upper select transistor of the cell is electrically coupled to the first output line;
The neural network chip, characterized in that the drain of the fourth upper select transistor of the cell is electrically coupled to the second output line.
central processing unit;
sensor unit;
neural network engine; and
Includes a logic-friendly non-volatile memory unit;
The central processing unit, the sensor unit, the logic-friendly non-volatile memory unit, and the neural network engine are connected by a system bus,
The neural network engine,
Synapse array including a plurality of non-volatile synapses;
low driver;
criteria generator; and
a sensing circuit;
The synapse array, row driver, reference generator and sensing circuit are electrically coupled;
Each non-volatile synapse,
a first input signal line providing a first input signal from a row driver, wherein the reference generator provides a desired voltage level to the row driver;
a reference signal line for providing a reference signal from the row driver, wherein the reference generator provides the required voltage level to the row driver;
a first output line for conveying an output signal, the output signal being processed by the sensing circuit; and
a first cell for generating an output signal;
each cell,
a first upper select transistor having a gate electrically connected to the first input signal line; and
and a first resistive change element having one end connected in series to the first upper select transistor and the other end electrically connected to the reference signal line, wherein a value of the first resistive change element is programmed to change a magnitude of an output signal. possible-
Here, the drain of the first upper selection transistor of the first cell is electrically connected to the first output line,
The on-chip neural network system, characterized in that the neural network engine can execute data stored in the logic-friendly non-volatile memory without transmitting it to the outside of the chip.
According to claim 15,
The logic-friendly non-volatile memory unit is embedded in the neural network engine,
The on-chip neural network system, characterized in that the neural network engine can access data stored in the logic-friendly non-volatile memory without intervention of the central processing unit.
a central processing unit for controlling the elements of the chip;
a non-volatile neural network unit;
a sensor for providing an input signal to the non-volatile neural network; and
a memory unit,
The central processing unit, the sensor, the memory unit, and the non-volatile neural network unit are electrically coupled, and the non-volatile neural network unit controls operating parameters such as voltage and frequency of the central processing unit, the memory unit, and the sensor. A neural network chip characterized in that for controlling.