EP3740837B1 - Circuit de référence de tension avec réinitialisation à la mise sous tension - Google Patents

Circuit de référence de tension avec réinitialisation à la mise sous tension Download PDF

Info

Publication number
EP3740837B1
EP3740837B1 EP19701794.0A EP19701794A EP3740837B1 EP 3740837 B1 EP3740837 B1 EP 3740837B1 EP 19701794 A EP19701794 A EP 19701794A EP 3740837 B1 EP3740837 B1 EP 3740837B1
Authority
EP
European Patent Office
Prior art keywords
voltage
current
bipolar transistor
circuit
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP19701794.0A
Other languages
German (de)
English (en)
Other versions
EP3740837A1 (fr
Inventor
Carsten Hermann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3740837A1 publication Critical patent/EP3740837A1/fr
Application granted granted Critical
Publication of EP3740837B1 publication Critical patent/EP3740837B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • B60R16/03—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K2017/226—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in bipolar transistor switches

Definitions

  • the present invention relates to a voltage reference circuit with a combined power-on-reset signal.
  • FIG Figure 1 An example of a common voltage reference circuit according to the prior art that operates on the bandgap principle is shown in FIG Figure 1 shown. It is based on a current mirror circuit that is connected to a voltage input to which an operating voltage is applied.
  • the current mirror here comprises structurally identical MOS transistors M1, M2, the gates of which are connected to one another. In the case of a first of the MOS transistors M1, the gate is also connected to the drain connection.
  • This first MOS transistor M1 is connected with its drain connection directly to the collector of a first bipolar transistor Q1.
  • the emitter of the first bipolar transistor Q1 is connected to ground via a first resistor.
  • the base of the first bipolar transistor Q1 is connected to the base of a second bipolar transistor Q2.
  • the base of the second bipolar transistor Q2 is also connected to the collector.
  • the collector of the second bipolar transistor Q2 is connected to the drain connection of the MOS transistor M2 via a second resistor R2.
  • the circuit makes the reference voltage UBG available at the drain connection of the MOS transistor M2. With current mirrors it is possible to generate an identical current to an existing current or a current in a fixed ratio to the existing current.
  • bipolar or MOS transistors are used, which are identical in their structural shape or shaped in the same way, but are not of the same area.
  • the area ratios of the active areas, emitter areas or gate areas can be used to determine the ratio of the currents solely via their areas.
  • the two bipolar transistors are structurally identical, i.e. identical or identical in their design. However, they are not the same area.
  • the area of the bipolar transistor Q1 is greater by a factor of n than that of the bipolar transistor Q2, where n is a natural number greater than one. So n is the size ratio of Q1 / Q2.
  • the current mirror from M1 and M2 sets the operating point for both bipolar transistors at which both their base voltage UB and their collector currents IC1 and IC2 are the same.
  • k is the Boltzmann constant
  • T is the absolute temperature
  • q the charge of an electron.
  • the current IPTAT is strongly temperature dependent. It is proportional to the absolute temperature (English: proportional to absolute temperature (PTAT)). Within a temperature range of -40 ° C - 150 ° C, which is common in many applications, for example in the automotive sector, this current increases by a factor of two.
  • the base-emitter voltage of the bipolar transistors Q1 and Q2 is also highly temperature-dependent. It is halved in the said usual temperature range. Both the temperature curve of the base-emitter voltages and the temperature curve of the collector currents are almost linear. Therefore, by a suitable choice of the resistor R2 cause the sum UBG of the voltage drop UR2 over R2 (due to the collector current IC2 flowing through it) and the base-emitter voltage UBE2 to be independent of the temperature as a first approximation.
  • This total voltage UBG is referred to as the bandgap voltage. Regardless of the semiconductor technology used, it is around 1.25 V.
  • the in Figure 1 The voltage reference circuit shown can only work correctly from a certain operating voltage.
  • a drain-source voltage UDS2 of approx. 200 mV (drain-source saturation voltage) or more can be established for the MOS transistor M2.
  • the in Figure 1 The voltage reference circuit shown can therefore only work properly at an operating voltage of approx. 1.5 V.
  • the reference voltage is only valid above a certain minimum required operating voltage. Below this it is too low and cannot be used as a voltage reference for subsequent circuits, such as voltage regulators and / or comparators.
  • the increasing or decreasing operating voltage always passes through voltage ranges in which the reference voltage cannot reach its target value.
  • a power-on-reset circuit can be used to signal when the operating voltage provided is high enough. Often the issue here is also the availability of the voltage reference circuit so that the Operating voltage threshold, from which the operational readiness is signaled, cannot be set arbitrarily high.
  • Availability must be weighed against the safety margin. Since both circuits work independently of one another, there is a risk that the power-on-reset signal of the power-on-reset circuit could be released incorrectly while the operating voltage is running up or down. For example, at a certain rate of increase and level of the operating voltage and depending on the previous time course of the internal voltage accounts, the power-on-reset signal of the power-on-reset circuit can be incorrectly received despite the reference voltage of the voltage reference circuit being too low is released. This can cause malfunctions in other circuit parts of the ASIC.
  • the additional power-on-reset circuit requires an additional supply current.
  • Power-on-reset circuits according to the state of the art, which are based on the bandgap principle, can signal more or less precisely when the operating voltage, which is running up or down, exceeds or falls below a certain target value.
  • This power-on-reset threshold can make a statement about whether the available operating voltage is sufficient to operate a voltage reference circuit. Ultimately, however, it always boils down to combining two separate circuits, the actual voltage reference circuit and a circuit for generating the power-on reset. However, this harbors the risk that arises from the consideration of availability and the size of the safety margin between the largest operating voltage required for the voltage reference circuit and the smallest power-on reset threshold. Dynamic effects and finite accuracy of the power-on-reset threshold can make it necessary to additionally increase this safety margin.
  • the document US 2013/120026 A1 discloses a voltage reference circuit for providing a reference voltage for an application specific integrated circuit.
  • a voltage reference circuit according to claim 1 is proposed.
  • the voltage reference circuit is used to provide a reference voltage for an application-specific integrated circuit.
  • the voltage reference circuit comprises a voltage input for applying an operating voltage, a ground connection, a voltage output for providing a reference voltage and a signal output for providing a power-on reset signal.
  • the voltage reference circuit comprises an IPTAT circuit connected between the voltage input and the ground connection for generating a current proportional to the absolute temperature.
  • the voltage reference circuit is designed to provide the power-on-reset signal only when the reference voltage has reached a target value and if, in addition, a current flows in the IPTAT circuit with a current intensity that is one by a voltage value of the operating voltage and one Pulldown resistance value reaches or exceeds a certain minimum current strength.
  • the generation of a reference voltage and a power-on-reset signal is combined in one circuit.
  • the power-on-reset signal can therefore be generated depending on the fact that the reference voltage of the voltage reference circuit has reached a target value, with current flowing in the IPTAT circuit at the same time.
  • the power-on-reset signal of the present invention therefore reliably indicates the operational readiness of the voltage reference.
  • the adjustment of the reference voltage is also the adjustment of the power-on-reset threshold. Reaching the minimum operating voltage, which is necessary for the trouble-free operation of the voltage reference circuit, also allows a direct Statement about the correct start-up of the voltage reference circuit. While the operating voltage is running up and down, there are no high-resistance nodes in the signal path of the power-on-reset signal, which could lead to the power-on-reset signal signaling readiness for operation even though the reference voltage has not reached its target value.
  • the IPTAT circuit comprises a first and a second bipolar transistor with different current-voltage characteristics, the first bipolar transistor being larger than the second bipolar transistor, an IPTAT circuit resistor, a first current mirror, the maps the current flowing through the first bipolar transistor onto a first current path which comprises the second bipolar transistor, a second current mirror which is connected to the voltage input, and a sixth bipolar transistor and a fourth MOS transistor.
  • a drain connection of the fourth MOS transistor is connected to the second current mirror
  • a gate connection of the fourth MOS transistor is connected to a collector of the second bipolar transistor and a source connection of the fourth MOS transistor is connected to the bases of the first, of the second and the sixth bipolar transistor connected.
  • the voltage reference circuit furthermore comprises a second current path between the voltage input and the ground connection, wherein the second current path comprises a pulldown resistor with the pulldown resistance value and wherein the second current mirror maps a current flowing through the fourth MOS transistor onto the second current path, wherein the pulldown resistance value is selected such that a voltage drop across the resistor does not increase any further when the current flowing through the fourth MOS transistor is so high that the first and the second bipolar transistor conduct.
  • a pull-down resistor reliably pulls a node to ground when the current in the IPTAT circuit is not flows sufficiently (LOW level).
  • a size of the pull-down resistor determines the amount of current that is sufficient according to the circuit.
  • the voltage reference circuit can furthermore comprise a third current path between the voltage input and the ground connection and a third current mirror.
  • the third current path can include a third bipolar transistor, the third current mirror being able to map a further current flowing through the first bipolar transistor on the third current path in an enlarged manner.
  • the source connection of the fourth MOS transistor can be connected to a base of the third bipolar transistor.
  • the amount of current of the further current, for the dissipation of which the third bipolar transistor is suitable, is due to the coupling of the source connection of the fourth MOS transistor with the base of the third bipolar transistor to the amount of current proportional to the absolute temperature that is contained in the IPTAT -Circuit can flow limited. Since the enlarged image of the further current is always greater than this amount of current, a voltage can be applied to the collector of the third bipolar transistor, which can serve as an indicator that the reference voltage has reached its target value, provided that the enlarged image of the current is not pinched off.
  • the voltage reference circuit can therefore comprise a pull-down current source, which can carry precisely the amount of current proportional to the absolute temperature.
  • the voltage reference circuit can have a first Schmitt trigger, which is connected to a node on the second current path, wherein the node can be arranged between the current mirror and the pull-down resistor, and a second Schmitt trigger, which is connected to a further node may be connected to the third current path.
  • the further node can be arranged between the third current mirror and the third bipolar transistor.
  • the image of the current calls the Pull-down resistor produces a maximum voltage drop, so that the input of the first Schmitt trigger is pulled towards the positive operating voltage (HIGH level) through the image of the current and the output of this first Schmitt trigger thus delivers a HIGH level.
  • the enlarged image of the further current can also be used to pull the input of the second Schmitt trigger to a positive operating voltage (HIGH level) if this image of the further current is greater than the image of the current that the pull -Down current source that pulls the input of this second Schmitt trigger towards ground.
  • the voltage reference circuit can furthermore comprise a NAND gate, outputs of the first and second Schmitt triggers being able to be connected to inputs of the NAND gate and an output of the NAND gate to the signal output for providing a power-on reset Signal (RST) can be connected.
  • RST power-on reset Signal
  • the NAND gate combines the output signals of the two Schmitt triggers. In this way, a power-on reset signal is generated that reliably only assumes a LOW level (no reset) when the applied operating voltage is so high that the reference voltage has reached its target value.
  • a LOW level is then present at the signal output when the inputs of the first and the second Schmitt trigger each have a HIGH level.
  • the power-on-reset signal is set to the low level precisely when the reference voltage has just reached its target value and a current with sufficient amperage is also flowing in the IPTAT circuit.
  • the voltage reference circuit can furthermore have a fourth current path between the voltage input and the ground connection and a fourth Include current mirror.
  • the fourth current path can include a further resistor and a fourth bipolar transistor connected in series. The base and collector of the fourth bipolar transistor can be connected to one another.
  • the fourth current mirror can be designed to map the further current onto the fourth current path.
  • the voltage reference circuit can furthermore include a further node on the fourth current path, which is arranged between the fourth current mirror and the further resistor and is connected to the voltage output for providing a reference voltage.
  • the voltage reference circuit can furthermore comprise a fifth current mirror, which can be designed to map the image of the further current flowing through the fourth current path in a reduced size onto the third current path.
  • An RC filter can be connected to the voltage input to filter the operating voltage.
  • a timing element can advantageously be used to delay the power-on-reset signal.
  • An integrated circuit on a reference voltage circuit according to the present invention can be used, for example, in a vehicle.
  • An exemplary embodiment of the present invention is in the form of a voltage reference circuit 100 for providing a reference voltage for an application-specific integrated circuit (ASIC).
  • the voltage reference circuit 100 of this embodiment comprises a voltage input for applying an operating voltage and a voltage output for providing a reference voltage VBG.
  • the voltage reference circuit also includes a signal output for providing a power-on-reset signal RST.
  • the voltage reference circuit is designed to provide the power-on reset signal RST only when the reference voltage reaches its target value.
  • an RC filter is connected to the voltage input in the exemplary embodiment.
  • the RC filter can be omitted without departing from the present invention.
  • the voltage reference circuit also includes two Schmitt triggers X1, X2 and a NAND gate X3.
  • One input of one Schmitt trigger X1 is connected to a node, the first node.
  • One input of the other Schmitt trigger X2 is connected to a further node, the second node.
  • the outputs of the Schmitt triggers X1, X2 are connected to the inputs of the NAND gate X3.
  • One output of the NAND gate X3 is connected to the signal output.
  • the IPTAT circuit of the exemplary embodiment of the invention comprises an IPTAT circuit resistor R1 and a first, a second, a third and a fourth MOS transistor M1, M2, M3, M4.
  • the IPTAT circuit also includes first, second and sixth bipolar transistors Q1, Q2 and Q6.
  • the first and second bipolar transistors Q1, Q2 differ in size. The size ratio is preferably rational, more preferably natural.
  • the first and second MOS transistors M1, M2 have the same constitution.
  • the emitter of the second bipolar transistor Q2 is connected directly to ground in the exemplary embodiment.
  • the emitter of the first bipolar transistor Q1 is connected to ground via the IPTAT circuit resistor R1.
  • the source connection of the first MOS transistor M1, the source connection of the second MOS transistor M2 and the source connection of the third MOS transistor M3 are connected to the operating voltage input in the exemplary embodiment.
  • the drain connection of the first MOS transistor M1 is connected to the collector of the first bipolar transistor Q1.
  • the drain connection of the second MOS transistor M2 is connected directly to the collector of the second bipolar transistor Q2.
  • the drain connection of the third MOS transistor M3 is connected to the drain connection of the fourth MOS transistor M4.
  • the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected to a third node in the exemplary embodiment.
  • the drain connection of the first MOS transistor M1 is connected to the third node and the drain connection of the third MOS transistor M3 is connected to the gate of the third MOS transistor M3.
  • the base of the first bipolar transistor Q1 and the base of the second bipolar transistor Q2 are connected to a fourth node in the exemplary embodiment.
  • the source connection of the fourth MOS transistor M4 is connected to the fourth node and the gate of the fourth MOS transistor M4 is connected to the collector of the second bipolar transistor Q2 in the exemplary embodiment.
  • the voltage reference circuit furthermore comprises a second current path with a fifth MOS transistor M5, which forms a second current mirror with the third MOS transistor M3, and a pulldown resistor R3.
  • the source connection of the fifth MOS transistor M5 is connected to the operating voltage input.
  • the gate of the fifth MOS transistor M5 is connected to the gate of the third MOS transistor M3.
  • the drain connection of the fifth MOS transistor M5 is connected to the first node.
  • the pull-down resistor R3 is connected between the first node and ground. A current intensity of the current flowing in the IPTAT circuit must exceed a minimum current intensity dependent on the voltage value of the operating voltage and the pulldown resistance value of the pulldown resistor R3 so that a voltage can build up at the first node.
  • the voltage reference circuit furthermore comprises a third current path with a third bipolar transistor Q3, a sixth MOS transistor M6 and a seventh MOS transistor M7.
  • the source connection of the sixth MOS transistor M6 is connected to the operating voltage input.
  • the sixth MOS transistor M6 forms a second current mirror with the first MOS transistor M1.
  • the drain connection of the sixth MOS transistor M6 is connected to the source connection of the seventh MOS transistor M7.
  • the drain connection of the seventh MOS transistor M7 is connected to the second node.
  • the collector of the third bipolar transistor Q3 is also connected to the second node.
  • the emitter of the third bipolar transistor Q3 is connected to ground in this embodiment.
  • the base of the third bipolar transistor Q3 is connected to the fourth node in this embodiment.
  • the voltage reference circuit can comprise a fourth current path with yet another node, the fifth node, a third resistor R4, a fourth bipolar transistor Q4 and an eighth and a ninth MOS transistor M8, M9.
  • the source connection of the eighth MOS transistor M8 can be connected to the operating voltage input.
  • the gate of the eighth MOS transistor M8 can be connected to the third node.
  • the eighth MOS transistor M8 forms a fourth current mirror with the first MOS transistor M1.
  • the drain connection of the eighth MOS transistor M8 can be connected to the source connection of the ninth MOS transistor M9.
  • the gate of the ninth MOS transistor M9 can be connected to the gate of the seventh MOS transistor M7.
  • the seventh MOS transistor M7 forms a fifth current mirror with the ninth MOS transistor M9.
  • the drain connection of the ninth MOS transistor M9 can be connected to the fifth node.
  • the collector of the fourth bipolar transistor Q4 can be connected to the fifth node via the third resistor R4.
  • the base of the fourth bipolar transistor Q4 may be connected to the collector of the fourth bipolar transistor Q4.
  • the emitter of the fourth bipolar transistor Q4 can be connected to the ground.
  • the reference voltage output VBG and the gate of the ninth MOS transistor M9 can be connected to the fifth node.
  • the voltage reference circuit further comprises a fourth resistor R5, a fifth and a sixth bipolar transistor Q5, Q6 and a tenth and an eleventh MOS transistor M10, M11.
  • the drain connection of the eleventh MOS transistor M11 is connected directly to the operating voltage input and the drain connection of the tenth MOS transistor M10 is connected to the operating voltage input via the fourth resistor R5.
  • the sources of the tenth and eleventh MOS transistors M10, M11 are connected to the collectors of the fifth and sixth bipolar transistors Q5, Q6, respectively.
  • the emitters of the fifth and sixth bipolar transistors Q5, Q6 are connected to the ground.
  • the base of the fifth bipolar transistor Q5 is connected to the collector of the fifth bipolar transistor Q5 and the base of the sixth bipolar transistor Q6 is connected to the collector of the sixth bipolar transistor Q6.
  • the base of the sixth bipolar transistor Q6 is still connected to the fourth node.
  • An integrated circuit with a reference voltage circuit according to the present invention can be used, for example, in a vehicle.
  • a voltage reference circuit reliably signals via its own inherent power-on-reset signal when the operating voltage made available to it is just high enough that its reference voltage target value has just been reached.
  • neither a second, internal or external reference voltage nor a separate power-on-reset circuit are necessary for this.
  • the function of the in Figure 2 shown embodiment of the invention proposed voltage reference circuit described in more detail.
  • the two bipolar transistors Q1 and Q2, the IPTAT circuit resistor R1 and the current mirror formed from M1 and M2 cause collector currents IC1, IC2 and drain-source currents IDS1, IDS2 to be proportional to the absolute temperature corresponding to those of the circuit in Figure 1 to adjust:
  • the base voltage UB of Q1 and Q2 is regulated by M4. If the current IPTAT is too small, the collector current IC1 of Q1 is higher than that of Q2 due to its area n is greater than that of Q2, so that the gate of M4 is pulled up by the MOS transistor M2 and the current IPTAT increases . If the current IPTAT is too high, the collector current IC1 is lower than that of Q2 due to the negative current feedback from Q1 (caused by the IPTAT circuit resistance R1), so that the gate of M4 is pulled down by the bipolar transistor Q2 and the current IPTAT decreases. With the same dimensioning, there is approximately the same base voltage UB as in the circuit in FIG Figure 1 one.
  • a start-up circuit is advantageous for starting up the voltage reference circuit.
  • the start-up circuit is formed by the resistor R5, the MOS transistors M10, M11 and the bipolar transistors Q5, Q6.
  • the current IDS10 flows through the resistor R5 and the MOS transistors M10 and Q5.
  • the resistor R5 must be dimensioned so that IDS11 ⁇ IPTAT applies over the entire temperature range.
  • collector currents IC1 and IC2 also flow through the bipolar transistors Q1 and Q2.
  • the collector current IC1 of Q1 is greater by a factor of n Area higher than that of Q2, so that the gate of M4 is pulled up by the MOS transistor M2 and the current IPTAT continues to rise until the operating point described above is set and the bandgap voltage of approx. 1.25 V results .
  • the MOS transistor M4 has to supply the collector current for the sixth bipolar transistor Q6 and the base currents for the first, second, third and sixth bipolar transistors Q1, Q2, Q3, Q6. This is only possible when the operating voltage is so high that the third and fourth MOS transistors M3, M4 and the base-emitter paths of the first, second and sixth bipolar transistors Q1, Q2 and Q6 are conducting.
  • the voltage drop across the pulldown resistor R3 does not increase any further.
  • the voltage drop across the pulldown resistor R3 can also only increase as far as the drain-source saturation voltage of the fifth MOS transistor M5 is not undershot, so that the fifth MOS transistor M5 can still work as a current source.
  • the voltage drop across the pull-down resistor R3 can accordingly come close to the operating voltage.
  • a resistance value for the pulldown resistor R3 can be found, the voltage drop across it at the output of the Schmitt trigger X1 causing a logic high signal if the current provided by the fourth MOS transistor M4 is sufficient for the bipolar transistors Q1 and Q2 begin to conduct and gate voltage regulation begins.
  • the voltage drop across R3 is correspondingly due to the temperature dependence of IPTAT is also temperature dependent. It can therefore be advantageous to insert a resistor R6 in the collector path of Q6, which limits the collector current of Q6 at high temperatures. This can allow a larger range of values for the pulldown resistor R3
  • the base of Q6 would still be connected to the source connection of M11 and the collector of Q6 would be connected to the source connection of M11 via the resistor R6.
  • the pulldown resistor R3 reliably pulls the input of one Schmitt trigger X1 to ground and its output carries a logic low signal.
  • the following NAND gate X3 then has a logic high signal at its output.
  • the outcome of the NAND gate X3 is the power-on reset signal RST.
  • the voltage reference circuit proposed here signals its operational readiness via the power-on reset signal RST when the target value of the reference voltage is reached, depending on the applied operating voltage, with a low level. If the operating voltage is too low, the RST signal is reliably high.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Electronic Switches (AREA)
  • Control Of Electrical Variables (AREA)

Claims (10)

  1. Circuit de référence de tension (100) permettant de fournir une tension de référence (VBG) pour un circuit intégré spécifique à une application, comprenant : une entrée de tension pour appliquer une tension de service, une borne de masse, une sortie de tension pour fournir une tension de référence (VBG) et une sortie de signal pour fournir un signal de réinitialisation à la mise sous tension (RST), le circuit de référence de tension (100) comprenant un circuit IPTAT connecté entre l'entrée de tension et la borne de masse pour générer un courant proportionnel à la température absolue,
    caractérisé en ce que le circuit de référence de tension (100) est réalisé pour fournir le signal de réinitialisation à la mise sous tension (RST) uniquement si la tension de référence a atteint une valeur cible et si en plus dans le circuit IPTAT passe un courant d'une intensité de courant qui atteint ou dépasse une intensité de courant minimale déterminée par une valeur de tension de la tension de service et une valeur de résistance de tirage vers le bas.
  2. Circuit de référence de tension (100) selon la revendication 1, dans lequel le circuit IPTAT comprend un premier et un deuxième transistor bipolaire (Q1, Q2) avec différentes courbes caractéristiques courant/tension, le premier transistor bipolaire (Q1) étant plus grand que le deuxième transistor bipolaire (Q2), une résistance de circuit IPTAT (R1), l'émetteur du premier transistor bipolaire (Q1) étant relié à la borne de masse par l'intermédiaire de la résistance de circuit IPTAT (R1), et l'émetteur du deuxième transistor bipolaire (Q2) étant relié directement à la borne de masse, un premier miroir de courant (M1, M2) qui mappe le courant passant par le premier transistor bipolaire (Q1) sur un premier trajet de courant qui comprend le deuxième transistor bipolaire (Q2), un deuxième miroir de courant (M3, M5), un quatrième transistor MOS (M4) et un sixième transistor bipolaire (Q6), une borne de drain du quatrième transistor MOS (M4) étant reliée à l'entrée de tension, une borne de grille du quatrième transistor MOS (M4) étant reliée à un collecteur du deuxième transistor bipolaire (Q2), et une borne de source du quatrième transistor MOS (M4) étant reliée aux bases du premier, du deuxième et du sixième transistor bipolaire (Q1, Q2, Q6), dans lequel le circuit de référence de tension (100) comprend en outre un deuxième trajet de courant entre l'entrée de tension et la borne de masse, un émetteur du sixième transistor bipolaire (Q6) étant relié à la borne de masse, et un collecteur du sixième transistor bipolaire (Q6) étant relié à la base du sixième transistor bipolaire (Q6), le deuxième trajet de courant comprenant une résistance de tirage vers le bas (R3) ayant la valeur de résistance de tirage vers le bas, et le deuxième miroir de courant (M3, M5) mappant un courant passant par le quatrième transistor MOS (M4) sur le deuxième trajet de courant, la valeur de résistance de tirage vers le bas (R3) étant sélectionnée de telle sorte qu'une chute de tension à travers la résistance de tirage vers le bas (R3) n'augmente plus si le courant passant par le quatrième transistor MOS (M4) est si élevé que le premier et le deuxième transistor bipolaire (Q1, Q2) sont conducteurs.
  3. Circuit de référence de tension (100) selon la revendication 2, comprenant en outre un troisième trajet de courant entre l'entrée de tension et la borne de masse et un troisième miroir de courant (M1, M6), le troisième trajet de courant comprenant un troisième transistor bipolaire (Q3), le troisième miroir de courant (M1, M6) mappant de manière augmentée un autre courant passant par le premier transistor bipolaire (Q1) sur le troisième trajet de courant, et la borne de source du quatrième transistor MOS (M4) étant reliée à une base du troisième transistor bipolaire (Q3).
  4. Circuit de référence de tension (100) selon la revendication 3, comprenant en outre une première bascule de Schmitt (X1) qui est reliée à un premier nœud sur le deuxième trajet de courant, le premier nœud étant disposé entre le miroir de courant (M3, M5) et la résistance de tirage vers le bas (R3), et une deuxième bascule de Schmitt (X2) qui est reliée à un deuxième nœud sur le troisième trajet de courant, le deuxième nœud étant disposé entre le troisième miroir de courant (M1, M6) et le troisième transistor bipolaire (Q3).
  5. Circuit de référence de tension (100) selon la revendication 4, comprenant en outre une grille NAND, les sorties de la première et de la deuxième bascule de Schmitt (X1, X2) étant reliées aux entrées de la grille NAND, et une sortie de la grille NAND étant reliée à la sortie de signal pour fournir un signal de réinitialisation à la mise sous tension (RST).
  6. Circuit de référence de tension (100) selon la revendication 3, 4 ou 5, comprenant en outre un quatrième trajet de courant entre l'entrée de tension et la borne de masse et un quatrième miroir de courant (M1, M8), le quatrième trajet de courant comprenant une autre résistance (R4) et un quatrième transistor bipolaire (Q4) connectés en série, la base et le collecteur du quatrième transistor bipolaire (Q4) étant reliés l'un à l'autre, et le quatrième miroir de courant (M1, M8) mappant l'autre courant sur le quatrième trajet de courant, comprenant en outre encore un autre nœud sur le quatrième trajet de courant qui est disposé entre le quatrième miroir de courant (M1, M8) et l'autre résistance (R4) et relié à la sortie de tension pour fournir une tension de référence (VBG).
  7. Circuit de référence de tension (100) selon la revendication 6, comprenant en outre un cinquième miroir de courant (M9, M7) qui mappe de manière diminuée sur le troisième trajet de courant le mappage de l'autre courant passant par le quatrième trajet de courant.
  8. Circuit de référence de tension selon l'une quelconque des revendications précédentes, comprenant en outre un filtre RC pour filtrer la tension de service, le filtre RC étant connecté à l'entrée de tension.
  9. Circuit de référence de tension selon l'une quelconque des revendications précédentes, comprenant en outre un relais temporisateur pour retarder le signal de réinitialisation à la mise sous tension.
  10. Véhicule comprenant un circuit intégré sur un circuit de tension de référence selon l'une quelconque des revendications précédentes.
EP19701794.0A 2018-01-18 2019-01-16 Circuit de référence de tension avec réinitialisation à la mise sous tension Active EP3740837B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018200785.3A DE102018200785A1 (de) 2018-01-18 2018-01-18 Spannungsreferenz-Schaltkreis mit kombiniertem Power-on-Reset
PCT/EP2019/050988 WO2019141697A1 (fr) 2018-01-18 2019-01-16 Circuit de référence de tension avec réinitialisation à la mise sous tension

Publications (2)

Publication Number Publication Date
EP3740837A1 EP3740837A1 (fr) 2020-11-25
EP3740837B1 true EP3740837B1 (fr) 2021-12-29

Family

ID=65234532

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19701794.0A Active EP3740837B1 (fr) 2018-01-18 2019-01-16 Circuit de référence de tension avec réinitialisation à la mise sous tension

Country Status (5)

Country Link
US (1) US11061426B2 (fr)
EP (1) EP3740837B1 (fr)
JP (1) JP6990318B2 (fr)
DE (1) DE102018200785A1 (fr)
WO (1) WO2019141697A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114785331B (zh) * 2022-04-01 2023-09-19 无锡力芯微电子股份有限公司 可调式高精度复位电路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020141121A1 (en) * 2001-03-27 2002-10-03 Brohlin Paul L. Supply independent low quiescent current undervoltage lockout circuit
DE69902891T2 (de) * 1999-06-22 2003-01-23 Alcatel Sa Referenzspannungsgenerator mit Überwachungs- und Anlaufschaltung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4543582B2 (ja) * 2001-06-07 2010-09-15 株式会社デンソー 回路装置及び回路装置の調整データ設定方法
KR100939291B1 (ko) 2005-02-24 2010-01-28 후지쯔 가부시끼가이샤 기준 전압 발생 회로
US20090121699A1 (en) * 2007-11-08 2009-05-14 Jae-Boum Park Bandgap reference voltage generation circuit in semiconductor memory device
JP5607963B2 (ja) * 2010-03-19 2014-10-15 スパンション エルエルシー 基準電圧回路および半導体集積回路
US8723554B2 (en) 2011-11-10 2014-05-13 Aeroflex Colorado Springs Inc. High-stability reset circuit for monitoring supply undervoltage and overvoltage
US9356569B2 (en) 2013-10-18 2016-05-31 Freescale Semiconductor, Inc. Ready-flag circuitry for differential amplifiers
JP2016114496A (ja) * 2014-12-16 2016-06-23 株式会社デンソー 異常監視回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69902891T2 (de) * 1999-06-22 2003-01-23 Alcatel Sa Referenzspannungsgenerator mit Überwachungs- und Anlaufschaltung
US20020141121A1 (en) * 2001-03-27 2002-10-03 Brohlin Paul L. Supply independent low quiescent current undervoltage lockout circuit

Also Published As

Publication number Publication date
EP3740837A1 (fr) 2020-11-25
WO2019141697A1 (fr) 2019-07-25
JP2021510879A (ja) 2021-04-30
US20200379498A1 (en) 2020-12-03
JP6990318B2 (ja) 2022-01-12
US11061426B2 (en) 2021-07-13
DE102018200785A1 (de) 2019-07-18

Similar Documents

Publication Publication Date Title
DE102006003123B4 (de) Bezugsspannungsschaltkreise
DE102018200704B4 (de) Elektrische Schaltung für den sicheren Hoch- und Runterlauf eines Verbrauchers
DE102004007620B4 (de) Vorladeschaltkreis für die Inbetriebnahme eines DC-DC-Wandlers zur Spannungserhöhung
DE102017122144A1 (de) Schaltvorrichtung und Verfahren
DE102014103597A1 (de) Flipped-gate-spannungsreferenz und verfahren zu ihrer nutzung
EP0496018B1 (fr) Circuit intégré servant à générer un signal de remise à zéro
EP0591561A1 (fr) Circuit intégré pour générer un signal de remise à l'état initial
EP3740837B1 (fr) Circuit de référence de tension avec réinitialisation à la mise sous tension
EP1944674A1 (fr) Circuit destiné à la production d'une valeur de référence de tension ou de courant compensée par température
EP0499673A1 (fr) Circuit de commande pour un générateur de tension d'un substrat
DE2636198C3 (de) Schaltungsanordnung zum Konstanthalten einer Spannung zwischen einer Eingangsund einer Ausgangsklemme
DE102014013032A1 (de) Erzeugung eines Stroms mit umgekehrter Versorgungsspannungsproportionalität
DE2745302B1 (de) Schaltungsanordnung zur Kontrolle der Versorgungsspannung fuer vorzugsweise integrierte Schaltkreise
EP0640259B1 (fr) Bascule de schmitt
DE10237122B4 (de) Schaltung und Verfahren zur Einstellung des Arbeitspunkts einer BGR-Schaltung
DE102014111900A1 (de) Oszillatorschaltung
DE10335018A1 (de) Vorrichtung zum Aufladen einer Batterie
DE10255582B4 (de) Spannungsregler mit Einschaltschutzschaltung
DE102013111083A1 (de) Verfahren und schaltung für einen spannungsreferenz- und vorstromgenerator mit geringem stromverbrauch
DE10223562A1 (de) Integrierte Schaltungsanordnung mit einer kaskodierten Stromquelle und einer Einstellschaltung zur Einstellung des Arbeitspunkts der kaskodierten Stromquelle
DE102017127478B4 (de) Vorrichtung und Verfahren zur Erzeugung einer Referenzspannung
DE4012847A1 (de) Integrierbare schaltungsanordnung
DE102021202149A1 (de) Spannungsreglerschaltung und Verfahren zur Bereitstellung einer geregelten Spannung
DE19530737A1 (de) Schaltungsanordnung zum Liefern eines konstanten Stromes
DE1283892B (de) Kaskodenschaltung mit Transistoren

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20200818

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20210929

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502019003108

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1459173

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220115

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220329

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20211229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220329

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220330

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220429

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20220429

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502019003108

Country of ref document: DE

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20220131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220116

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220131

26N No opposition filed

Effective date: 20220930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220131

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220116

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230123

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20230131

Year of fee payment: 5

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20230116

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230116

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20211229

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240322

Year of fee payment: 6